adrv9009: A10SOC: Initial commit
Adrian Costina
parent
a5b7699bd5
commit
f12bd3d246
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####################################################################################
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## Copyright 2018(c) Analog Devices, Inc.
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## Auto-generated, do not modify!
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####################################################################################
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PROJECT_NAME := adrv9009_a10soc
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M_DEPS += ../common/adrv9009_qsys.tcl
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M_DEPS += ../../common/a10soc/a10soc_system_qsys.tcl
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M_DEPS += ../../common/a10soc/a10soc_system_assign.tcl
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M_DEPS += ../../common/a10soc/a10soc_plddr4_dacfifo_qsys.tcl
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M_DEPS += ../../common/a10soc/a10soc_plddr4_assign.tcl
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LIB_DEPS += altera/adi_jesd204
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LIB_DEPS += altera/avl_dacfifo
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LIB_DEPS += axi_adrv9009
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LIB_DEPS += axi_dmac
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LIB_DEPS += util_cpack
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LIB_DEPS += util_upack
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include ../../scripts/project-altera.mk
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create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}]
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create_clock -period "4.069 ns" -name ref_clk0 [get_ports {ref_clk0}]
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create_clock -period "4.069 ns" -name ref_clk1 [get_ports {ref_clk1}]
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derive_pll_clocks
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derive_clock_uncertainty
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set_false_path -to [get_registers *sys_gpio_bd|readdata[12]*]
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set_false_path -to [get_registers *sys_gpio_bd|readdata[13]*]
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set_false_path -from [get_registers *altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out*]
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@ -0,0 +1,139 @@
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source ../../scripts/adi_env.tcl
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source ../../scripts/adi_project_alt.tcl
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adi_project_altera adrv9009_a10soc
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source $ad_hdl_dir/projects/common/a10soc/a10soc_system_assign.tcl
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source $ad_hdl_dir/projects/common/a10soc/a10soc_plddr4_assign.tcl
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# adrv9009
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set_location_assignment PIN_N29 -to ref_clk0 ; ## D04 FMC_HPC_GBTCLK0_M2C_P (NC)
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set_location_assignment PIN_N28 -to "ref_clk0(n)" ; ## D05 FMC_HPC_GBTCLK0_M2C_N (NC)
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set_location_assignment PIN_R29 -to ref_clk1 ; ## B20 FMC_HPC_GBTCLK1_M2C_P
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set_location_assignment PIN_R28 -to "ref_clk1(n)" ; ## B21 FMC_HPC_GBTCLK1_M2C_N
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set_location_assignment PIN_R33 -to rx_serial_data[0] ; ## A02 FMC_HPC_DP1_M2C_P
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set_location_assignment PIN_R32 -to "rx_serial_data[0](n)" ; ## A03 FMC_HPC_DP1_M2C_N
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set_location_assignment PIN_P35 -to rx_serial_data[1] ; ## A06 FMC_HPC_DP2_M2C_P
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set_location_assignment PIN_P34 -to "rx_serial_data[1](n)" ; ## A07 FMC_HPC_DP2_M2C_N
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set_location_assignment PIN_T31 -to rx_serial_data[2] ; ## C06 FMC_HPC_DP0_M2C_P
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set_location_assignment PIN_T30 -to "rx_serial_data[2](n)" ; ## C07 FMC_HPC_DP0_M2C_N
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set_location_assignment PIN_P31 -to rx_serial_data[3] ; ## A10 FMC_HPC_DP3_M2C_P
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set_location_assignment PIN_P30 -to "rx_serial_data[3](n)" ; ## A11 FMC_HPC_DP3_M2C_N
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set_location_assignment PIN_M39 -to tx_serial_data[0] ; ## A22 FMC_HPC_DP1_C2M_P (tx_serial_data_p[0])
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set_location_assignment PIN_M38 -to "tx_serial_data[0](n)" ; ## A23 FMC_HPC_DP1_C2M_N (tx_serial_data_n[0])
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set_location_assignment PIN_L37 -to tx_serial_data[1] ; ## A26 FMC_HPC_DP2_C2M_P (tx_serial_data_p[3])
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set_location_assignment PIN_L36 -to "tx_serial_data[1](n)" ; ## A27 FMC_HPC_DP2_C2M_N (tx_serial_data_n[3])
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set_location_assignment PIN_N37 -to tx_serial_data[2] ; ## C02 FMC_HPC_DP0_C2M_P (tx_serial_data_p[2])
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set_location_assignment PIN_N36 -to "tx_serial_data[2](n)" ; ## C03 FMC_HPC_DP0_C2M_N (tx_serial_data_n[2])
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set_location_assignment PIN_K39 -to tx_serial_data[3] ; ## A30 FMC_HPC_DP3_C2M_P (tx_serial_data_p[1])
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set_location_assignment PIN_K38 -to "tx_serial_data[3](n)" ; ## A31 FMC_HPC_DP3_C2M_N (tx_serial_data_n[1])
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set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to rx_serial_data
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set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to tx_serial_data
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set_instance_assignment -name IO_STANDARD LVDS -to ref_clk0
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set_instance_assignment -name IO_STANDARD LVDS -to ref_clk1
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set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_serial_data
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set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_serial_data
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# Merge RX and TX into single transceiver
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for {set i 0} {$i < 4} {incr i} {
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set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_${i} -to rx_serial_data[${i}]
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set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_${i} -to tx_serial_data[${i}]
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}
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set_location_assignment PIN_C14 -to rx_sync ; ## G09 FMC_HPC_LA03_P
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set_location_assignment PIN_D14 -to rx_sync(n) ; ## G10 FMC_HPC_LA03_N
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set_location_assignment PIN_E3 -to rx_os_sync ; ## G27 FMC_HPC_LA25_P (Sniffer)
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set_location_assignment PIN_F3 -to rx_os_sync(n) ; ## G28 FMC_HPC_LA25_N (Sniffer)
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set_location_assignment PIN_C13 -to tx_sync ; ## H07 FMC_HPC_LA02_P
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set_location_assignment PIN_D13 -to tx_sync(n) ; ## H08 FMC_HPC_LA02_N
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set_location_assignment PIN_G14 -to sysref ; ## G06 FMC_HPC_LA00_CC_P
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set_location_assignment PIN_H14 -to sysref(n) ; ## G07 FMC_HPC_LA00_CC_N
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set_location_assignment PIN_E1 -to tx_sync_1 ; ## H28 FMC_HPC_LA24_P
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set_location_assignment PIN_E2 -to tx_sync_1(n) ; ## H29 FMC_HPC_LA24_N
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set_instance_assignment -name IO_STANDARD LVDS -to rx_sync
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set_instance_assignment -name IO_STANDARD LVDS -to rx_os_sync
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set_instance_assignment -name IO_STANDARD LVDS -to tx_sync
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set_instance_assignment -name IO_STANDARD LVDS -to sysref
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set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to tx_sync
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set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to sysref
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set_location_assignment PIN_A13 -to spi_csn_ad9528 ; ## D15 FMC_HPC_LA09_N
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set_location_assignment PIN_A12 -to spi_csn_adrv9009 ; ## D14 FMC_HPC_LA09_P
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set_location_assignment PIN_A9 -to spi_clk ; ## H13 FMC_HPC_LA07_P
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set_location_assignment PIN_B9 -to spi_mosi ; ## H14 FMC_HPC_LA07_N
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set_location_assignment PIN_B11 -to spi_miso ; ## G12 FMC_HPC_LA08_P
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set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_csn_ad9528
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set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_csn_adrv9009
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set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_clk
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set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_mosi
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set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_miso
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set_location_assignment PIN_F2 -to ad9528_reset_b ; ## D26 FMC_HPC_LA26_P
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set_location_assignment PIN_G2 -to ad9528_sysref_req ; ## D27 FMC_HPC_LA26_N
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set_location_assignment PIN_J11 -to adrv9009_tx1_enable ; ## D17 FMC_HPC_LA13_P
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set_location_assignment PIN_J9 -to adrv9009_tx2_enable ; ## C18 FMC_HPC_LA14_P
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set_location_assignment PIN_K11 -to adrv9009_rx1_enable ; ## D18 FMC_HPC_LA13_N
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set_location_assignment PIN_J10 -to adrv9009_rx2_enable ; ## C19 FMC_HPC_LA14_N
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set_location_assignment PIN_C9 -to adrv9009_test ; ## H16 FMC_HPC_LA11_P
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set_location_assignment PIN_H12 -to adrv9009_reset_b ; ## H10 FMC_HPC_LA04_P
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set_location_assignment PIN_H13 -to adrv9009_gpint ; ## H11 FMC_HPC_LA04_N
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set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9528_reset_b
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set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9528_sysref_req
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set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_tx1_enable
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set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_tx2_enable
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set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_rx1_enable
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set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_rx2_enable
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set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_test
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set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_reset_b
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set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpint
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# single ended default
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set_location_assignment PIN_D4 -to adrv9009_gpio[0] ; ## H19 FMC_HPC_LA15_P
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set_location_assignment PIN_D5 -to adrv9009_gpio[1] ; ## H20 FMC_HPC_LA15_N
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set_location_assignment PIN_D6 -to adrv9009_gpio[2] ; ## G18 FMC_HPC_LA16_P
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set_location_assignment PIN_E6 -to adrv9009_gpio[3] ; ## G19 FMC_HPC_LA16_N
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set_location_assignment PIN_C2 -to adrv9009_gpio[4] ; ## H25 FMC_HPC_LA21_P
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set_location_assignment PIN_D3 -to adrv9009_gpio[5] ; ## H26 FMC_HPC_LA21_N
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set_location_assignment PIN_G7 -to adrv9009_gpio[6] ; ## C22 FMC_HPC_LA18_CC_P
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set_location_assignment PIN_H7 -to adrv9009_gpio[7] ; ## C23 FMC_HPC_LA18_CC_N
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set_location_assignment PIN_G4 -to adrv9009_gpio[8] ; ## G25 FMC_HPC_LA22_N (LVDS_1N)
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set_location_assignment PIN_G5 -to adrv9009_gpio[9] ; ## H22 FMC_HPC_LA19_P (LVDS_2P)
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set_location_assignment PIN_G6 -to adrv9009_gpio[10] ; ## H23 FMC_HPC_LA19_N (LVDS_2N)
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set_location_assignment PIN_C3 -to adrv9009_gpio[11] ; ## G21 FMC_HPC_LA20_P (LVDS_3P)
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set_location_assignment PIN_C4 -to adrv9009_gpio[12] ; ## G22 FMC_HPC_LA20_N (LVDS_3N)
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set_location_assignment PIN_N13 -to adrv9009_gpio[13] ; ## G16 FMC_HPC_LA12_N (LVDS_4N)
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set_location_assignment PIN_M12 -to adrv9009_gpio[14] ; ## G15 FMC_HPC_LA12_P (LVDS_4P)
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set_location_assignment PIN_F4 -to adrv9009_gpio[15] ; ## G24 FMC_HPC_LA22_P (LVDS_1P)
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set_location_assignment PIN_B10 -to adrv9009_gpio[16] ; ## C11 FMC_HPC_LA06_N (LVDS_5N)
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set_location_assignment PIN_A10 -to adrv9009_gpio[17] ; ## C10 FMC_HPC_LA06_P (LVDS_5P)
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set_location_assignment PIN_F14 -to adrv9009_gpio[18] ; ## D12 FMC_HPC_LA05_N
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set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpio[0]
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set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpio[1]
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set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpio[2]
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set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpio[3]
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set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpio[4]
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set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpio[5]
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set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpio[6]
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set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpio[7]
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set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpio[8]
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set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpio[9]
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set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpio[10]
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set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpio[11]
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set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpio[12]
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set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpio[13]
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set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpio[14]
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set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpio[15]
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set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpio[16]
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set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpio[17]
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set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpio[18]
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execute_flow -compile
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@ -0,0 +1,11 @@
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set dac_fifo_name avl_adrv9009_tx_fifo
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set dac_fifo_address_width 10
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set dac_data_width 128
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set dac_dma_data_width 128
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source $ad_hdl_dir/projects/common/a10soc/a10soc_system_qsys.tcl
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source $ad_hdl_dir/projects/common/a10soc/a10soc_plddr4_dacfifo_qsys.tcl
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source ../common/adrv9009_qsys.tcl
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@ -0,0 +1,328 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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// clock and resets
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input sys_clk,
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input sys_resetn,
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// hps-ddr4 (32)
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input hps_ddr_ref_clk,
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output [ 0:0] hps_ddr_clk_p,
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output [ 0:0] hps_ddr_clk_n,
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output [ 16:0] hps_ddr_a,
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output [ 1:0] hps_ddr_ba,
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output [ 0:0] hps_ddr_bg,
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output [ 0:0] hps_ddr_cke,
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output [ 0:0] hps_ddr_cs_n,
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output [ 0:0] hps_ddr_odt,
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output [ 0:0] hps_ddr_reset_n,
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output [ 0:0] hps_ddr_act_n,
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output [ 0:0] hps_ddr_par,
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input [ 0:0] hps_ddr_alert_n,
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inout [ 3:0] hps_ddr_dqs_p,
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inout [ 3:0] hps_ddr_dqs_n,
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inout [ 31:0] hps_ddr_dq,
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inout [ 3:0] hps_ddr_dbi_n,
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input hps_ddr_rzq,
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// pl-ddr4
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input sys_ddr_ref_clk,
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output [ 0:0] sys_ddr_clk_p,
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output [ 0:0] sys_ddr_clk_n,
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output [ 16:0] sys_ddr_a,
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output [ 1:0] sys_ddr_ba,
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output [ 0:0] sys_ddr_bg,
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output [ 0:0] sys_ddr_cke,
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output [ 0:0] sys_ddr_cs_n,
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output [ 0:0] sys_ddr_odt,
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output [ 0:0] sys_ddr_reset_n,
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output [ 0:0] sys_ddr_act_n,
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output [ 0:0] sys_ddr_par,
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input [ 0:0] sys_ddr_alert_n,
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inout [ 7:0] sys_ddr_dqs_p,
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inout [ 7:0] sys_ddr_dqs_n,
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inout [ 63:0] sys_ddr_dq,
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inout [ 7:0] sys_ddr_dbi_n,
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input sys_ddr_rzq,
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// hps-ethernet
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input [ 0:0] hps_eth_rxclk,
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input [ 0:0] hps_eth_rxctl,
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input [ 3:0] hps_eth_rxd,
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output [ 0:0] hps_eth_txclk,
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output [ 0:0] hps_eth_txctl,
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output [ 3:0] hps_eth_txd,
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output [ 0:0] hps_eth_mdc,
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inout [ 0:0] hps_eth_mdio,
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// hps-sdio
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output [ 0:0] hps_sdio_clk,
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inout [ 0:0] hps_sdio_cmd,
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inout [ 7:0] hps_sdio_d,
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// hps-usb
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input [ 0:0] hps_usb_clk,
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input [ 0:0] hps_usb_dir,
|
||||
input [ 0:0] hps_usb_nxt,
|
||||
output [ 0:0] hps_usb_stp,
|
||||
inout [ 7:0] hps_usb_d,
|
||||
|
||||
// hps-uart
|
||||
|
||||
input [ 0:0] hps_uart_rx,
|
||||
output [ 0:0] hps_uart_tx,
|
||||
|
||||
// hps-i2c (shared w fmc-a, fmc-b)
|
||||
|
||||
inout [ 0:0] hps_i2c_sda,
|
||||
inout [ 0:0] hps_i2c_scl,
|
||||
|
||||
// hps-gpio (max-v-u16)
|
||||
|
||||
inout [ 3:0] hps_gpio,
|
||||
|
||||
// gpio (max-v-u21)
|
||||
|
||||
input [ 7:0] gpio_bd_i,
|
||||
output [ 3:0] gpio_bd_o,
|
||||
|
||||
// adrv9009-interface
|
||||
|
||||
input ref_clk0,
|
||||
input ref_clk1,
|
||||
input [ 3:0] rx_serial_data,
|
||||
output [ 3:0] tx_serial_data,
|
||||
output rx_sync,
|
||||
output rx_os_sync,
|
||||
input tx_sync,
|
||||
input tx_sync_1,
|
||||
input sysref,
|
||||
|
||||
output ad9528_reset_b,
|
||||
output ad9528_sysref_req,
|
||||
output adrv9009_tx1_enable,
|
||||
output adrv9009_tx2_enable,
|
||||
output adrv9009_rx1_enable,
|
||||
output adrv9009_rx2_enable,
|
||||
output adrv9009_test,
|
||||
output adrv9009_reset_b,
|
||||
input adrv9009_gpint,
|
||||
|
||||
inout [ 18:0] adrv9009_gpio,
|
||||
|
||||
output spi_csn_ad9528,
|
||||
output spi_csn_adrv9009,
|
||||
output spi_clk,
|
||||
output spi_mosi,
|
||||
input spi_miso);
|
||||
|
||||
// internal signals
|
||||
|
||||
wire sys_ddr_cal_success;
|
||||
wire sys_ddr_cal_fail;
|
||||
wire sys_hps_resetn;
|
||||
wire sys_resetn_s;
|
||||
wire [ 63:0] gpio_i;
|
||||
wire [ 63:0] gpio_o;
|
||||
wire [ 7:0] spi_csn_s;
|
||||
wire dac_fifo_bypass;
|
||||
|
||||
// assignments
|
||||
|
||||
assign spi_csn_ad9528 = spi_csn_s[0];
|
||||
assign spi_csn_adrv9009 = spi_csn_s[1];
|
||||
|
||||
// gpio (adrv9009)
|
||||
|
||||
assign gpio_i[63:61] = gpio_o[63:61];
|
||||
|
||||
assign dac_fifo_bypass = gpio_o[60];
|
||||
assign gpio_i[60:60] = gpio_o[60];
|
||||
|
||||
assign ad9528_reset_b = gpio_o[59];
|
||||
assign ad9528_sysref_req = gpio_o[58];
|
||||
assign adrv9009_tx1_enable = gpio_o[57];
|
||||
assign adrv9009_tx2_enable = gpio_o[56];
|
||||
assign adrv9009_rx1_enable = gpio_o[55];
|
||||
assign adrv9009_rx2_enable = gpio_o[54];
|
||||
assign adrv9009_test = gpio_o[53];
|
||||
assign adrv9009_reset_b = gpio_o[52];
|
||||
assign gpio_i[59:52] = gpio_o[59:52];
|
||||
|
||||
assign gpio_i[51:51] = adrv9009_gpint;
|
||||
|
||||
assign gpio_i[50:32] = gpio_o[50:32];
|
||||
|
||||
// board stuff (max-v-u21)
|
||||
|
||||
assign gpio_i[31:14] = gpio_o[31:14];
|
||||
assign gpio_i[13:13] = sys_ddr_cal_success;
|
||||
assign gpio_i[12:12] = sys_ddr_cal_fail;
|
||||
assign gpio_i[11: 4] = gpio_bd_i;
|
||||
assign gpio_i[ 3: 0] = gpio_o[3:0];
|
||||
|
||||
assign gpio_bd_o = gpio_o[3:0];
|
||||
|
||||
// peripheral reset
|
||||
|
||||
assign sys_resetn_s = sys_resetn & sys_hps_resetn;
|
||||
|
||||
// instantiations
|
||||
|
||||
system_bd i_system_bd (
|
||||
.adrv9009_gpio_export (adrv9009_gpio),
|
||||
.sys_clk_clk (sys_clk),
|
||||
.sys_ddr_mem_mem_ck (sys_ddr_clk_p),
|
||||
.sys_ddr_mem_mem_ck_n (sys_ddr_clk_n),
|
||||
.sys_ddr_mem_mem_a (sys_ddr_a),
|
||||
.sys_ddr_mem_mem_act_n (sys_ddr_act_n),
|
||||
.sys_ddr_mem_mem_ba (sys_ddr_ba),
|
||||
.sys_ddr_mem_mem_bg (sys_ddr_bg),
|
||||
.sys_ddr_mem_mem_cke (sys_ddr_cke),
|
||||
.sys_ddr_mem_mem_cs_n (sys_ddr_cs_n),
|
||||
.sys_ddr_mem_mem_odt (sys_ddr_odt),
|
||||
.sys_ddr_mem_mem_reset_n (sys_ddr_reset_n),
|
||||
.sys_ddr_mem_mem_par (sys_ddr_par),
|
||||
.sys_ddr_mem_mem_alert_n (sys_ddr_alert_n),
|
||||
.sys_ddr_mem_mem_dqs (sys_ddr_dqs_p),
|
||||
.sys_ddr_mem_mem_dqs_n (sys_ddr_dqs_n),
|
||||
.sys_ddr_mem_mem_dq (sys_ddr_dq),
|
||||
.sys_ddr_mem_mem_dbi_n (sys_ddr_dbi_n),
|
||||
.sys_ddr_oct_oct_rzqin (sys_ddr_rzq),
|
||||
.sys_ddr_ref_clk_clk (sys_ddr_ref_clk),
|
||||
.sys_ddr_status_local_cal_success (sys_ddr_cal_success),
|
||||
.sys_ddr_status_local_cal_fail (sys_ddr_cal_fail),
|
||||
.sys_gpio_bd_in_port (gpio_i[31:0]),
|
||||
.sys_gpio_bd_out_port (gpio_o[31:0]),
|
||||
.sys_gpio_in_export (gpio_i[63:32]),
|
||||
.sys_gpio_out_export (gpio_o[63:32]),
|
||||
.sys_hps_ddr_mem_ck (hps_ddr_clk_p),
|
||||
.sys_hps_ddr_mem_ck_n (hps_ddr_clk_n),
|
||||
.sys_hps_ddr_mem_a (hps_ddr_a),
|
||||
.sys_hps_ddr_mem_act_n (hps_ddr_act_n),
|
||||
.sys_hps_ddr_mem_ba (hps_ddr_ba),
|
||||
.sys_hps_ddr_mem_bg (hps_ddr_bg),
|
||||
.sys_hps_ddr_mem_cke (hps_ddr_cke),
|
||||
.sys_hps_ddr_mem_cs_n (hps_ddr_cs_n),
|
||||
.sys_hps_ddr_mem_odt (hps_ddr_odt),
|
||||
.sys_hps_ddr_mem_reset_n (hps_ddr_reset_n),
|
||||
.sys_hps_ddr_mem_par (hps_ddr_par),
|
||||
.sys_hps_ddr_mem_alert_n (hps_ddr_alert_n),
|
||||
.sys_hps_ddr_mem_dqs (hps_ddr_dqs_p),
|
||||
.sys_hps_ddr_mem_dqs_n (hps_ddr_dqs_n),
|
||||
.sys_hps_ddr_mem_dq (hps_ddr_dq),
|
||||
.sys_hps_ddr_mem_dbi_n (hps_ddr_dbi_n),
|
||||
.sys_hps_ddr_oct_oct_rzqin (hps_ddr_rzq),
|
||||
.sys_hps_ddr_ref_clk_clk (hps_ddr_ref_clk),
|
||||
.sys_hps_ddr_rstn_reset_n (sys_resetn),
|
||||
.sys_hps_io_hps_io_phery_emac0_TX_CLK (hps_eth_txclk),
|
||||
.sys_hps_io_hps_io_phery_emac0_TXD0 (hps_eth_txd[0]),
|
||||
.sys_hps_io_hps_io_phery_emac0_TXD1 (hps_eth_txd[1]),
|
||||
.sys_hps_io_hps_io_phery_emac0_TXD2 (hps_eth_txd[2]),
|
||||
.sys_hps_io_hps_io_phery_emac0_TXD3 (hps_eth_txd[3]),
|
||||
.sys_hps_io_hps_io_phery_emac0_RX_CTL (hps_eth_rxctl),
|
||||
.sys_hps_io_hps_io_phery_emac0_TX_CTL (hps_eth_txctl),
|
||||
.sys_hps_io_hps_io_phery_emac0_RX_CLK (hps_eth_rxclk),
|
||||
.sys_hps_io_hps_io_phery_emac0_RXD0 (hps_eth_rxd[0]),
|
||||
.sys_hps_io_hps_io_phery_emac0_RXD1 (hps_eth_rxd[1]),
|
||||
.sys_hps_io_hps_io_phery_emac0_RXD2 (hps_eth_rxd[2]),
|
||||
.sys_hps_io_hps_io_phery_emac0_RXD3 (hps_eth_rxd[3]),
|
||||
.sys_hps_io_hps_io_phery_emac0_MDIO (hps_eth_mdio),
|
||||
.sys_hps_io_hps_io_phery_emac0_MDC (hps_eth_mdc),
|
||||
.sys_hps_io_hps_io_phery_sdmmc_CMD (hps_sdio_cmd),
|
||||
.sys_hps_io_hps_io_phery_sdmmc_D0 (hps_sdio_d[0]),
|
||||
.sys_hps_io_hps_io_phery_sdmmc_D1 (hps_sdio_d[1]),
|
||||
.sys_hps_io_hps_io_phery_sdmmc_D2 (hps_sdio_d[2]),
|
||||
.sys_hps_io_hps_io_phery_sdmmc_D3 (hps_sdio_d[3]),
|
||||
.sys_hps_io_hps_io_phery_sdmmc_D4 (hps_sdio_d[4]),
|
||||
.sys_hps_io_hps_io_phery_sdmmc_D5 (hps_sdio_d[5]),
|
||||
.sys_hps_io_hps_io_phery_sdmmc_D6 (hps_sdio_d[6]),
|
||||
.sys_hps_io_hps_io_phery_sdmmc_D7 (hps_sdio_d[7]),
|
||||
.sys_hps_io_hps_io_phery_sdmmc_CCLK (hps_sdio_clk),
|
||||
.sys_hps_io_hps_io_phery_usb0_DATA0 (hps_usb_d[0]),
|
||||
.sys_hps_io_hps_io_phery_usb0_DATA1 (hps_usb_d[1]),
|
||||
.sys_hps_io_hps_io_phery_usb0_DATA2 (hps_usb_d[2]),
|
||||
.sys_hps_io_hps_io_phery_usb0_DATA3 (hps_usb_d[3]),
|
||||
.sys_hps_io_hps_io_phery_usb0_DATA4 (hps_usb_d[4]),
|
||||
.sys_hps_io_hps_io_phery_usb0_DATA5 (hps_usb_d[5]),
|
||||
.sys_hps_io_hps_io_phery_usb0_DATA6 (hps_usb_d[6]),
|
||||
.sys_hps_io_hps_io_phery_usb0_DATA7 (hps_usb_d[7]),
|
||||
.sys_hps_io_hps_io_phery_usb0_CLK (hps_usb_clk),
|
||||
.sys_hps_io_hps_io_phery_usb0_STP (hps_usb_stp),
|
||||
.sys_hps_io_hps_io_phery_usb0_DIR (hps_usb_dir),
|
||||
.sys_hps_io_hps_io_phery_usb0_NXT (hps_usb_nxt),
|
||||
.sys_hps_io_hps_io_phery_uart1_RX (hps_uart_rx),
|
||||
.sys_hps_io_hps_io_phery_uart1_TX (hps_uart_tx),
|
||||
.sys_hps_io_hps_io_phery_i2c1_SDA (hps_i2c_sda),
|
||||
.sys_hps_io_hps_io_phery_i2c1_SCL (hps_i2c_scl),
|
||||
.sys_hps_io_hps_io_gpio_gpio1_io5 (hps_gpio[0]),
|
||||
.sys_hps_io_hps_io_gpio_gpio1_io14 (hps_gpio[1]),
|
||||
.sys_hps_io_hps_io_gpio_gpio1_io16 (hps_gpio[2]),
|
||||
.sys_hps_io_hps_io_gpio_gpio1_io17 (hps_gpio[3]),
|
||||
.sys_hps_out_rstn_reset_n (sys_hps_resetn),
|
||||
.sys_hps_rstn_reset_n (sys_resetn),
|
||||
.sys_rstn_reset_n (sys_resetn_s),
|
||||
.sys_spi_MISO (spi_miso),
|
||||
.sys_spi_MOSI (spi_mosi),
|
||||
.sys_spi_SCLK (spi_clk),
|
||||
.sys_spi_SS_n (spi_csn_s),
|
||||
.tx_serial_data_tx_serial_data (tx_serial_data),
|
||||
.tx_fifo_bypass_bypass (dac_fifo_bypass),
|
||||
.tx_ref_clk_clk (ref_clk1),
|
||||
.tx_sync_export (tx_sync),
|
||||
.tx_sysref_export (sysref),
|
||||
.rx_serial_data_rx_serial_data (rx_serial_data[1:0]),
|
||||
.rx_os_serial_data_rx_serial_data (rx_serial_data[3:2]),
|
||||
.rx_os_ref_clk_clk (ref_clk1),
|
||||
.rx_os_sync_export (rx_os_sync),
|
||||
.rx_os_sysref_export (sysref),
|
||||
.rx_ref_clk_clk (ref_clk1),
|
||||
.rx_sync_export (rx_sync),
|
||||
.rx_sysref_export (sysref));
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
|
@ -0,0 +1,262 @@
|
|||
|
||||
# adrv9009_tx JESD204
|
||||
|
||||
add_instance adrv9009_tx_jesd204 adi_jesd204
|
||||
set_instance_parameter_value adrv9009_tx_jesd204 {ID} {0}
|
||||
set_instance_parameter_value adrv9009_tx_jesd204 {TX_OR_RX_N} {1}
|
||||
set_instance_parameter_value adrv9009_tx_jesd204 {SOFT_PCS} {true}
|
||||
set_instance_parameter_value adrv9009_tx_jesd204 {LANE_RATE} {9830.4}
|
||||
set_instance_parameter_value adrv9009_tx_jesd204 {REFCLK_FREQUENCY} {245.76}
|
||||
set_instance_parameter_value adrv9009_tx_jesd204 {NUM_OF_LANES} {4}
|
||||
set_instance_parameter_value adrv9009_tx_jesd204 {LANE_MAP} {0 3 2 1}
|
||||
|
||||
add_connection sys_clk.clk adrv9009_tx_jesd204.sys_clk
|
||||
add_connection sys_clk.clk_reset adrv9009_tx_jesd204.sys_resetn
|
||||
add_interface tx_ref_clk clock sink
|
||||
set_interface_property tx_ref_clk EXPORT_OF adrv9009_tx_jesd204.ref_clk
|
||||
add_interface tx_serial_data conduit end
|
||||
set_interface_property tx_serial_data EXPORT_OF adrv9009_tx_jesd204.serial_data
|
||||
add_interface tx_sysref conduit end
|
||||
set_interface_property tx_sysref EXPORT_OF adrv9009_tx_jesd204.sysref
|
||||
add_interface tx_sync conduit end
|
||||
set_interface_property tx_sync EXPORT_OF adrv9009_tx_jesd204.sync
|
||||
|
||||
# adrv9009_rx JESD204
|
||||
|
||||
add_instance adrv9009_rx_jesd204 adi_jesd204
|
||||
set_instance_parameter_value adrv9009_rx_jesd204 {ID} {1}
|
||||
set_instance_parameter_value adrv9009_rx_jesd204 {TX_OR_RX_N} {0}
|
||||
set_instance_parameter_value adrv9009_rx_jesd204 {SOFT_PCS} {true}
|
||||
set_instance_parameter_value adrv9009_rx_jesd204 {LANE_RATE} {9830.4}
|
||||
set_instance_parameter_value adrv9009_rx_jesd204 {REFCLK_FREQUENCY} {245.76}
|
||||
set_instance_parameter_value adrv9009_rx_jesd204 {NUM_OF_LANES} {2}
|
||||
|
||||
add_connection sys_clk.clk adrv9009_rx_jesd204.sys_clk
|
||||
add_connection sys_clk.clk_reset adrv9009_rx_jesd204.sys_resetn
|
||||
add_interface rx_ref_clk clock sink
|
||||
set_interface_property rx_ref_clk EXPORT_OF adrv9009_rx_jesd204.ref_clk
|
||||
add_interface rx_serial_data conduit end
|
||||
set_interface_property rx_serial_data EXPORT_OF adrv9009_rx_jesd204.serial_data
|
||||
add_interface rx_sysref conduit end
|
||||
set_interface_property rx_sysref EXPORT_OF adrv9009_rx_jesd204.sysref
|
||||
add_interface rx_sync conduit end
|
||||
set_interface_property rx_sync EXPORT_OF adrv9009_rx_jesd204.sync
|
||||
|
||||
# adrv9009_rx_os JESD204
|
||||
|
||||
add_instance adrv9009_rx_os_jesd204 adi_jesd204
|
||||
set_instance_parameter_value adrv9009_rx_os_jesd204 {ID} {1}
|
||||
set_instance_parameter_value adrv9009_rx_os_jesd204 {TX_OR_RX_N} {0}
|
||||
set_instance_parameter_value adrv9009_rx_os_jesd204 {SOFT_PCS} {true}
|
||||
set_instance_parameter_value adrv9009_rx_os_jesd204 {LANE_RATE} {9830.4}
|
||||
set_instance_parameter_value adrv9009_rx_os_jesd204 {REFCLK_FREQUENCY} {245.76}
|
||||
set_instance_parameter_value adrv9009_rx_os_jesd204 {NUM_OF_LANES} {2}
|
||||
|
||||
add_connection sys_clk.clk adrv9009_rx_os_jesd204.sys_clk
|
||||
add_connection sys_clk.clk_reset adrv9009_rx_os_jesd204.sys_resetn
|
||||
add_interface rx_os_ref_clk clock sink
|
||||
set_interface_property rx_os_ref_clk EXPORT_OF adrv9009_rx_os_jesd204.ref_clk
|
||||
add_interface rx_os_serial_data conduit end
|
||||
set_interface_property rx_os_serial_data EXPORT_OF adrv9009_rx_os_jesd204.serial_data
|
||||
add_interface rx_os_sysref conduit end
|
||||
set_interface_property rx_os_sysref EXPORT_OF adrv9009_rx_os_jesd204.sysref
|
||||
add_interface rx_os_sync conduit end
|
||||
set_interface_property rx_os_sync EXPORT_OF adrv9009_rx_os_jesd204.sync
|
||||
|
||||
# adrv9009-core
|
||||
|
||||
add_instance axi_adrv9009 axi_adrv9009
|
||||
add_connection adrv9009_tx_jesd204.link_clk axi_adrv9009.if_dac_clk
|
||||
add_connection axi_adrv9009.if_dac_tx_data adrv9009_tx_jesd204.link_data
|
||||
add_connection adrv9009_rx_jesd204.link_clk axi_adrv9009.if_adc_clk
|
||||
add_connection adrv9009_rx_jesd204.link_sof axi_adrv9009.if_adc_rx_sof
|
||||
add_connection adrv9009_rx_jesd204.link_data axi_adrv9009.if_adc_rx_data
|
||||
add_connection adrv9009_rx_os_jesd204.link_clk axi_adrv9009.if_adc_os_clk
|
||||
add_connection adrv9009_rx_os_jesd204.link_sof axi_adrv9009.if_adc_rx_os_sof
|
||||
add_connection adrv9009_rx_os_jesd204.link_data axi_adrv9009.if_adc_rx_os_data
|
||||
add_connection sys_clk.clk axi_adrv9009.s_axi_clock
|
||||
add_connection sys_clk.clk_reset axi_adrv9009.s_axi_reset
|
||||
|
||||
# pack(s) & unpack(s)
|
||||
|
||||
add_instance axi_adrv9009_tx_upack util_upack
|
||||
set_instance_parameter_value axi_adrv9009_tx_upack {NUM_OF_CHANNELS} {4}
|
||||
set_instance_parameter_value axi_adrv9009_tx_upack {CHANNEL_DATA_WIDTH} {32}
|
||||
add_connection adrv9009_tx_jesd204.link_clk axi_adrv9009_tx_upack.if_dac_clk
|
||||
add_connection axi_adrv9009_tx_upack.dac_ch_0 axi_adrv9009.dac_ch_0
|
||||
add_connection axi_adrv9009_tx_upack.dac_ch_1 axi_adrv9009.dac_ch_1
|
||||
add_connection axi_adrv9009_tx_upack.dac_ch_2 axi_adrv9009.dac_ch_2
|
||||
add_connection axi_adrv9009_tx_upack.dac_ch_3 axi_adrv9009.dac_ch_3
|
||||
|
||||
add_instance axi_adrv9009_rx_cpack util_cpack
|
||||
set_instance_parameter_value axi_adrv9009_rx_cpack {NUM_OF_CHANNELS} {4}
|
||||
set_instance_parameter_value axi_adrv9009_rx_cpack {CHANNEL_DATA_WIDTH} {16}
|
||||
add_connection sys_clk.clk_reset axi_adrv9009_rx_cpack.if_adc_rst
|
||||
add_connection adrv9009_rx_jesd204.link_clk axi_adrv9009_rx_cpack.if_adc_clk
|
||||
add_connection axi_adrv9009.adc_ch_0 axi_adrv9009_rx_cpack.adc_ch_0
|
||||
add_connection axi_adrv9009.adc_ch_1 axi_adrv9009_rx_cpack.adc_ch_1
|
||||
add_connection axi_adrv9009.adc_ch_2 axi_adrv9009_rx_cpack.adc_ch_2
|
||||
add_connection axi_adrv9009.adc_ch_3 axi_adrv9009_rx_cpack.adc_ch_3
|
||||
|
||||
add_instance axi_adrv9009_rx_os_cpack util_cpack
|
||||
set_instance_parameter_value axi_adrv9009_rx_os_cpack {NUM_OF_CHANNELS} {2}
|
||||
set_instance_parameter_value axi_adrv9009_rx_os_cpack {CHANNEL_DATA_WIDTH} {32}
|
||||
add_connection sys_clk.clk_reset axi_adrv9009_rx_os_cpack.if_adc_rst
|
||||
add_connection adrv9009_rx_os_jesd204.link_clk axi_adrv9009_rx_os_cpack.if_adc_clk
|
||||
add_connection axi_adrv9009.adc_os_ch_0 axi_adrv9009_rx_os_cpack.adc_ch_0
|
||||
add_connection axi_adrv9009.adc_os_ch_1 axi_adrv9009_rx_os_cpack.adc_ch_1
|
||||
|
||||
# dac fifo
|
||||
|
||||
add_interface tx_fifo_bypass conduit end
|
||||
set_interface_property tx_fifo_bypass EXPORT_OF avl_adrv9009_tx_fifo.if_bypass
|
||||
|
||||
add_connection adrv9009_tx_jesd204.link_clk avl_adrv9009_tx_fifo.if_dac_clk
|
||||
add_connection adrv9009_tx_jesd204.link_reset avl_adrv9009_tx_fifo.if_dac_rst
|
||||
add_connection axi_adrv9009_tx_upack.if_dac_valid avl_adrv9009_tx_fifo.if_dac_valid
|
||||
add_connection avl_adrv9009_tx_fifo.if_dac_data axi_adrv9009_tx_upack.if_dac_data
|
||||
add_connection avl_adrv9009_tx_fifo.if_dac_dunf axi_adrv9009.if_dac_dunf
|
||||
|
||||
# dac & adc dma
|
||||
|
||||
add_instance axi_adrv9009_tx_dma axi_dmac
|
||||
set_instance_parameter_value axi_adrv9009_tx_dma {ID} {0}
|
||||
set_instance_parameter_value axi_adrv9009_tx_dma {DMA_DATA_WIDTH_SRC} {128}
|
||||
set_instance_parameter_value axi_adrv9009_tx_dma {DMA_DATA_WIDTH_DEST} {128}
|
||||
set_instance_parameter_value axi_adrv9009_tx_dma {DMA_LENGTH_WIDTH} {24}
|
||||
set_instance_parameter_value axi_adrv9009_tx_dma {DMA_2D_TRANSFER} {0}
|
||||
set_instance_parameter_value axi_adrv9009_tx_dma {AXI_SLICE_DEST} {0}
|
||||
set_instance_parameter_value axi_adrv9009_tx_dma {AXI_SLICE_SRC} {0}
|
||||
set_instance_parameter_value axi_adrv9009_tx_dma {SYNC_TRANSFER_START} {0}
|
||||
set_instance_parameter_value axi_adrv9009_tx_dma {CYCLIC} {1}
|
||||
set_instance_parameter_value axi_adrv9009_tx_dma {DMA_TYPE_DEST} {1}
|
||||
set_instance_parameter_value axi_adrv9009_tx_dma {DMA_TYPE_SRC} {0}
|
||||
set_instance_parameter_value axi_adrv9009_tx_dma {FIFO_SIZE} {16}
|
||||
add_connection sys_dma_clk.clk avl_adrv9009_tx_fifo.if_dma_clk
|
||||
add_connection sys_dma_clk.clk_reset avl_adrv9009_tx_fifo.if_dma_rst
|
||||
add_connection sys_dma_clk.clk axi_adrv9009_tx_dma.if_m_axis_aclk
|
||||
add_connection axi_adrv9009_tx_dma.if_m_axis_valid avl_adrv9009_tx_fifo.if_dma_valid
|
||||
add_connection axi_adrv9009_tx_dma.if_m_axis_data avl_adrv9009_tx_fifo.if_dma_data
|
||||
add_connection axi_adrv9009_tx_dma.if_m_axis_last avl_adrv9009_tx_fifo.if_dma_xfer_last
|
||||
add_connection axi_adrv9009_tx_dma.if_m_axis_xfer_req avl_adrv9009_tx_fifo.if_dma_xfer_req
|
||||
add_connection avl_adrv9009_tx_fifo.if_dma_ready axi_adrv9009_tx_dma.if_m_axis_ready
|
||||
add_connection sys_clk.clk axi_adrv9009_tx_dma.s_axi_clock
|
||||
add_connection sys_clk.clk_reset axi_adrv9009_tx_dma.s_axi_reset
|
||||
add_connection sys_dma_clk.clk axi_adrv9009_tx_dma.m_src_axi_clock
|
||||
add_connection sys_dma_clk.clk_reset axi_adrv9009_tx_dma.m_src_axi_reset
|
||||
|
||||
add_instance axi_adrv9009_rx_dma axi_dmac
|
||||
set_instance_parameter_value axi_adrv9009_rx_dma {ID} {0}
|
||||
set_instance_parameter_value axi_adrv9009_rx_dma {DMA_DATA_WIDTH_SRC} {64}
|
||||
set_instance_parameter_value axi_adrv9009_rx_dma {DMA_DATA_WIDTH_DEST} {128}
|
||||
set_instance_parameter_value axi_adrv9009_rx_dma {DMA_LENGTH_WIDTH} {24}
|
||||
set_instance_parameter_value axi_adrv9009_rx_dma {DMA_2D_TRANSFER} {0}
|
||||
set_instance_parameter_value axi_adrv9009_rx_dma {AXI_SLICE_DEST} {0}
|
||||
set_instance_parameter_value axi_adrv9009_rx_dma {AXI_SLICE_SRC} {0}
|
||||
set_instance_parameter_value axi_adrv9009_rx_dma {SYNC_TRANSFER_START} {1}
|
||||
set_instance_parameter_value axi_adrv9009_rx_dma {CYCLIC} {0}
|
||||
set_instance_parameter_value axi_adrv9009_rx_dma {DMA_TYPE_DEST} {0}
|
||||
set_instance_parameter_value axi_adrv9009_rx_dma {DMA_TYPE_SRC} {2}
|
||||
set_instance_parameter_value axi_adrv9009_rx_dma {FIFO_SIZE} {16}
|
||||
add_connection adrv9009_rx_jesd204.link_clk axi_adrv9009_rx_dma.if_fifo_wr_clk
|
||||
add_connection axi_adrv9009_rx_cpack.if_adc_valid axi_adrv9009_rx_dma.if_fifo_wr_en
|
||||
add_connection axi_adrv9009_rx_cpack.if_adc_sync axi_adrv9009_rx_dma.if_fifo_wr_sync
|
||||
add_connection axi_adrv9009_rx_cpack.if_adc_data axi_adrv9009_rx_dma.if_fifo_wr_din
|
||||
add_connection axi_adrv9009_rx_dma.if_fifo_wr_overflow axi_adrv9009.if_adc_dovf
|
||||
add_connection sys_clk.clk axi_adrv9009_rx_dma.s_axi_clock
|
||||
add_connection sys_clk.clk_reset axi_adrv9009_rx_dma.s_axi_reset
|
||||
add_connection sys_dma_clk.clk axi_adrv9009_rx_dma.m_dest_axi_clock
|
||||
add_connection sys_dma_clk.clk_reset axi_adrv9009_rx_dma.m_dest_axi_reset
|
||||
|
||||
add_instance axi_adrv9009_rx_os_dma axi_dmac
|
||||
set_instance_parameter_value axi_adrv9009_rx_os_dma {ID} {0}
|
||||
set_instance_parameter_value axi_adrv9009_rx_os_dma {DMA_DATA_WIDTH_SRC} {64}
|
||||
set_instance_parameter_value axi_adrv9009_rx_os_dma {DMA_DATA_WIDTH_DEST} {128}
|
||||
set_instance_parameter_value axi_adrv9009_rx_os_dma {DMA_LENGTH_WIDTH} {24}
|
||||
set_instance_parameter_value axi_adrv9009_rx_os_dma {DMA_2D_TRANSFER} {0}
|
||||
set_instance_parameter_value axi_adrv9009_rx_os_dma {AXI_SLICE_DEST} {0}
|
||||
set_instance_parameter_value axi_adrv9009_rx_os_dma {AXI_SLICE_SRC} {0}
|
||||
set_instance_parameter_value axi_adrv9009_rx_os_dma {SYNC_TRANSFER_START} {1}
|
||||
set_instance_parameter_value axi_adrv9009_rx_os_dma {CYCLIC} {0}
|
||||
set_instance_parameter_value axi_adrv9009_rx_os_dma {DMA_TYPE_DEST} {0}
|
||||
set_instance_parameter_value axi_adrv9009_rx_os_dma {DMA_TYPE_SRC} {2}
|
||||
set_instance_parameter_value axi_adrv9009_rx_os_dma {FIFO_SIZE} {16}
|
||||
add_connection adrv9009_rx_os_jesd204.link_clk axi_adrv9009_rx_os_dma.if_fifo_wr_clk
|
||||
add_connection axi_adrv9009_rx_os_cpack.if_adc_valid axi_adrv9009_rx_os_dma.if_fifo_wr_en
|
||||
add_connection axi_adrv9009_rx_os_cpack.if_adc_sync axi_adrv9009_rx_os_dma.if_fifo_wr_sync
|
||||
add_connection axi_adrv9009_rx_os_cpack.if_adc_data axi_adrv9009_rx_os_dma.if_fifo_wr_din
|
||||
add_connection axi_adrv9009_rx_os_dma.if_fifo_wr_overflow axi_adrv9009.if_adc_os_dovf
|
||||
add_connection sys_clk.clk axi_adrv9009_rx_os_dma.s_axi_clock
|
||||
add_connection sys_clk.clk_reset axi_adrv9009_rx_os_dma.s_axi_reset
|
||||
add_connection sys_dma_clk.clk axi_adrv9009_rx_os_dma.m_dest_axi_clock
|
||||
add_connection sys_dma_clk.clk_reset axi_adrv9009_rx_os_dma.m_dest_axi_reset
|
||||
|
||||
# adrv9009 gpio
|
||||
|
||||
add_instance avl_adrv9009_gpio altera_avalon_pio
|
||||
set_instance_parameter_value avl_adrv9009_gpio {direction} {Bidir}
|
||||
set_instance_parameter_value avl_adrv9009_gpio {generateIRQ} {1}
|
||||
set_instance_parameter_value avl_adrv9009_gpio {width} {19}
|
||||
add_connection sys_clk.clk avl_adrv9009_gpio.clk
|
||||
add_connection sys_clk.clk_reset avl_adrv9009_gpio.reset
|
||||
add_interface adrv9009_gpio conduit end
|
||||
set_interface_property adrv9009_gpio EXPORT_OF avl_adrv9009_gpio.external_connection
|
||||
|
||||
# reconfig sharing
|
||||
|
||||
for {set i 0} {$i < 4} {incr i} {
|
||||
add_instance avl_adxcfg_${i} avl_adxcfg
|
||||
add_connection sys_clk.clk avl_adxcfg_${i}.rcfg_clk
|
||||
add_connection sys_clk.clk_reset avl_adxcfg_${i}.rcfg_reset_n
|
||||
add_connection avl_adxcfg_${i}.rcfg_m0 adrv9009_tx_jesd204.phy_reconfig_${i}
|
||||
|
||||
if {$i < 2} {
|
||||
add_connection avl_adxcfg_${i}.rcfg_m1 adrv9009_rx_jesd204.phy_reconfig_${i}
|
||||
} else {
|
||||
set j [expr $i - 2]
|
||||
add_connection avl_adxcfg_${i}.rcfg_m1 adrv9009_rx_os_jesd204.phy_reconfig_${j}
|
||||
}
|
||||
}
|
||||
|
||||
# addresses
|
||||
|
||||
ad_cpu_interconnect 0x00020000 adrv9009_tx_jesd204.link_reconfig
|
||||
ad_cpu_interconnect 0x00024000 adrv9009_tx_jesd204.link_management
|
||||
ad_cpu_interconnect 0x00025000 adrv9009_tx_jesd204.link_pll_reconfig
|
||||
ad_cpu_interconnect 0x00026000 adrv9009_tx_jesd204.lane_pll_reconfig
|
||||
ad_cpu_interconnect 0x00028000 avl_adxcfg_0.rcfg_s0
|
||||
ad_cpu_interconnect 0x00029000 avl_adxcfg_1.rcfg_s0
|
||||
ad_cpu_interconnect 0x0002a000 avl_adxcfg_2.rcfg_s0
|
||||
ad_cpu_interconnect 0x0002b000 avl_adxcfg_3.rcfg_s0
|
||||
ad_cpu_interconnect 0x0002c000 axi_adrv9009_tx_dma.s_axi
|
||||
|
||||
ad_cpu_interconnect 0x00030000 adrv9009_rx_jesd204.link_reconfig
|
||||
ad_cpu_interconnect 0x00034000 adrv9009_rx_jesd204.link_management
|
||||
ad_cpu_interconnect 0x00035000 adrv9009_rx_jesd204.link_pll_reconfig
|
||||
ad_cpu_interconnect 0x00038000 avl_adxcfg_0.rcfg_s1
|
||||
ad_cpu_interconnect 0x00039000 avl_adxcfg_1.rcfg_s1
|
||||
ad_cpu_interconnect 0x0003c000 axi_adrv9009_rx_dma.s_axi
|
||||
|
||||
ad_cpu_interconnect 0x00040000 adrv9009_rx_os_jesd204.link_reconfig
|
||||
ad_cpu_interconnect 0x00044000 adrv9009_rx_os_jesd204.link_management
|
||||
ad_cpu_interconnect 0x00045000 adrv9009_rx_os_jesd204.link_pll_reconfig
|
||||
ad_cpu_interconnect 0x00048000 avl_adxcfg_2.rcfg_s1
|
||||
ad_cpu_interconnect 0x00049000 avl_adxcfg_3.rcfg_s1
|
||||
ad_cpu_interconnect 0x0004c000 axi_adrv9009_rx_os_dma.s_axi
|
||||
|
||||
ad_cpu_interconnect 0x00050000 axi_adrv9009.s_axi
|
||||
ad_cpu_interconnect 0x00060000 avl_adrv9009_gpio.s1
|
||||
|
||||
# dma interconnects
|
||||
|
||||
ad_dma_interconnect axi_adrv9009_tx_dma.m_src_axi
|
||||
ad_dma_interconnect axi_adrv9009_rx_dma.m_dest_axi
|
||||
ad_dma_interconnect axi_adrv9009_rx_os_dma.m_dest_axi
|
||||
|
||||
# interrupts
|
||||
|
||||
ad_cpu_interrupt 11 axi_adrv9009_tx_dma.interrupt_sender
|
||||
ad_cpu_interrupt 12 axi_adrv9009_rx_dma.interrupt_sender
|
||||
ad_cpu_interrupt 13 axi_adrv9009_rx_os_dma.interrupt_sender
|
||||
ad_cpu_interrupt 14 avl_adrv9009_gpio.irq
|
||||
|
||||
Loading…
Reference in New Issue