From f03675cdab21285d2451f5ce62d0c7c1774789db Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Thu, 24 Nov 2016 13:20:45 +0200 Subject: [PATCH] axi_dmac: ID_WIDTH must be clog2(FIFO_SIZE*2) --- library/axi_dmac/axi_dmac.v | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/library/axi_dmac/axi_dmac.v b/library/axi_dmac/axi_dmac.v index 7d3753302..3c1d34498 100644 --- a/library/axi_dmac/axi_dmac.v +++ b/library/axi_dmac/axi_dmac.v @@ -225,14 +225,13 @@ localparam BYTES_PER_BEAT_WIDTH_SRC = DMA_DATA_WIDTH_SRC > 1024 ? 8 : DMA_DATA_WIDTH_SRC > 32 ? 3 : DMA_DATA_WIDTH_SRC > 16 ? 2 : DMA_DATA_WIDTH_SRC > 8 ? 1 : 0; -localparam ID_WIDTH = (FIFO_SIZE*2) > 1024 ? 8 : - (FIFO_SIZE*2) > 512 ? 7 : - (FIFO_SIZE*2) > 256 ? 6 : - (FIFO_SIZE*2) > 128 ? 5 : - (FIFO_SIZE*2) > 64 ? 4 : - (FIFO_SIZE*2) > 32 ? 3 : - (FIFO_SIZE*2) > 16 ? 2 : - (FIFO_SIZE*2) > 8 ? 1 : 0; +localparam ID_WIDTH = (FIFO_SIZE) > 64 ? 8 : + (FIFO_SIZE) > 32 ? 7 : + (FIFO_SIZE) > 16 ? 6 : + (FIFO_SIZE) > 8 ? 5 : + (FIFO_SIZE) > 4 ? 4 : + (FIFO_SIZE) > 2 ? 3 : + (FIFO_SIZE) > 1 ? 2 : 1; // Register interface signals reg [31:0] up_rdata = 'd0;