From ef960a29c76d7ec1ff30f96913ed5089040c0796 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Fri, 21 Mar 2014 15:13:50 -0400 Subject: [PATCH] altera files --- library/axi_dmac/axi_dmac_alt.v | 453 +++++++++++++++++++++++++++++++ library/axi_dmac/axi_dmac_hw.tcl | 355 ++++++++++++++++++++++++ 2 files changed, 808 insertions(+) create mode 100755 library/axi_dmac/axi_dmac_alt.v create mode 100755 library/axi_dmac/axi_dmac_hw.tcl diff --git a/library/axi_dmac/axi_dmac_alt.v b/library/axi_dmac/axi_dmac_alt.v new file mode 100755 index 000000000..ff9a274b1 --- /dev/null +++ b/library/axi_dmac/axi_dmac_alt.v @@ -0,0 +1,453 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_dmac_alt ( + + // axi interface + + s_axi_aclk, + s_axi_aresetn, + s_axi_awvalid, + s_axi_awaddr, + s_axi_awid, + s_axi_awlen, + s_axi_awsize, + s_axi_awburst, + s_axi_awlock, + s_axi_awcache, + s_axi_awprot, + s_axi_awready, + s_axi_wvalid, + s_axi_wdata, + s_axi_wstrb, + s_axi_wlast, + s_axi_wready, + s_axi_bvalid, + s_axi_bresp, + s_axi_bid, + s_axi_bready, + s_axi_arvalid, + s_axi_araddr, + s_axi_arid, + s_axi_arlen, + s_axi_arsize, + s_axi_arburst, + s_axi_arlock, + s_axi_arcache, + s_axi_arprot, + s_axi_arready, + s_axi_rvalid, + s_axi_rresp, + s_axi_rdata, + s_axi_rid, + s_axi_rlast, + s_axi_rready, + + // axi master interface (destination) + + m_dest_axi_aclk, + m_dest_axi_aresetn, + m_dest_axi_awvalid, + m_dest_axi_awaddr, + m_dest_axi_awid, + m_dest_axi_awlen, + m_dest_axi_awsize, + m_dest_axi_awburst, + m_dest_axi_awlock, + m_dest_axi_awcache, + m_dest_axi_awprot, + m_dest_axi_awready, + m_dest_axi_wvalid, + m_dest_axi_wdata, + m_dest_axi_wstrb, + m_dest_axi_wlast, + m_dest_axi_wready, + m_dest_axi_bvalid, + m_dest_axi_bresp, + m_dest_axi_bid, + m_dest_axi_bready, + m_dest_axi_arvalid, + m_dest_axi_araddr, + m_dest_axi_arid, + m_dest_axi_arlen, + m_dest_axi_arsize, + m_dest_axi_arburst, + m_dest_axi_arlock, + m_dest_axi_arcache, + m_dest_axi_arprot, + m_dest_axi_arready, + m_dest_axi_rvalid, + m_dest_axi_rresp, + m_dest_axi_rdata, + m_dest_axi_rid, + m_dest_axi_rlast, + m_dest_axi_rready, + + // axi master interface (source) + + m_src_axi_aclk, + m_src_axi_aresetn, + m_src_axi_awvalid, + m_src_axi_awaddr, + m_src_axi_awid, + m_src_axi_awlen, + m_src_axi_awsize, + m_src_axi_awburst, + m_src_axi_awlock, + m_src_axi_awcache, + m_src_axi_awprot, + m_src_axi_awready, + m_src_axi_wvalid, + m_src_axi_wdata, + m_src_axi_wstrb, + m_src_axi_wlast, + m_src_axi_wready, + m_src_axi_bvalid, + m_src_axi_bresp, + m_src_axi_bid, + m_src_axi_bready, + m_src_axi_arvalid, + m_src_axi_araddr, + m_src_axi_arid, + m_src_axi_arlen, + m_src_axi_arsize, + m_src_axi_arburst, + m_src_axi_arlock, + m_src_axi_arcache, + m_src_axi_arprot, + m_src_axi_arready, + m_src_axi_rvalid, + m_src_axi_rresp, + m_src_axi_rdata, + m_src_axi_rid, + m_src_axi_rlast, + m_src_axi_rready, + + // axis + + s_axis_aclk, + s_axis_ready, + s_axis_valid, + s_axis_data, + s_axis_user, + m_axis_aclk, + m_axis_ready, + m_axis_valid, + m_axis_data, + + // fifo + + fifo_wr_clk, + fifo_wr_en, + fifo_wr_din, + fifo_wr_overflow, + fifo_wr_sync, + fifo_rd_clk, + fifo_rd_en, + fifo_rd_valid, + fifo_rd_dout, + fifo_rd_underflow); + + parameter PCORE_ID = 0; + parameter C_DMA_DATA_WIDTH_SRC = 64; + parameter C_DMA_DATA_WIDTH_DEST = 64; + parameter C_ADDR_ALIGN_BITS = 3; + parameter C_DMA_LENGTH_WIDTH = 14; + parameter C_2D_TRANSFER = 1; + parameter C_CLKS_ASYNC_REQ_SRC = 1; + parameter C_CLKS_ASYNC_SRC_DEST = 1; + parameter C_CLKS_ASYNC_DEST_REQ = 1; + parameter C_AXI_SLICE_DEST = 0; + parameter C_AXI_SLICE_SRC = 0; + parameter C_SYNC_TRANSFER_START = 0; + parameter C_CYCLIC = 1; + parameter C_DMA_TYPE_DEST = 0; + parameter C_DMA_TYPE_SRC = 2; + + // axi slave interface + + input s_axi_aclk; + input s_axi_aresetn; + input s_axi_awvalid; + input [31:0] s_axi_awaddr; + input [ 0:0] s_axi_awid; + input [ 7:0] s_axi_awlen; + input [ 2:0] s_axi_awsize; + input [ 1:0] s_axi_awburst; + input [ 0:0] s_axi_awlock; + input [ 3:0] s_axi_awcache; + input [ 2:0] s_axi_awprot; + output s_axi_awready; + input s_axi_wvalid; + input [31:0] s_axi_wdata; + input [ 3:0] s_axi_wstrb; + input s_axi_wlast; + output s_axi_wready; + output s_axi_bvalid; + output [ 1:0] s_axi_bresp; + output [ 0:0] s_axi_bid; + input s_axi_bready; + input s_axi_arvalid; + input [31:0] s_axi_araddr; + input [ 0:0] s_axi_arid; + input [ 7:0] s_axi_arlen; + input [ 2:0] s_axi_arsize; + input [ 1:0] s_axi_arburst; + input [ 0:0] s_axi_arlock; + input [ 3:0] s_axi_arcache; + input [ 2:0] s_axi_arprot; + output s_axi_arready; + output s_axi_rvalid; + output [ 1:0] s_axi_rresp; + output [31:0] s_axi_rdata; + output [ 0:0] s_axi_rid; + output s_axi_rlast; + input s_axi_rready; + + // axi master interface (destination) + + input m_dest_axi_aclk; + input m_dest_axi_aresetn; + output m_dest_axi_awvalid; + output [31:0] m_dest_axi_awaddr; + output [ 0:0] m_dest_axi_awid; + output [ 7:0] m_dest_axi_awlen; + output [ 2:0] m_dest_axi_awsize; + output [ 1:0] m_dest_axi_awburst; + output [ 0:0] m_dest_axi_awlock; + output [ 3:0] m_dest_axi_awcache; + output [ 2:0] m_dest_axi_awprot; + input m_dest_axi_awready; + output m_dest_axi_wvalid; + output [C_DMA_DATA_WIDTH_DEST-1:0] m_dest_axi_wdata; + output [(C_DMA_DATA_WIDTH_DEST/8)-1:0] m_dest_axi_wstrb; + output m_dest_axi_wlast; + input m_dest_axi_wready; + input m_dest_axi_bvalid; + input [ 1:0] m_dest_axi_bresp; + input [ 0:0] m_dest_axi_bid; + output m_dest_axi_bready; + output m_dest_axi_arvalid; + output [31:0] m_dest_axi_araddr; + output [ 0:0] m_dest_axi_arid; + output [ 7:0] m_dest_axi_arlen; + output [ 2:0] m_dest_axi_arsize; + output [ 1:0] m_dest_axi_arburst; + output [ 0:0] m_dest_axi_arlock; + output [ 3:0] m_dest_axi_arcache; + output [ 2:0] m_dest_axi_arprot; + input m_dest_axi_arready; + input m_dest_axi_rvalid; + input [ 1:0] m_dest_axi_rresp; + input [C_DMA_DATA_WIDTH_DEST-1:0] m_dest_axi_rdata; + input [ 0:0] m_dest_axi_rid; + input m_dest_axi_rlast; + output m_dest_axi_rready; + + // axi master interface (source) + + input m_src_axi_aclk; + input m_src_axi_aresetn; + output m_src_axi_awvalid; + output [31:0] m_src_axi_awaddr; + output [ 0:0] m_src_axi_awid; + output [ 7:0] m_src_axi_awlen; + output [ 2:0] m_src_axi_awsize; + output [ 1:0] m_src_axi_awburst; + output [ 0:0] m_src_axi_awlock; + output [ 3:0] m_src_axi_awcache; + output [ 2:0] m_src_axi_awprot; + input m_src_axi_awready; + output m_src_axi_wvalid; + output [C_DMA_DATA_WIDTH_SRC-1:0] m_src_axi_wdata; + output [(C_DMA_DATA_WIDTH_SRC/8)-1:0] m_src_axi_wstrb; + output m_src_axi_wlast; + input m_src_axi_wready; + input m_src_axi_bvalid; + input [ 1:0] m_src_axi_bresp; + input [ 0:0] m_src_axi_bid; + output m_src_axi_bready; + output m_src_axi_arvalid; + output [31:0] m_src_axi_araddr; + output [ 0:0] m_src_axi_arid; + output [ 7:0] m_src_axi_arlen; + output [ 2:0] m_src_axi_arsize; + output [ 1:0] m_src_axi_arburst; + output [ 0:0] m_src_axi_arlock; + output [ 3:0] m_src_axi_arcache; + output [ 2:0] m_src_axi_arprot; + input m_src_axi_arready; + input m_src_axi_rvalid; + input [ 1:0] m_src_axi_rresp; + input [C_DMA_DATA_WIDTH_SRC-1:0] m_src_axi_rdata; + input [ 0:0] m_src_axi_rid; + input m_src_axi_rlast; + output m_src_axi_rready; + + // axis + + input s_axis_aclk; + output s_axis_ready; + input s_axis_valid; + input [C_DMA_DATA_WIDTH_SRC-1:0] s_axis_data; + input [ 0:0] s_axis_user; + input m_axis_aclk; + input m_axis_ready; + output m_axis_valid; + output [C_DMA_DATA_WIDTH_DEST-1:0] m_axis_data; + + // fifo + + input fifo_wr_clk; + input fifo_wr_en; + input [C_DMA_DATA_WIDTH_SRC-1:0] fifo_wr_din; + output fifo_wr_overflow; + input fifo_wr_sync; + input fifo_rd_clk; + input fifo_rd_en; + output fifo_rd_valid; + output [C_DMA_DATA_WIDTH_DEST-1:0] fifo_rd_dout; + output fifo_rd_underflow; + + // defaults + + assign s_axi_bid = 1'd0; + assign s_axi_rid = 1'd0; + assign s_axi_rlast = 1'd0; + + // instantiation + + axi_dmac #( + .PCORE_ID (PCORE_ID), + .C_BASEADDR (32'h00000000), + .C_HIGHADDR (32'hffffffff), + .C_DMA_DATA_WIDTH_SRC (C_DMA_DATA_WIDTH_SRC), + .C_DMA_DATA_WIDTH_DEST (C_DMA_DATA_WIDTH_DEST), + .C_ADDR_ALIGN_BITS (C_ADDR_ALIGN_BITS), + .C_DMA_LENGTH_WIDTH (C_DMA_LENGTH_WIDTH), + .C_2D_TRANSFER (C_2D_TRANSFER), + .C_CLKS_ASYNC_REQ_SRC (C_CLKS_ASYNC_REQ_SRC), + .C_CLKS_ASYNC_SRC_DEST (C_CLKS_ASYNC_SRC_DEST), + .C_CLKS_ASYNC_DEST_REQ (C_CLKS_ASYNC_DEST_REQ), + .C_AXI_SLICE_DEST (C_AXI_SLICE_DEST), + .C_AXI_SLICE_SRC (C_AXI_SLICE_SRC), + .C_SYNC_TRANSFER_START (C_SYNC_TRANSFER_START), + .C_CYCLIC (C_CYCLIC), + .C_DMA_TYPE_DEST (C_DMA_TYPE_DEST), + .C_DMA_TYPE_SRC (C_DMA_TYPE_SRC)) + i_axi_dmac ( + .s_axi_aclk (s_axi_aclk), + .s_axi_aresetn (s_axi_aresetn), + .s_axi_awvalid (s_axi_awvalid), + .s_axi_awaddr (s_axi_awaddr), + .s_axi_awready (s_axi_awready), + .s_axi_wvalid (s_axi_wvalid), + .s_axi_wdata (s_axi_wdata), + .s_axi_wstrb (s_axi_wstrb), + .s_axi_wready (s_axi_wready), + .s_axi_bvalid (s_axi_bvalid), + .s_axi_bresp (s_axi_bresp), + .s_axi_bready (s_axi_bready), + .s_axi_arvalid (s_axi_arvalid), + .s_axi_araddr (s_axi_araddr), + .s_axi_arready (s_axi_arready), + .s_axi_rvalid (s_axi_rvalid), + .s_axi_rready (s_axi_rready), + .s_axi_rresp (s_axi_rresp), + .s_axi_rdata (s_axi_rdata), + .irq (irq), + .m_dest_axi_aclk (m_dest_axi_aclk), + .m_dest_axi_aresetn (m_dest_axi_aresetn), + .m_src_axi_aclk (m_src_axi_aclk), + .m_src_axi_aresetn (m_src_axi_aresetn), + .m_dest_axi_awaddr (m_dest_axi_awaddr), + .m_dest_axi_awlen (m_dest_axi_awlen), + .m_dest_axi_awsize (m_dest_axi_awsize), + .m_dest_axi_awburst (m_dest_axi_awburst), + .m_dest_axi_awprot (m_dest_axi_awprot), + .m_dest_axi_awcache (m_dest_axi_awcache), + .m_dest_axi_awvalid (m_dest_axi_awvalid), + .m_dest_axi_awready (m_dest_axi_awready), + .m_dest_axi_wdata (m_dest_axi_wdata), + .m_dest_axi_wstrb (m_dest_axi_wstrb), + .m_dest_axi_wready (m_dest_axi_wready), + .m_dest_axi_wvalid (m_dest_axi_wvalid), + .m_dest_axi_wlast (m_dest_axi_wlast), + .m_dest_axi_bvalid (m_dest_axi_bvalid), + .m_dest_axi_bresp (m_dest_axi_bresp), + .m_dest_axi_bready (m_dest_axi_bready), + .m_src_axi_arready (m_src_axi_arready), + .m_src_axi_arvalid (m_src_axi_arvalid), + .m_src_axi_araddr (m_src_axi_araddr), + .m_src_axi_arlen (m_src_axi_arlen), + .m_src_axi_arsize (m_src_axi_arsize), + .m_src_axi_arburst (m_src_axi_arburst), + .m_src_axi_arprot (m_src_axi_arprot), + .m_src_axi_arcache (m_src_axi_arcache), + .m_src_axi_rdata (m_src_axi_rdata), + .m_src_axi_rready (m_src_axi_rready), + .m_src_axi_rvalid (m_src_axi_rvalid), + .m_src_axi_rresp (m_src_axi_rresp), + .s_axis_aclk (s_axis_aclk), + .s_axis_ready (s_axis_ready), + .s_axis_valid (s_axis_valid), + .s_axis_data (s_axis_data), + .s_axis_user (s_axis_user), + .m_axis_aclk (m_axis_aclk), + .m_axis_ready (m_axis_ready), + .m_axis_valid (m_axis_valid), + .m_axis_data (m_axis_data), + .fifo_wr_clk (fifo_wr_clk), + .fifo_wr_en (fifo_wr_en), + .fifo_wr_din (fifo_wr_din), + .fifo_wr_overflow (fifo_wr_overflow), + .fifo_wr_sync (fifo_wr_sync), + .fifo_rd_clk (fifo_rd_clk), + .fifo_rd_en (fifo_rd_en), + .fifo_rd_valid (fifo_rd_valid), + .fifo_rd_dout (fifo_rd_dout), + .fifo_rd_underflow (fifo_rd_underflow)); + +endmodule + +// *************************************************************************** +// *************************************************************************** + diff --git a/library/axi_dmac/axi_dmac_hw.tcl b/library/axi_dmac/axi_dmac_hw.tcl new file mode 100755 index 000000000..66215dc83 --- /dev/null +++ b/library/axi_dmac/axi_dmac_hw.tcl @@ -0,0 +1,355 @@ + + +package require -exact qsys 13.0 +source ../scripts/adi_env.tcl + +set_module_property NAME axi_dmac +set_module_property DESCRIPTION "AXI DMA Controller" +set_module_property VERSION 1.0 +set_module_property DISPLAY_NAME axi_dmac +set_module_property ELABORATION_CALLBACK axi_dmac_elaborate + +# files + +add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis" +set_fileset_property quartus_synth TOP_LEVEL axi_dmac_alt +add_fileset_file sync_bits.v VERILOG PATH $ad_hdl_dir/library/common/sync_bits.v +add_fileset_file sync_gray.v VERILOG PATH $ad_hdl_dir/library/common/sync_gray.v +add_fileset_file up_axi.v VERILOG PATH $ad_hdl_dir/library/common/up_axi.v +add_fileset_file axi_fifo.v VERILOG PATH $ad_hdl_dir/library/axi_fifo/axi_fifo.v +add_fileset_file address_gray.v VERILOG PATH $ad_hdl_dir/library/axi_fifo/address_gray.v +add_fileset_file address_gray_pipelined.v VERILOG PATH $ad_hdl_dir/library/axi_fifo/address_gray_pipelined.v +add_fileset_file address_generator.v VERILOG PATH address_generator.v +add_fileset_file data_mover.v VERILOG PATH data_mover.v +add_fileset_file request_arb.v VERILOG PATH request_arb.v +add_fileset_file request_generator.v VERILOG PATH request_generator.v +add_fileset_file response_handler.v VERILOG PATH response_handler.v +add_fileset_file axi_register_slice.v VERILOG PATH axi_register_slice.v +add_fileset_file 2d_transfer.v VERILOG PATH 2d_transfer.v +add_fileset_file dest_axi_mm.v VERILOG PATH dest_axi_mm.v +add_fileset_file dest_axi_stream.v VERILOG PATH dest_axi_stream.v +add_fileset_file dest_fifo_inf.v VERILOG PATH dest_fifo_inf.v +add_fileset_file src_axi_mm.v VERILOG PATH src_axi_mm.v +add_fileset_file src_axi_stream.v VERILOG PATH src_axi_stream.v +add_fileset_file src_fifo_inf.v VERILOG PATH src_fifo_inf.v +add_fileset_file splitter.v VERILOG PATH splitter.v +add_fileset_file response_generator.v VERILOG PATH response_generator.v +add_fileset_file axi_dmac.v VERILOG PATH axi_dmac.v +add_fileset_file axi_repack.v VERILOG PATH axi_repack.v + +# parameters + +add_parameter PCORE_ID INTEGER 0 +set_parameter_property PCORE_ID DEFAULT_VALUE 0 +set_parameter_property PCORE_ID DISPLAY_NAME PCORE_ID +set_parameter_property PCORE_ID TYPE INTEGER +set_parameter_property PCORE_ID UNITS None +set_parameter_property PCORE_ID HDL_PARAMETER true + +add_parameter C_DMA_DATA_WIDTH_SRC INTEGER 0 +set_parameter_property C_DMA_DATA_WIDTH_SRC DEFAULT_VALUE 64 +set_parameter_property C_DMA_DATA_WIDTH_SRC DISPLAY_NAME C_DMA_DATA_WIDTH_SRC +set_parameter_property C_DMA_DATA_WIDTH_SRC TYPE INTEGER +set_parameter_property C_DMA_DATA_WIDTH_SRC UNITS None +set_parameter_property C_DMA_DATA_WIDTH_SRC HDL_PARAMETER true + +add_parameter C_DMA_DATA_WIDTH_DEST INTEGER 0 +set_parameter_property C_DMA_DATA_WIDTH_DEST DEFAULT_VALUE 64 +set_parameter_property C_DMA_DATA_WIDTH_DEST DISPLAY_NAME C_DMA_DATA_WIDTH_DEST +set_parameter_property C_DMA_DATA_WIDTH_DEST TYPE INTEGER +set_parameter_property C_DMA_DATA_WIDTH_DEST UNITS None +set_parameter_property C_DMA_DATA_WIDTH_DEST HDL_PARAMETER true + +add_parameter C_ADDR_ALIGN_BITS INTEGER 0 +set_parameter_property C_ADDR_ALIGN_BITS DEFAULT_VALUE 3 +set_parameter_property C_ADDR_ALIGN_BITS DISPLAY_NAME C_ADDR_ALIGN_BITS +set_parameter_property C_ADDR_ALIGN_BITS TYPE INTEGER +set_parameter_property C_ADDR_ALIGN_BITS UNITS None +set_parameter_property C_ADDR_ALIGN_BITS HDL_PARAMETER true + +add_parameter C_DMA_LENGTH_WIDTH INTEGER 0 +set_parameter_property C_DMA_LENGTH_WIDTH DEFAULT_VALUE 14 +set_parameter_property C_DMA_LENGTH_WIDTH DISPLAY_NAME C_DMA_LENGTH_WIDTH +set_parameter_property C_DMA_LENGTH_WIDTH TYPE INTEGER +set_parameter_property C_DMA_LENGTH_WIDTH UNITS None +set_parameter_property C_DMA_LENGTH_WIDTH HDL_PARAMETER true + +add_parameter C_2D_TRANSFER INTEGER 0 +set_parameter_property C_2D_TRANSFER DEFAULT_VALUE 1 +set_parameter_property C_2D_TRANSFER DISPLAY_NAME C_2D_TRANSFER +set_parameter_property C_2D_TRANSFER TYPE INTEGER +set_parameter_property C_2D_TRANSFER UNITS None +set_parameter_property C_2D_TRANSFER HDL_PARAMETER true + +add_parameter C_CLKS_ASYNC_REQ_SRC INTEGER 0 +set_parameter_property C_CLKS_ASYNC_REQ_SRC DEFAULT_VALUE 1 +set_parameter_property C_CLKS_ASYNC_REQ_SRC DISPLAY_NAME C_CLKS_ASYNC_REQ_SRC +set_parameter_property C_CLKS_ASYNC_REQ_SRC TYPE INTEGER +set_parameter_property C_CLKS_ASYNC_REQ_SRC UNITS None +set_parameter_property C_CLKS_ASYNC_REQ_SRC HDL_PARAMETER true + +add_parameter C_CLKS_ASYNC_SRC_DEST INTEGER 0 +set_parameter_property C_CLKS_ASYNC_SRC_DEST DEFAULT_VALUE 1 +set_parameter_property C_CLKS_ASYNC_SRC_DEST DISPLAY_NAME C_CLKS_ASYNC_SRC_DEST +set_parameter_property C_CLKS_ASYNC_SRC_DEST TYPE INTEGER +set_parameter_property C_CLKS_ASYNC_SRC_DEST UNITS None +set_parameter_property C_CLKS_ASYNC_SRC_DEST HDL_PARAMETER true + +add_parameter C_CLKS_ASYNC_DEST_REQ INTEGER 0 +set_parameter_property C_CLKS_ASYNC_DEST_REQ DEFAULT_VALUE 1 +set_parameter_property C_CLKS_ASYNC_DEST_REQ DISPLAY_NAME C_CLKS_ASYNC_DEST_REQ +set_parameter_property C_CLKS_ASYNC_DEST_REQ TYPE INTEGER +set_parameter_property C_CLKS_ASYNC_DEST_REQ UNITS None +set_parameter_property C_CLKS_ASYNC_DEST_REQ HDL_PARAMETER true + +add_parameter C_AXI_SLICE_DEST INTEGER 0 +set_parameter_property C_AXI_SLICE_DEST DEFAULT_VALUE 0 +set_parameter_property C_AXI_SLICE_DEST DISPLAY_NAME C_AXI_SLICE_DEST +set_parameter_property C_AXI_SLICE_DEST TYPE INTEGER +set_parameter_property C_AXI_SLICE_DEST UNITS None +set_parameter_property C_AXI_SLICE_DEST HDL_PARAMETER true + +add_parameter C_AXI_SLICE_SRC INTEGER 0 +set_parameter_property C_AXI_SLICE_SRC DEFAULT_VALUE 0 +set_parameter_property C_AXI_SLICE_SRC DISPLAY_NAME C_AXI_SLICE_SRC +set_parameter_property C_AXI_SLICE_SRC TYPE INTEGER +set_parameter_property C_AXI_SLICE_SRC UNITS None +set_parameter_property C_AXI_SLICE_SRC HDL_PARAMETER true + +add_parameter C_SYNC_TRANSFER_START INTEGER 0 +set_parameter_property C_SYNC_TRANSFER_START DEFAULT_VALUE 0 +set_parameter_property C_SYNC_TRANSFER_START DISPLAY_NAME C_SYNC_TRANSFER_START +set_parameter_property C_SYNC_TRANSFER_START TYPE INTEGER +set_parameter_property C_SYNC_TRANSFER_START UNITS None +set_parameter_property C_SYNC_TRANSFER_START HDL_PARAMETER true + +add_parameter C_CYCLIC INTEGER 0 +set_parameter_property C_CYCLIC DEFAULT_VALUE 1 +set_parameter_property C_CYCLIC DISPLAY_NAME C_CYCLIC +set_parameter_property C_CYCLIC TYPE INTEGER +set_parameter_property C_CYCLIC UNITS None +set_parameter_property C_CYCLIC HDL_PARAMETER true + +add_parameter C_DMA_TYPE_DEST INTEGER 0 +set_parameter_property C_DMA_TYPE_DEST DEFAULT_VALUE 0 +set_parameter_property C_DMA_TYPE_DEST DISPLAY_NAME C_DMA_TYPE_DEST +set_parameter_property C_DMA_TYPE_DEST TYPE INTEGER +set_parameter_property C_DMA_TYPE_DEST UNITS None +set_parameter_property C_DMA_TYPE_DEST HDL_PARAMETER true + +add_parameter C_DMA_TYPE_SRC INTEGER 0 +set_parameter_property C_DMA_TYPE_SRC DEFAULT_VALUE 2 +set_parameter_property C_DMA_TYPE_SRC DISPLAY_NAME C_DMA_TYPE_SRC +set_parameter_property C_DMA_TYPE_SRC TYPE INTEGER +set_parameter_property C_DMA_TYPE_SRC UNITS None +set_parameter_property C_DMA_TYPE_SRC HDL_PARAMETER true + +# axi4 slave + +add_interface s_axi_clock clock end +add_interface_port s_axi_clock s_axi_aclk clk Input 1 + +add_interface s_axi_reset reset end +set_interface_property s_axi_reset associatedClock s_axi_clock +add_interface_port s_axi_reset s_axi_aresetn reset_n Input 1 + +add_interface s_axi axi4 end +set_interface_property s_axi associatedClock s_axi_clock +set_interface_property s_axi associatedReset s_axi_reset +add_interface_port s_axi s_axi_awvalid awvalid Input 1 +add_interface_port s_axi s_axi_awaddr awaddr Input 32 +add_interface_port s_axi s_axi_awready awready Output 1 +add_interface_port s_axi s_axi_wvalid wvalid Input 1 +add_interface_port s_axi s_axi_wdata wdata Input 32 +add_interface_port s_axi s_axi_wstrb wstrb Input 4 +add_interface_port s_axi s_axi_wready wready Output 1 +add_interface_port s_axi s_axi_bvalid bvalid Output 1 +add_interface_port s_axi s_axi_bresp bresp Output 2 +add_interface_port s_axi s_axi_bready bready Input 1 +add_interface_port s_axi s_axi_arvalid arvalid Input 1 +add_interface_port s_axi s_axi_araddr araddr Input 32 +add_interface_port s_axi s_axi_arready arready Output 1 +add_interface_port s_axi s_axi_rvalid rvalid Output 1 +add_interface_port s_axi s_axi_rresp rresp Output 2 +add_interface_port s_axi s_axi_rdata rdata Output 32 +add_interface_port s_axi s_axi_rready rready Input 1 +add_interface_port s_axi s_axi_awid awid Input 1 +add_interface_port s_axi s_axi_awlen awlen Input 8 +add_interface_port s_axi s_axi_awsize awsize Input 3 +add_interface_port s_axi s_axi_awburst awburst Input 2 +add_interface_port s_axi s_axi_awlock awlock Input 1 +add_interface_port s_axi s_axi_awcache awcache Input 4 +add_interface_port s_axi s_axi_awprot awprot Input 3 +add_interface_port s_axi s_axi_wlast wlast Input 1 +add_interface_port s_axi s_axi_bid bid Output 1 +add_interface_port s_axi s_axi_arid arid Input 1 +add_interface_port s_axi s_axi_arlen arlen Input 8 +add_interface_port s_axi s_axi_arsize arsize Input 3 +add_interface_port s_axi s_axi_arburst arburst Input 2 +add_interface_port s_axi s_axi_arlock arlock Input 1 +add_interface_port s_axi s_axi_arcache arcache Input 4 +add_interface_port s_axi s_axi_arprot arprot Input 3 +add_interface_port s_axi s_axi_rid rid Output 1 +add_interface_port s_axi s_axi_rlast rlast Output 1 + +# conditional interface + +proc axi_dmac_elaborate {} { + + # axi4 destination/source + + if {[get_parameter_value C_DMA_TYPE_DEST] == 0} { + + add_interface m_dest_axi_clock clock end + add_interface_port m_dest_axi_clock m_dest_axi_aclk clk Input 1 + + add_interface m_dest_axi_reset reset end + set_interface_property m_dest_axi_reset associatedClock m_dest_axi_clock + add_interface_port m_dest_axi_reset m_dest_axi_aresetn reset_n Input 1 + + add_interface m_dest_axi axi4 start + set_interface_property m_dest_axi associatedClock m_dest_axi_clock + set_interface_property m_dest_axi associatedReset m_dest_axi_reset + add_interface_port m_dest_axi m_dest_axi_awvalid awvalid Output 1 + add_interface_port m_dest_axi m_dest_axi_awaddr awaddr Output 32 + add_interface_port m_dest_axi m_dest_axi_awready awready Input 1 + add_interface_port m_dest_axi m_dest_axi_wvalid wvalid Output 1 + add_interface_port m_dest_axi m_dest_axi_wdata wdata Output C_DMA_DATA_WIDTH_DEST + add_interface_port m_dest_axi m_dest_axi_wstrb wstrb Output C_DMA_DATA_WIDTH_DEST/8 + add_interface_port m_dest_axi m_dest_axi_wready wready Input 1 + add_interface_port m_dest_axi m_dest_axi_bvalid bvalid Input 1 + add_interface_port m_dest_axi m_dest_axi_bresp bresp Input 2 + add_interface_port m_dest_axi m_dest_axi_bready bready Output 1 + add_interface_port m_dest_axi m_dest_axi_arvalid arvalid Output 1 + add_interface_port m_dest_axi m_dest_axi_araddr araddr Output 32 + add_interface_port m_dest_axi m_dest_axi_arready arready Input 1 + add_interface_port m_dest_axi m_dest_axi_rvalid rvalid Input 1 + add_interface_port m_dest_axi m_dest_axi_rresp rresp Input 2 + add_interface_port m_dest_axi m_dest_axi_rdata rdata Input C_DMA_DATA_WIDTH_DEST + add_interface_port m_dest_axi m_dest_axi_rready rready Output 1 + add_interface_port m_dest_axi m_dest_axi_awid awid Output 1 + add_interface_port m_dest_axi m_dest_axi_awlen awlen Output 8 + add_interface_port m_dest_axi m_dest_axi_awsize awsize Output 3 + add_interface_port m_dest_axi m_dest_axi_awburst awburst Output 2 + add_interface_port m_dest_axi m_dest_axi_awlock awlock Output 1 + add_interface_port m_dest_axi m_dest_axi_awcache awcache Output 4 + add_interface_port m_dest_axi m_dest_axi_awprot awprot Output 3 + add_interface_port m_dest_axi m_dest_axi_wlast wlast Output 1 + add_interface_port m_dest_axi m_dest_axi_bid bid Input 1 + add_interface_port m_dest_axi m_dest_axi_arid arid Output 1 + add_interface_port m_dest_axi m_dest_axi_arlen arlen Output 8 + add_interface_port m_dest_axi m_dest_axi_arsize arsize Output 3 + add_interface_port m_dest_axi m_dest_axi_arburst arburst Output 2 + add_interface_port m_dest_axi m_dest_axi_arlock arlock Output 1 + add_interface_port m_dest_axi m_dest_axi_arcache arcache Output 4 + add_interface_port m_dest_axi m_dest_axi_arprot arprot Output 3 + add_interface_port m_dest_axi m_dest_axi_rid rid Input 1 + add_interface_port m_dest_axi m_dest_axi_rlast rlast Input 1 + } + + if {[get_parameter_value C_DMA_TYPE_SRC] == 0} { + + add_interface m_src_axi_clock clock end + add_interface_port m_src_axi_clock m_src_axi_aclk clk Input 1 + + add_interface m_src_axi_reset reset end + set_interface_property m_src_axi_reset associatedClock m_src_axi_clock + add_interface_port m_src_axi_reset m_src_axi_aresetn reset_n Input 1 + + add_interface m_src_axi axi4 start + set_interface_property m_src_axi associatedClock m_src_axi_clock + set_interface_property m_src_axi associatedReset m_src_axi_reset + add_interface_port m_src_axi m_src_axi_awvalid awvalid Output 1 + add_interface_port m_src_axi m_src_axi_awaddr awaddr Output 32 + add_interface_port m_src_axi m_src_axi_awready awready Input 1 + add_interface_port m_src_axi m_src_axi_wvalid wvalid Output 1 + add_interface_port m_src_axi m_src_axi_wdata wdata Output C_DMA_DATA_WIDTH_SRC + add_interface_port m_src_axi m_src_axi_wstrb wstrb Output C_DMA_DATA_WIDTH_SRC/8 + add_interface_port m_src_axi m_src_axi_wready wready Input 1 + add_interface_port m_src_axi m_src_axi_bvalid bvalid Input 1 + add_interface_port m_src_axi m_src_axi_bresp bresp Input 2 + add_interface_port m_src_axi m_src_axi_bready bready Output 1 + add_interface_port m_src_axi m_src_axi_arvalid arvalid Output 1 + add_interface_port m_src_axi m_src_axi_araddr araddr Output 32 + add_interface_port m_src_axi m_src_axi_arready arready Input 1 + add_interface_port m_src_axi m_src_axi_rvalid rvalid Input 1 + add_interface_port m_src_axi m_src_axi_rresp rresp Input 2 + add_interface_port m_src_axi m_src_axi_rdata rdata Input C_DMA_DATA_WIDTH_SRC + add_interface_port m_src_axi m_src_axi_rready rready Output 1 + add_interface_port m_src_axi m_src_axi_awid awid Output 1 + add_interface_port m_src_axi m_src_axi_awlen awlen Output 8 + add_interface_port m_src_axi m_src_axi_awsize awsize Output 3 + add_interface_port m_src_axi m_src_axi_awburst awburst Output 2 + add_interface_port m_src_axi m_src_axi_awlock awlock Output 1 + add_interface_port m_src_axi m_src_axi_awcache awcache Output 4 + add_interface_port m_src_axi m_src_axi_awprot awprot Output 3 + add_interface_port m_src_axi m_src_axi_wlast wlast Output 1 + add_interface_port m_src_axi m_src_axi_bid bid Input 1 + add_interface_port m_src_axi m_src_axi_arid arid Output 1 + add_interface_port m_src_axi m_src_axi_arlen arlen Output 8 + add_interface_port m_src_axi m_src_axi_arsize arsize Output 3 + add_interface_port m_src_axi m_src_axi_arburst arburst Output 2 + add_interface_port m_src_axi m_src_axi_arlock arlock Output 1 + add_interface_port m_src_axi m_src_axi_arcache arcache Output 4 + add_interface_port m_src_axi m_src_axi_arprot arprot Output 3 + add_interface_port m_src_axi m_src_axi_rid rid Input 1 + add_interface_port m_src_axi m_src_axi_rlast rlast Input 1 + } + + # axis destination/source + + if {[get_parameter_value C_DMA_TYPE_DEST] == 1} { + + add_interface m_axis_clk clock end + add_interface_port m_axis_clk m_axis_aclk clk Input 1 + + add_interface m_axis_if conduit end + set_interface_property m_axis_if associatedClock m_axis_clk + add_interface_port m_axis_if m_axis_ready ready Input 1 + add_interface_port m_axis_if m_axis_valid valid Output 1 + add_interface_port m_axis_if m_axis_data data Output C_DMA_DATA_WIDTH_DEST + } + + if {[get_parameter_value C_DMA_TYPE_SRC] == 1} { + + add_interface s_axis_clk clock end + add_interface_port s_axis_clk s_axis_aclk clk Input 1 + + add_interface s_axis_if conduit end + set_interface_property s_axis_if associatedClock s_axis_clk + add_interface_port s_axis_if s_axis_ready ready Output 1 + add_interface_port s_axis_if s_axis_valid valid Input 1 + add_interface_port s_axis_if s_axis_data data Input C_DMA_DATA_WIDTH_SRC + add_interface_port s_axis_if s_axis_user user Input 1 + } + + # fifo destination/source + + if {[get_parameter_value C_DMA_TYPE_DEST] == 2} { + + add_interface fifo_rd_clock clock end + add_interface_port fifo_rd_clock fifo_rd_clk clk Input 1 + + add_interface fifo_rd_if conduit end + set_interface_property fifo_rd_if associatedClock fifo_rd_clock + add_interface_port fifo_rd_if fifo_rd_en rden Input 1 + add_interface_port fifo_rd_if fifo_rd_valid valid Output 1 + add_interface_port fifo_rd_if fifo_rd_dout data Output C_DMA_DATA_WIDTH_DEST + add_interface_port fifo_rd_if fifo_rd_underflow unf Output 1 + } + + if {[get_parameter_value C_DMA_TYPE_SRC] == 2} { + + add_interface fifo_wr_clock clock end + add_interface_port fifo_wr_clock fifo_wr_clk clk Input 1 + + add_interface fifo_wr_if conduit end + set_interface_property fifo_wr_if associatedClock fifo_wr_clock + add_interface_port fifo_wr_if fifo_wr_overflow ovf Output 1 + add_interface_port fifo_wr_if fifo_wr_en wren Input 1 + add_interface_port fifo_wr_if fifo_wr_din data Input C_DMA_DATA_WIDTH_SRC + add_interface_port fifo_wr_if fifo_wr_sync sync Input 1 + } + +} +