diff --git a/library/intel/adi_jesd204/adi_jesd204_glue.v b/library/intel/adi_jesd204/adi_jesd204_glue.v
index a59cf0aca..3f7978571 100644
--- a/library/intel/adi_jesd204/adi_jesd204_glue.v
+++ b/library/intel/adi_jesd204/adi_jesd204_glue.v
@@ -38,10 +38,12 @@
 module adi_jesd204_glue (
   input in_pll_powerdown,
   output out_pll_powerdown,
-  output out_mcgb_rst
+  output out_mcgb_rst,
+  output out_pll_select_gnd
 );
 
 assign out_pll_powerdown = in_pll_powerdown;
 assign out_mcgb_rst = in_pll_powerdown;
+assign out_pll_select_gnd = 1'b0;
 
 endmodule
diff --git a/library/intel/adi_jesd204/adi_jesd204_glue_hw.tcl b/library/intel/adi_jesd204/adi_jesd204_glue_hw.tcl
index 7ba0c016c..e2e8dd3c1 100644
--- a/library/intel/adi_jesd204/adi_jesd204_glue_hw.tcl
+++ b/library/intel/adi_jesd204/adi_jesd204_glue_hw.tcl
@@ -58,11 +58,18 @@ ad_ip_files adi_jesd204_glue [list \
 
 # parameters
 
+ad_ip_parameter IN_PLL_POWERDOWN_EN BOOLEAN 1 false
+
 proc jesd204_phy_glue_elab {} {
   add_interface in_pll_powerdown conduit end
   add_interface_port in_pll_powerdown in_pll_powerdown pll_powerdown Input 1
+  set_interface_property in_pll_powerdown ENABLED [get_parameter IN_PLL_POWERDOWN_EN]
+
   add_interface out_pll_powerdown conduit end
   add_interface_port out_pll_powerdown out_pll_powerdown pll_powerdown Output 1
   add_interface out_mcgb_rst conduit end
   add_interface_port out_mcgb_rst out_mcgb_rst mcgb_rst Output 1
+
+  add_interface out_pll_select_gnd conduit end
+  add_interface_port out_pll_select_gnd out_pll_select_gnd pll_select Output 1
 }
diff --git a/library/intel/adi_jesd204/adi_jesd204_hw.tcl b/library/intel/adi_jesd204/adi_jesd204_hw.tcl
index 2b879654a..26ee73fb8 100644
--- a/library/intel/adi_jesd204/adi_jesd204_hw.tcl
+++ b/library/intel/adi_jesd204/adi_jesd204_hw.tcl
@@ -69,7 +69,7 @@ set_module_property COMPOSITION_CALLBACK jesd204_compose
 # parameters
 
 ad_ip_parameter DEVICE_FAMILY STRING "" false {
-  VISIBLE false
+  VISIBLE true
 }
 
 ad_ip_parameter DEVICE STRING "" false {
@@ -134,43 +134,116 @@ ad_ip_parameter EXT_DEVICE_CLK_EN BOOLEAN 0 false { \
 }
 
 proc create_phy_reset_control {tx num_of_lanes sysclk_frequency} {
-
   global version
 
-  add_instance phy_reset_control altera_xcvr_reset_control $version
-  set_instance_property phy_reset_control SUPPRESS_ALL_WARNINGS true
-  set_instance_parameter_value phy_reset_control {CHANNELS} $num_of_lanes
-  set_instance_parameter_value phy_reset_control {SYS_CLK_IN_MHZ} $sysclk_frequency
-  set_instance_parameter_value phy_reset_control {TX_PLL_ENABLE} $tx
-  set_instance_parameter_value phy_reset_control {TX_ENABLE} $tx
-  set_instance_parameter_value phy_reset_control {RX_ENABLE} [expr !$tx]
-  set_instance_parameter_value phy_reset_control {SYNCHRONIZE_RESET} {0}
-  add_connection sys_clock.clk phy_reset_control.clock
-  add_connection link_reset.out_reset phy_reset_control.reset
-  add_connection sys_clock.clk_reset phy_reset_control.reset
+  set device [get_parameter_value DEVICE_FAMILY]
 
-  if {$tx} {
+  if {[string equal $device "Arria 10"]} {
+
+    add_instance phy_reset_control altera_xcvr_reset_control $version
+    set_instance_property phy_reset_control SUPPRESS_ALL_WARNINGS true
+    set_instance_parameter_value phy_reset_control {SYNCHRONIZE_RESET} {0}
+    set_instance_parameter_value phy_reset_control {CHANNELS} $num_of_lanes
+    set_instance_parameter_value phy_reset_control {SYS_CLK_IN_MHZ} $sysclk_frequency
+    set_instance_parameter_value phy_reset_control {TX_PLL_ENABLE} $tx
+    set_instance_parameter_value phy_reset_control {TX_ENABLE} $tx
+    set_instance_parameter_value phy_reset_control {RX_ENABLE} [expr !$tx]
+
+    add_connection sys_clock.clk phy_reset_control.clock
+    add_connection link_reset.out_reset phy_reset_control.reset
+    add_connection sys_clock.clk_reset phy_reset_control.reset
+
+    if {$tx} {
+      set_instance_parameter_value phy_reset_control {T_PLL_POWERDOWN} {1000}
+      set_instance_parameter_value phy_reset_control {gui_pll_cal_busy} {1}
+      set_instance_parameter_value phy_reset_control {T_TX_ANALOGRESET} {70000}
+      set_instance_parameter_value phy_reset_control {T_TX_DIGITALRESET} {70000}
+
+      add_connection phy_reset_control.tx_ready axi_xcvr.ready
+    } else {
+      set_instance_parameter_value phy_reset_control {T_RX_ANALOGRESET} {70000}
+      set_instance_parameter_value phy_reset_control {T_RX_DIGITALRESET} {4000}
+
+      add_connection phy_reset_control.rx_ready axi_xcvr.ready
+    }
+
+  } elseif {[string equal $device "Stratix 10"]} {
+
+    add_instance phy_reset_control altera_xcvr_reset_control_s10 $version
+    set_instance_parameter_value phy_reset_control {CHANNELS} $num_of_lanes
+    set_instance_parameter_value phy_reset_control {SYS_CLK_IN_MHZ} $sysclk_frequency
+    set_instance_parameter_value phy_reset_control {TX_ENABLE} $tx
+    set_instance_parameter_value phy_reset_control {RX_ENABLE} [expr !$tx]
+    set_instance_parameter_value phy_reset_control {REDUCED_SIM_TIME} {1}
     set_instance_parameter_value phy_reset_control {T_PLL_POWERDOWN} {1000}
-    set_instance_parameter_value phy_reset_control {gui_pll_cal_busy} {1}
-    set_instance_parameter_value phy_reset_control {T_TX_ANALOGRESET} {70000}
-    set_instance_parameter_value phy_reset_control {T_TX_DIGITALRESET} {70000}
+    set_instance_parameter_value phy_reset_control {T_PLL_LOCK_HYST} {1000}
+
+    add_connection sys_clock.clk phy_reset_control.clock
+    add_connection link_reset.out_reset phy_reset_control.reset
+    add_connection sys_clock.clk_reset phy_reset_control.reset
+
+    if {$tx} {
+      set_instance_parameter_value phy_reset_control {gui_pll_cal_busy} {1}
+      set_instance_parameter_value phy_reset_control {TX_MANUAL_RESET} {0}
+      set_instance_parameter_value phy_reset_control {T_TX_ANALOGRESET} {0}
+      set_instance_parameter_value phy_reset_control {T_TX_DIGITALRESET} {20}
+
+      add_connection phy_reset_control.tx_ready axi_xcvr.ready
+    } else {
+      set_instance_parameter_value phy_reset_control {RX_MANUAL_RESET} {0}
+      set_instance_parameter_value phy_reset_control {T_RX_ANALOGRESET} {40}
+      set_instance_parameter_value phy_reset_control {T_RX_DIGITALRESET} {5000}
+
+      add_connection phy_reset_control.rx_ready axi_xcvr.ready
+    }
 
-    add_connection phy_reset_control.tx_ready axi_xcvr.ready
   } else {
-    set_instance_parameter_value phy_reset_control {T_RX_ANALOGRESET} {70000}
-    set_instance_parameter_value phy_reset_control {T_RX_DIGITALRESET} {4000}
-
-    add_connection phy_reset_control.rx_ready axi_xcvr.ready
+    send_message error "Only Arria 10 and Stratix 10 are supported."
   }
 }
 
-proc create_lane_pll {id pllclk_frequency refclk_frequency num_lanes bonding_clocks_en} {
+proc create_lane_pll {id tx_or_rx_n pllclk_frequency refclk_frequency num_lanes bonding_clocks_en} {
 
   global version
 
-  add_instance lane_pll altera_xcvr_atx_pll_a10 $version
-  set_instance_property lane_pll SUPPRESS_ALL_INFO_MESSAGES true
-  set_instance_parameter_value lane_pll {enable_pll_reconfig} {1}
+  set device_family [get_parameter_value "DEVICE_FAMILY"]
+
+  if {$device_family == "Arria 10"} {
+    add_instance lane_pll altera_xcvr_atx_pll_a10 $version
+    if {$num_lanes > 6} {
+      set_instance_parameter_value lane_pll enable_mcgb {true}
+      if {$bonding_clocks_en} {
+          set_instance_parameter_value lane_pll {enable_bonding_clks} {true}
+          set_instance_parameter_value lane_pll {mcgb_div} {1}
+          set_instance_parameter_value lane_pll {set_ref_clk_div} {1}
+          set_instance_parameter_value lane_pll {pma_width} {40}
+      } else {
+          set_instance_parameter_value lane_pll enable_hfreq_clk {true}
+      }
+
+      add_instance glue adi_jesd204_glue 1.0
+      add_connection phy_reset_control.pll_powerdown glue.in_pll_powerdown
+      add_connection glue.out_pll_powerdown lane_pll.pll_powerdown
+      add_connection glue.out_mcgb_rst lane_pll.mcgb_rst
+    } else {
+      add_connection phy_reset_control.pll_powerdown lane_pll.pll_powerdown
+    }
+    set_instance_parameter_value lane_pll {enable_pll_reconfig} {1}
+  } elseif {$device_family == "Stratix 10"} {
+    add_instance lane_pll altera_xcvr_atx_pll_s10_htile $version
+    set_instance_parameter_value lane_pll {rcfg_enable} {1}
+
+    ## tie pll_select to GND
+    add_instance glue adi_jesd204_glue 1.0
+    set_instance_parameter_value glue {IN_PLL_POWERDOWN_EN} {0}
+    if {$tx_or_rx_n} {
+      add_connection glue.out_pll_select_gnd phy_reset_control.pll_select
+    }
+
+  } else {
+    send_message error "Only Arria 10 and Stratix 10 are supported."
+  }
+
   set_instance_parameter_value lane_pll {rcfg_separate_avmm_busy} {1}
   set_instance_parameter_value lane_pll {set_capability_reg_enable} {1}
   set_instance_parameter_value lane_pll {set_user_identifier} $id
@@ -178,24 +251,6 @@ proc create_lane_pll {id pllclk_frequency refclk_frequency num_lanes bonding_clo
   set_instance_parameter_value lane_pll {set_output_clock_frequency} $pllclk_frequency
   set_instance_parameter_value lane_pll {set_auto_reference_clock_frequency} $refclk_frequency
 
-  if {$num_lanes > 6} {
-    set_instance_parameter_value lane_pll enable_mcgb {true}    
-    if {$bonding_clocks_en} {
-        set_instance_parameter_value lane_pll {enable_bonding_clks} {true}
-        set_instance_parameter_value lane_pll {mcgb_div} {1}
-        set_instance_parameter_value lane_pll {set_ref_clk_div} {1}
-        set_instance_parameter_value lane_pll {pma_width} {40}
-    } else {
-        set_instance_parameter_value lane_pll enable_hfreq_clk {true}
-    }
-    add_instance glue adi_jesd204_glue
-    add_connection phy_reset_control.pll_powerdown glue.in_pll_powerdown
-    add_connection glue.out_pll_powerdown lane_pll.pll_powerdown
-    add_connection glue.out_mcgb_rst lane_pll.mcgb_rst
-  } else {
-    add_connection phy_reset_control.pll_powerdown lane_pll.pll_powerdown
-  }
-
   add_connection lane_pll.pll_locked phy_reset_control.pll_locked
   add_connection lane_pll.pll_cal_busy phy_reset_control.pll_cal_busy
   add_connection ref_clock.out_clk lane_pll.pll_refclk0
@@ -209,6 +264,9 @@ proc jesd204_get_max_lane_rate {device soft_pcs} {
   if {[string range $device 0 2] == "10A"} {
     set device_speedgrade [string range $device 13 13]
     set pma_speedgrade [string range $device 8 8]
+  } elseif {[string range $device 0 1] == "1S"} {
+    set device_speedgrade [string range $device 13 13]
+    set pma_speedgrade [string range $device 8 8]
   } else {
     # Assume fastest speed grade
     set device_speedgrade 1
@@ -242,9 +300,9 @@ proc jesd204_validate {{quiet false}} {
   set num_of_lanes [get_parameter_value "NUM_OF_LANES"]
   set tx_or_rx_n [get_parameter_value "TX_OR_RX_N"]
 
-  if {$device_family != "Arria 10"} {
+  if {$device_family != "Arria 10" && $device_family != "Stratix 10"} {
     if {!$quiet} {
-      send_message error "Only Arria 10 is supported."
+      send_message error "Only Arria 10 and Startix 10 are supported."
     }
     return false
   }
@@ -262,7 +320,7 @@ proc jesd204_validate {{quiet false}} {
   }
 
   set_parameter_property BONDING_CLOCKS_EN VISIBLE [expr ($num_of_lanes > 6) && ($tx_or_rx_n)]
-  
+
   return true
 }
 
@@ -310,22 +368,7 @@ proc jesd204_compose {} {
   add_interface ref_clk clock sink
   set_interface_property ref_clk EXPORT_OF ref_clock.in_clk
 
-  # FIXME: In phase alignment mode manual re-calibration fails
-  add_instance link_pll altera_xcvr_fpll_a10 $version
-  set_instance_property link_pll SUPPRESS_ALL_WARNINGS true
-  set_instance_property link_pll SUPPRESS_ALL_INFO_MESSAGES true
-  set_instance_parameter_value link_pll {gui_fpll_mode} {0}
-  set_instance_parameter_value link_pll {gui_reference_clock_frequency} $refclk_frequency
-  set_instance_parameter_value link_pll {gui_number_of_output_clocks} 1
-#  set_instance_parameter_value link_pll {gui_enable_phase_alignment} 1
-  set_instance_parameter_value link_pll {gui_desired_outclk0_frequency} $linkclk_frequency
-#  set pfdclk_frequency [get_instance_parameter_value link_pll gui_pfd_frequency]
-#  set_instance_parameter_value link_pll {gui_desired_outclk1_frequency} $pfdclk_frequency
-  set_instance_parameter_value link_pll {enable_pll_reconfig} {1}
-  set_instance_parameter_value link_pll {set_capability_reg_enable} {1}
-  set_instance_parameter_value link_pll {set_csr_soft_logic_enable} {1}
-  set_instance_parameter_value link_pll {rcfg_separate_avmm_busy} {1}
-  add_connection ref_clock.out_clk link_pll.pll_refclk0
+  set outclk_name ""
 
   ## link clock configuration (also known as device clock, which will be used
   ## by the upper layers for the data path, it can come from the PCS or external)
@@ -333,15 +376,69 @@ proc jesd204_compose {} {
   add_instance link_clock altera_clock_bridge $version
   set_instance_parameter_value link_clock {EXPLICIT_CLOCK_RATE} [expr $linkclk_frequency*1000000]
   set_instance_parameter_value link_clock {NUM_CLOCK_OUTPUTS} 2
-  add_connection link_pll.outclk0 link_clock.in_clk
-  add_interface link_clk clock source
 
   add_instance link_reset altera_reset_bridge $version
   set_instance_parameter_value link_reset {NUM_RESET_OUTPUTS} 2
+
+  if {$device_family == "Arria 10"} {
+
+    add_instance link_pll altera_xcvr_fpll_a10 $version
+    set_instance_parameter_value link_pll {gui_fpll_mode} {0}
+    set_instance_parameter_value link_pll {gui_reference_clock_frequency} $refclk_frequency
+    set_instance_parameter_value link_pll {gui_number_of_output_clocks} 1
+    set_instance_parameter_value link_pll {gui_desired_outclk0_frequency} $linkclk_frequency
+    set_instance_parameter_value link_pll {enable_pll_reconfig} {1}
+
+    set outclk_name "outclk0"
+
+    add_instance link_pll_reset_control altera_xcvr_reset_control $version
+    set_instance_parameter_value link_pll_reset_control {SYNCHRONIZE_RESET} {0}
+    set_instance_parameter_value link_pll_reset_control {SYS_CLK_IN_MHZ} $sysclk_frequency
+    set_instance_parameter_value link_pll_reset_control {TX_PLL_ENABLE} {1}
+    set_instance_parameter_value link_pll_reset_control {T_PLL_POWERDOWN} {1000}
+    set_instance_parameter_value link_pll_reset_control {TX_ENABLE} {0}
+    set_instance_parameter_value link_pll_reset_control {RX_ENABLE} {0}
+    add_connection sys_clock.clk link_pll_reset_control.clock
+    add_connection link_reset.out_reset link_pll_reset_control.reset
+    add_connection sys_clock.clk_reset link_pll_reset_control.reset
+    add_connection link_pll_reset_control.pll_powerdown link_pll.pll_powerdown
+
+  } elseif {$device_family == "Stratix 10"} {
+
+    send_message info "Instantiate a fpll_s10_htile for link_pll."
+    add_instance link_pll altera_xcvr_fpll_s10_htile 19.1.1
+    ## Primary Use is Core mode
+    set_instance_parameter_value link_pll {set_primary_use} 0
+    ## Basic Mode
+    set_instance_parameter_value link_pll {set_prot_mode} 0
+    set_instance_parameter_value link_pll {message_level} {error}
+    set_instance_parameter_value link_pll {set_refclk_cnt} {1}
+    set_instance_parameter_value link_pll {set_auto_reference_clock_frequency} $refclk_frequency
+    set_instance_parameter_value link_pll {set_output_clock_frequency} $linkclk_frequency
+    set_instance_parameter_value link_pll {set_bw_sel} {medium}
+    set_instance_parameter_value link_pll {rcfg_enable} {1}
+    set_instance_parameter_value link_pll {set_csr_soft_logic_enable} {1}
+    set_instance_parameter_value link_pll {set_capability_reg_enable} {1}
+
+    set outclk_name "outclk_div1"
+
+  } else {
+  ## Unsupported device
+    send_message error "Only Arria 10 and Stratix 10 are supported."
+  }
+
+  add_connection link_pll.$outclk_name link_clock.in_clk
+  add_interface link_clk clock source
+
   add_connection sys_clock.clk link_reset.clk
   add_interface link_reset reset source
   set_interface_property link_reset EXPORT_OF link_reset.out_reset_1
 
+  set_instance_parameter_value link_pll {set_capability_reg_enable} {1}
+  set_instance_parameter_value link_pll {set_csr_soft_logic_enable} {1}
+  set_instance_parameter_value link_pll {rcfg_separate_avmm_busy} {1}
+  add_connection ref_clock.out_clk link_pll.pll_refclk0
+
   add_connection sys_clock.clk_reset link_pll.reconfig_reset0
   add_connection sys_clock.clk link_pll.reconfig_clk0
 
@@ -360,23 +457,15 @@ proc jesd204_compose {} {
 
   add_interface link_pll_reconfig avalon slave
   set_interface_property link_pll_reconfig EXPORT_OF link_pll.reconfig_avmm0
+  set_interface_property link_pll_reconfig associatedClock sys_clk
+  set_interface_property link_pll_reconfig associatedReset sys_resetn
 
-  add_instance link_pll_reset_control altera_xcvr_reset_control $version
-  set_instance_parameter_value link_pll_reset_control {SYS_CLK_IN_MHZ} $sysclk_frequency
-  set_instance_parameter_value link_pll_reset_control {TX_PLL_ENABLE} {1}
-  set_instance_parameter_value link_pll_reset_control {T_PLL_POWERDOWN} {1000}
-  set_instance_parameter_value link_pll_reset_control {TX_ENABLE} {0}
-  set_instance_parameter_value link_pll_reset_control {RX_ENABLE} {0}
-  set_instance_parameter_value link_pll_reset_control {SYNCHRONIZE_RESET} {0}
-  add_connection sys_clock.clk link_pll_reset_control.clock
-  add_connection link_reset.out_reset link_pll_reset_control.reset
-  add_connection sys_clock.clk_reset link_pll_reset_control.reset
-  add_connection link_pll_reset_control.pll_powerdown link_pll.pll_powerdown
 
   create_phy_reset_control $tx_or_rx_n $num_of_lanes $sysclk_frequency
 
   add_instance phy jesd204_phy 1.0
   set_instance_parameter_value phy ID $id
+  set_instance_parameter_value phy DEVICE $device_family
   set_instance_parameter_value phy SOFT_PCS $soft_pcs
   set_instance_parameter_value phy TX_OR_RX_N $tx_or_rx_n
   set_instance_parameter_value phy LANE_RATE $lane_rate
@@ -406,15 +495,16 @@ proc jesd204_compose {} {
     set_interface_property link_clk EXPORT_OF link_clock.out_clk
   }
 
+  set phy_reset_intfs_s10 {analogreset_stat digitalreset_stat}
+
   if {$tx_or_rx_n} {
     set tx_rx "tx"
     set data_direction sink
     set jesd204_intfs {config control ilas_config event status}
-    set phy_reset_intfs {analogreset digitalreset cal_busy}   
+    set phy_reset_intfs {analogreset digitalreset cal_busy}
 
-    create_lane_pll $id $pllclk_frequency $refclk_frequency $num_of_lanes $bonding_clocks_en
-   
-    if {$num_of_lanes > 6} {          
+    create_lane_pll $id $tx_or_rx_n $pllclk_frequency $refclk_frequency $num_of_lanes $bonding_clocks_en
+    if {$num_of_lanes > 6} {
         if {$bonding_clocks_en} {
             add_connection lane_pll.tx_bonding_clocks phy.bonding_clocks
         } else {
@@ -461,6 +551,14 @@ proc jesd204_compose {} {
     add_connection phy_reset_control.${tx_rx}_${intf} phy.${intf}
   }
 
+  ## connect phy_reset_control interfaces specific to Stratix 10
+  if {$device_family == "Stratix 10"} {
+    foreach intf $phy_reset_intfs_s10 {
+      add_connection phy_reset_control.${tx_rx}_${intf} phy.${intf}
+    }
+
+  }
+
   set lane_map [regexp -all -inline {\S+} $lane_map]
   for {set i 0} {$i < $num_of_lanes} {incr i} {
     if {$lane_map != {}} {
@@ -498,4 +596,5 @@ proc jesd204_compose {} {
 
   add_interface serial_data conduit end
   set_interface_property serial_data EXPORT_OF phy.serial_data
+
 }
diff --git a/library/intel/avl_adxcfg/avl_adxcfg.v b/library/intel/avl_adxcfg/avl_adxcfg.v
index 010ad3c32..ef35110a9 100644
--- a/library/intel/avl_adxcfg/avl_adxcfg.v
+++ b/library/intel/avl_adxcfg/avl_adxcfg.v
@@ -35,7 +35,9 @@
 
 `timescale 1ns/1ps
 
-module avl_adxcfg (
+module avl_adxcfg #(
+
+  parameter ADDRESS_WIDTH = 10) (
 
   // reconfig sharing
 
@@ -44,28 +46,28 @@ module avl_adxcfg (
 
   input           rcfg_in_read_0,
   input           rcfg_in_write_0,
-  input   [ 9:0]  rcfg_in_address_0,
+  input   [ADDRESS_WIDTH-1:0]  rcfg_in_address_0,
   input   [31:0]  rcfg_in_writedata_0,
   output  [31:0]  rcfg_in_readdata_0,
   output          rcfg_in_waitrequest_0,
 
   input           rcfg_in_read_1,
   input           rcfg_in_write_1,
-  input   [ 9:0]  rcfg_in_address_1,
+  input   [ADDRESS_WIDTH-1:0]  rcfg_in_address_1,
   input   [31:0]  rcfg_in_writedata_1,
   output  [31:0]  rcfg_in_readdata_1,
   output          rcfg_in_waitrequest_1,
 
   output          rcfg_out_read_0,
   output          rcfg_out_write_0,
-  output  [ 9:0]  rcfg_out_address_0,
+  output  [ADDRESS_WIDTH-1:0]  rcfg_out_address_0,
   output  [31:0]  rcfg_out_writedata_0,
   input   [31:0]  rcfg_out_readdata_0,
   input           rcfg_out_waitrequest_0,
 
   output          rcfg_out_read_1,
   output          rcfg_out_write_1,
-  output  [ 9:0]  rcfg_out_address_1,
+  output  [ADDRESS_WIDTH-1:0]  rcfg_out_address_1,
   output  [31:0]  rcfg_out_writedata_1,
   input   [31:0]  rcfg_out_readdata_1,
   input           rcfg_out_waitrequest_1);
@@ -75,7 +77,7 @@ module avl_adxcfg (
   reg     [ 1:0]  rcfg_select = 'd0;
   reg             rcfg_read_int = 'd0;
   reg             rcfg_write_int = 'd0;
-  reg     [ 9:0]  rcfg_address_int = 'd0;
+  reg     [ADDRESS_WIDTH-1:0]  rcfg_address_int = 'd0;
   reg     [31:0]  rcfg_writedata_int = 'd0;
   reg     [31:0]  rcfg_readdata_int = 'd0;
   reg             rcfg_waitrequest_int_0 = 'd1;
@@ -109,7 +111,7 @@ module avl_adxcfg (
       rcfg_select <= 2'd0;
       rcfg_read_int <= 1'd0;
       rcfg_write_int <= 1'd0;
-      rcfg_address_int <= 10'd0;
+      rcfg_address_int <= 'd0;
       rcfg_writedata_int <= 32'd0;
       rcfg_readdata_int <= 32'd0;
       rcfg_waitrequest_int_0 <= 1'b1;
@@ -120,7 +122,7 @@ module avl_adxcfg (
           rcfg_select <= 2'd0;
           rcfg_read_int <= 1'b0;
           rcfg_write_int <= 1'b0;
-          rcfg_address_int <= 10'd0;
+          rcfg_address_int <= 'd0;
           rcfg_writedata_int <= 32'd0;
         end
         rcfg_readdata_int <= rcfg_readdata_s;
@@ -148,7 +150,7 @@ module avl_adxcfg (
         rcfg_select <= 2'd0;
         rcfg_read_int <= 1'd0;
         rcfg_write_int <= 1'd0;
-        rcfg_address_int <= 10'd0;
+        rcfg_address_int <= 'd0;
         rcfg_writedata_int <= 32'd0;
         rcfg_readdata_int <= 32'd0;
         rcfg_waitrequest_int_0 <= 1'b1;
diff --git a/library/intel/avl_adxcfg/avl_adxcfg_hw.tcl b/library/intel/avl_adxcfg/avl_adxcfg_hw.tcl
index 613b75713..2e2117e4d 100644
--- a/library/intel/avl_adxcfg/avl_adxcfg_hw.tcl
+++ b/library/intel/avl_adxcfg/avl_adxcfg_hw.tcl
@@ -6,6 +6,7 @@ set_module_property DESCRIPTION "Avalon ADXCFG Core"
 set_module_property VERSION 1.0
 set_module_property GROUP "Analog Devices"
 set_module_property DISPLAY_NAME avl_adxcfg
+set_module_property ELABORATION_CALLBACK elaborate
 
 # files
 
@@ -13,6 +14,12 @@ add_fileset quartus_synth QUARTUS_SYNTH "" ""
 set_fileset_property quartus_synth TOP_LEVEL avl_adxcfg
 add_fileset_file avl_adxcfg.v VERILOG PATH avl_adxcfg.v TOP_LEVEL_FILE
 
+# add exportable hdl parameter
+
+add_parameter ADDRESS_WIDTH INTEGER 10
+set_parameter_property ADDRESS_WIDTH AFFECTS_GENERATION false
+set_parameter_property ADDRESS_WIDTH HDL_PARAMETER true
+
 # reconfiguration interfaces
 
 add_interface rcfg_clk  clock sink
@@ -22,34 +29,34 @@ add_interface rcfg_reset_n reset end
 set_interface_property rcfg_reset_n associatedClock rcfg_clk
 add_interface_port rcfg_reset_n rcfg_reset_n reset_n Input 1
 
-for {set n 0} {$n < 2} {incr n} {
+proc elaborate {} {
+  for {set n 0} {$n < 2} {incr n} {
 
-  add_interface rcfg_s${n} avalon slave
-  add_interface rcfg_m${n} avalon master
+    add_interface rcfg_s${n} avalon slave
+    add_interface rcfg_m${n} avalon master
 
-  add_interface_port rcfg_s${n} rcfg_in_read_${n} read Input 1
-  add_interface_port rcfg_s${n} rcfg_in_write_${n} write Input 1
-  add_interface_port rcfg_s${n} rcfg_in_address_${n} address Input 10
-  add_interface_port rcfg_s${n} rcfg_in_writedata_${n} writedata Input 32
-  add_interface_port rcfg_s${n} rcfg_in_readdata_${n} readdata Output 32
-  add_interface_port rcfg_s${n} rcfg_in_waitrequest_${n} waitrequest Output 1
-  add_interface_port rcfg_m${n} rcfg_out_read_${n} read Output 1
-  add_interface_port rcfg_m${n} rcfg_out_write_${n} write Output 1
-  add_interface_port rcfg_m${n} rcfg_out_address_${n} address Output 10
-  add_interface_port rcfg_m${n} rcfg_out_writedata_${n} writedata Output 32
-  add_interface_port rcfg_m${n} rcfg_out_readdata_${n} readdata Input 32
-  add_interface_port rcfg_m${n} rcfg_out_waitrequest_${n} waitrequest Input 1
+    add_interface_port rcfg_s${n} rcfg_in_read_${n} read Input 1
+    add_interface_port rcfg_s${n} rcfg_in_write_${n} write Input 1
+    add_interface_port rcfg_s${n} rcfg_in_address_${n} address Input [get_parameter_value ADDRESS_WIDTH]
+    add_interface_port rcfg_s${n} rcfg_in_writedata_${n} writedata Input 32
+    add_interface_port rcfg_s${n} rcfg_in_readdata_${n} readdata Output 32
+    add_interface_port rcfg_s${n} rcfg_in_waitrequest_${n} waitrequest Output 1
+    add_interface_port rcfg_m${n} rcfg_out_read_${n} read Output 1
+    add_interface_port rcfg_m${n} rcfg_out_write_${n} write Output 1
+    add_interface_port rcfg_m${n} rcfg_out_address_${n} address Output [get_parameter_value ADDRESS_WIDTH]
+    add_interface_port rcfg_m${n} rcfg_out_writedata_${n} writedata Output 32
+    add_interface_port rcfg_m${n} rcfg_out_readdata_${n} readdata Input 32
+    add_interface_port rcfg_m${n} rcfg_out_waitrequest_${n} waitrequest Input 1
 
-  set_interface_property rcfg_s${n} associatedClock rcfg_clk
-  set_interface_property rcfg_s${n} associatedReset rcfg_reset_n
-  set_interface_property rcfg_s${n} addressUnits WORDS
-  set_interface_property rcfg_s${n} burstCountUnits WORDS
-  set_interface_property rcfg_s${n} explicitAddressSpan 0
-  set_interface_property rcfg_m${n} associatedClock rcfg_clk
-  set_interface_property rcfg_m${n} associatedReset rcfg_reset_n
-  set_interface_property rcfg_m${n} addressUnits WORDS
-  set_interface_property rcfg_m${n} burstCountUnits WORDS
+    set_interface_property rcfg_s${n} associatedClock rcfg_clk
+    set_interface_property rcfg_s${n} associatedReset rcfg_reset_n
+    set_interface_property rcfg_s${n} addressUnits WORDS
+    set_interface_property rcfg_s${n} burstCountUnits WORDS
+    set_interface_property rcfg_s${n} explicitAddressSpan 0
+    set_interface_property rcfg_m${n} associatedClock rcfg_clk
+    set_interface_property rcfg_m${n} associatedReset rcfg_reset_n
+    set_interface_property rcfg_m${n} addressUnits WORDS
+    set_interface_property rcfg_m${n} burstCountUnits WORDS
+  }
 }
 
-
-
diff --git a/library/intel/jesd204_phy/jesd204_phy_glue_hw.tcl b/library/intel/jesd204_phy/jesd204_phy_glue_hw.tcl
index 79358a7f8..9b569351f 100644
--- a/library/intel/jesd204_phy/jesd204_phy_glue_hw.tcl
+++ b/library/intel/jesd204_phy/jesd204_phy_glue_hw.tcl
@@ -64,6 +64,7 @@ ad_ip_files jesd204_glue [list \
 
 # parameters
 
+ad_ip_parameter DEVICE STRING "" false
 ad_ip_parameter TX_OR_RX_N BOOLEAN false false
 ad_ip_parameter SOFT_PCS BOOLEAN false false
 ad_ip_parameter BONDING_CLOCKS_EN BOOLEAN false false
@@ -226,6 +227,7 @@ proc jesd204_phy_glue_elab {} {
   variable sig_offset
   variable const_offset
 
+  set device [get_parameter DEVICE]
   set soft_pcs [get_parameter SOFT_PCS]
   set num_of_lanes [get_parameter NUM_OF_LANES]
   set bonding_clocks_en [get_parameter BONDING_CLOCKS_EN]
@@ -233,6 +235,16 @@ proc jesd204_phy_glue_elab {} {
   set sig_offset 0
   set const_offset 0
 
+  if {[string equal $device "Arria 10"]} {
+    set reconfig_avmm_address_width 10
+    set unused_width_per_lane 88
+  } elseif {[string equal $device "Stratix 10"]} {
+    set reconfig_avmm_address_width 11
+    set unused_width_per_lane 40
+  } else {
+    send_message error "Only Arria 10 and Stratix 10 are supported."
+  }
+
   glue_add_if $num_of_lanes reconfig_clk clock sink true
   glue_add_if_port $num_of_lanes reconfig_clk reconfig_clk clk Input 1 true
 
@@ -244,7 +256,7 @@ proc jesd204_phy_glue_elab {} {
     set_interface_property reconfig_avmm_${i} associatedClock reconfig_clk
     set_interface_property reconfig_avmm_${i} associatedReset reconfig_reset
   }
-  glue_add_if_port $num_of_lanes reconfig_avmm reconfig_address address Input 10
+  glue_add_if_port $num_of_lanes reconfig_avmm reconfig_address address Input $reconfig_avmm_address_width
   glue_add_if_port $num_of_lanes reconfig_avmm reconfig_read read Input 1
   glue_add_if_port $num_of_lanes reconfig_avmm reconfig_readdata readdata Output 32
   glue_add_if_port $num_of_lanes reconfig_avmm reconfig_waitrequest waitrequest Output 1
@@ -266,7 +278,7 @@ proc jesd204_phy_glue_elab {} {
     }
 
     if {$soft_pcs} {
-      set unused_width [expr $num_of_lanes * 88]
+      set unused_width [expr $num_of_lanes * $unused_width_per_lane]
 
       glue_add_const_conduit tx_enh_data_valid $num_of_lanes
 
diff --git a/library/intel/jesd204_phy/jesd204_phy_hw.tcl b/library/intel/jesd204_phy/jesd204_phy_hw.tcl
index 1c26d9f88..3150a1072 100644
--- a/library/intel/jesd204_phy/jesd204_phy_hw.tcl
+++ b/library/intel/jesd204_phy/jesd204_phy_hw.tcl
@@ -63,6 +63,7 @@ set_module_property INTERNAL false
 
 # parameters
 
+ad_ip_parameter DEVICE STRING "Stratix 10" false
 ad_ip_parameter ID NATURAL 0 false
 ad_ip_parameter SOFT_PCS BOOLEAN false false
 ad_ip_parameter TX_OR_RX_N BOOLEAN false false
@@ -78,6 +79,7 @@ proc jesd204_phy_composition_callback {} {
 
   global version
 
+  set device [get_parameter_value "DEVICE"]
   set soft_pcs [get_parameter_value "SOFT_PCS"]
   set tx [get_parameter_value "TX_OR_RX_N"]
   set lane_rate [get_parameter_value "LANE_RATE"]
@@ -91,6 +93,14 @@ proc jesd204_phy_composition_callback {} {
 
   set link_clk_frequency [expr $lane_rate / 40]
 
+  if {[string equal $device "Arria 10"]} {
+    set device_type 1
+  } elseif {[string equal $device "Stratix 10"]} {
+    set device_type 2
+  } else {
+    set device_type 0
+  }
+
   add_instance link_clock clock_source $version
   set_instance_parameter_value link_clock {clockFrequency} [expr $link_clk_frequency*1000000]
   add_interface link_clk clock sink
@@ -98,9 +108,23 @@ proc jesd204_phy_composition_callback {} {
   add_interface link_reset reset sink
   set_interface_property link_reset EXPORT_OF link_clock.clk_in_reset
 
-  add_instance native_phy altera_xcvr_native_a10 19.1
-  set_instance_property native_phy SUPPRESS_ALL_WARNINGS true
-  set_instance_property native_phy SUPPRESS_ALL_INFO_MESSAGES true
+  ## Arria10
+  if {$device_type == 1} {
+    add_instance native_phy altera_xcvr_native_a10 19.1
+    set_instance_parameter_value native_phy {enh_txfifo_mode} "Phase compensation"
+    set_instance_parameter_value native_phy {enh_rxfifo_mode} "Phase compensation"
+    set_instance_property native_phy SUPPRESS_ALL_WARNINGS true
+    set_instance_property native_phy SUPPRESS_ALL_INFO_MESSAGES true
+  ## Stratix 10
+  } elseif {$device_type == 2} {
+    add_instance native_phy altera_xcvr_native_s10_htile $version
+    set_instance_parameter_value native_phy {tx_fifo_mode} "Phase compensation"
+    set_instance_parameter_value native_phy {rx_fifo_mode} "Phase compensation"
+  ## Unsupported device
+  } else {
+    send_message error "Only Arria 10 and Stratix 10 are supported."
+  }
+
   if {$soft_pcs} {
     set_instance_parameter_value native_phy {protocol_mode} "basic_enh"
   } else {
@@ -132,14 +156,12 @@ proc jesd204_phy_composition_callback {} {
         set_instance_parameter_value native_phy {bonded_mode} "not_bonded"
     }
     set_instance_parameter_value native_phy {enable_port_tx_pma_elecidle} 0
-    set_instance_parameter_value native_phy {enh_txfifo_mode} "Phase compensation"
   } else {
     set_instance_parameter_value native_phy {duplex_mode} "rx"
     set_instance_parameter_value native_phy {set_cdr_refclk_freq} $refclk_frequency
     set_instance_parameter_value native_phy {enable_port_rx_is_lockedtodata} 1
     set_instance_parameter_value native_phy {enable_port_rx_is_lockedtoref} 0
     set_instance_parameter_value native_phy {enable_ports_rx_manual_cdr_mode} 0
-    set_instance_parameter_value native_phy {enh_rxfifo_mode} "Phase compensation"
   }
 
   set_instance_parameter_value native_phy {channels} $num_of_lanes
@@ -159,6 +181,7 @@ proc jesd204_phy_composition_callback {} {
   set_instance_parameter_value native_phy {set_prbs_soft_logic_enable} 0
 
   add_instance phy_glue jesd204_phy_glue 1.0
+  set_instance_parameter_value phy_glue DEVICE $device
   set_instance_parameter_value phy_glue TX_OR_RX_N $tx
   set_instance_parameter_value phy_glue SOFT_PCS $soft_pcs
   set_instance_parameter_value phy_glue NUM_OF_LANES $num_of_lanes
@@ -200,7 +223,7 @@ proc jesd204_phy_composition_callback {} {
       add_connection link_clock.clk phy_glue.tx_coreclkin
     }
 
-    if {$soft_pcs} {
+    if { $soft_pcs == true && $device_type == 1 }  {
       add_connection phy_glue.phy_tx_enh_data_valid native_phy.tx_enh_data_valid
     }
 
@@ -218,6 +241,15 @@ proc jesd204_phy_composition_callback {} {
       add_connection phy_glue.phy_tx_datak native_phy.tx_datak
       add_connection phy_glue.phy_tx_polinv native_phy.tx_polinv
     }
+
+    ## Startix 10
+    if {$device_type == 2} {
+      foreach x {analogreset_stat digitalreset_stat} {
+        add_interface ${x} conduit end
+        set_interface_property ${x} EXPORT_OF native_phy.tx_${x}
+      }
+    }
+
   } else {
 
     add_interface ref_clk clock sink
@@ -245,6 +277,15 @@ proc jesd204_phy_composition_callback {} {
       }
       add_connection phy_glue.phy_rx_polinv native_phy.rx_polinv
     }
+
+    ## Startix 10
+    if {$device_type == 2} {
+      foreach x {analogreset_stat digitalreset_stat} {
+        add_interface ${x} conduit end
+        set_interface_property ${x} EXPORT_OF native_phy.rx_${x}
+      }
+    }
+
   }
 
   for {set i 0} {$i < $num_of_lanes} {incr i} {