board: optimize interconnect for performance
parent
d5eaadd872
commit
ed28b47203
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@ -45,25 +45,30 @@ proc ad_connect {p_name_1 p_name_2} {
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if {$m_name_1 eq ""} {
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if {$m_name_1 eq ""} {
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if {[get_property CLASS $m_name_2] eq "bd_intf_pin"} {
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if {[get_property CLASS $m_name_2] eq "bd_intf_pin"} {
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puts "create_bd_intf_net $p_name_1"
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create_bd_intf_net $p_name_1
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create_bd_intf_net $p_name_1
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}
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}
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if {[get_property CLASS $m_name_2] eq "bd_pin"} {
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if {[get_property CLASS $m_name_2] eq "bd_pin"} {
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puts "create_bd_net $p_name_1"
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create_bd_net $p_name_1
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create_bd_net $p_name_1
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}
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}
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set m_name_1 [ad_connect_type $p_name_1]
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set m_name_1 [ad_connect_type $p_name_1]
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}
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}
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if {[get_property CLASS $m_name_1] eq "bd_intf_pin"} {
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if {[get_property CLASS $m_name_1] eq "bd_intf_pin"} {
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puts "connect_bd_intf_net $m_name_1 $m_name_2"
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connect_bd_intf_net $m_name_1 $m_name_2
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connect_bd_intf_net $m_name_1 $m_name_2
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return
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return
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}
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}
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if {[get_property CLASS $m_name_1] eq "bd_pin"} {
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if {[get_property CLASS $m_name_1] eq "bd_pin"} {
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puts "connect_bd_net $m_name_1 $m_name_2"
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connect_bd_net $m_name_1 $m_name_2
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connect_bd_net $m_name_1 $m_name_2
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return
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return
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}
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}
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if {[get_property CLASS $m_name_1] eq "bd_net"} {
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if {[get_property CLASS $m_name_1] eq "bd_net"} {
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puts "connect_bd_net -net $m_name_1 $m_name_2"
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connect_bd_net -net $m_name_1 $m_name_2
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connect_bd_net -net $m_name_1 $m_name_2
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return
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return
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}
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}
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@ -204,6 +209,10 @@ proc ad_mem_hpx_interconnect {p_sel p_clk p_name} {
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assign_bd_address $m_addr_seg
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assign_bd_address $m_addr_seg
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}
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}
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if {$m_interconnect_index == 3} {
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set_property CONFIG.STRATEGY {2} $m_interconnect_cell
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}
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if {$p_sel eq "MEM"} {set sys_mem_interconnect_index $m_interconnect_index}
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if {$p_sel eq "MEM"} {set sys_mem_interconnect_index $m_interconnect_index}
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if {$p_sel eq "HP0"} {set sys_hp0_interconnect_index $m_interconnect_index}
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if {$p_sel eq "HP0"} {set sys_hp0_interconnect_index $m_interconnect_index}
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if {$p_sel eq "HP1"} {set sys_hp1_interconnect_index $m_interconnect_index}
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if {$p_sel eq "HP1"} {set sys_hp1_interconnect_index $m_interconnect_index}
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