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fmcomms2: c5soc: Connect ADC, DAC and VGA DMA to different bridge interconnects 

We have enough bridge interconnect to give each DMA its own, so use them.
This makes sure that they do not interfere with each others transfers to
much. The SDRAM controller side of the FPGA2SDRAM bridges FIFO runs at a
much faster frequency then what we are able to use in the fabric. So its
better to do the arbitration on that side of the bus to make sure that we
can utilize the buses in the FPGA fabric to the maximum for each DMA core.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2014-09-12 16:08:52 +02:00
parent 17a993032b
commit ecc498313c
1 changed files with 291 additions and 253 deletions
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128
projects/fmcomms2/c5soc/system_bd.qsys
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@ -110,14 +110,6 @@
type = "String"; type = "String";
} }
} }
element axi_dmac_dac.s_axi
{
datum baseAddress
{
value = "16384";
type = "String";
}
}
element axi_dmac_adc.s_axi element axi_dmac_adc.s_axi
{ {
datum baseAddress datum baseAddress
@ -126,6 +118,14 @@
type = "String"; type = "String";
} }
} }
element axi_dmac_dac.s_axi
{
datum baseAddress
{
value = "16384";
type = "String";
}
}
element spi_ad9361 element spi_ad9361
{ {
datum _sortIndex datum _sortIndex
@ -762,8 +762,8 @@
<parameter name="F2S_Width" value="2" /> <parameter name="F2S_Width" value="2" />
<parameter name="S2F_Width" value="2" /> <parameter name="S2F_Width" value="2" />
<parameter name="LWH2F_Enable" value="true" /> <parameter name="LWH2F_Enable" value="true" />
<parameter name="F2SDRAM_Type">Avalon-MM Bidirectional</parameter> <parameter name="F2SDRAM_Type">Avalon-MM Bidirectional,AXI-3,AXI-3</parameter>
<parameter name="F2SDRAM_Width" value="64" /> <parameter name="F2SDRAM_Width" value="64,64,64" />
<parameter name="BONDING_OUT_ENABLED" value="false" /> <parameter name="BONDING_OUT_ENABLED" value="false" />
<parameter name="S2FCLK_COLDRST_Enable" value="false" /> <parameter name="S2FCLK_COLDRST_Enable" value="false" />
<parameter name="S2FCLK_PENDINGRST_Enable" value="false" /> <parameter name="S2FCLK_PENDINGRST_Enable" value="false" />
@ -836,9 +836,9 @@
<parameter name="F2H_AXI_CLOCK_FREQ" value="50000000" /> <parameter name="F2H_AXI_CLOCK_FREQ" value="50000000" />
<parameter name="H2F_AXI_CLOCK_FREQ" value="50000000" /> <parameter name="H2F_AXI_CLOCK_FREQ" value="50000000" />
<parameter name="H2F_LW_AXI_CLOCK_FREQ" value="50000000" /> <parameter name="H2F_LW_AXI_CLOCK_FREQ" value="50000000" />
<parameter name="F2H_SDRAM0_CLOCK_FREQ" value="80000000" /> <parameter name="F2H_SDRAM0_CLOCK_FREQ" value="50000000" />
<parameter name="F2H_SDRAM1_CLOCK_FREQ" value="100" /> <parameter name="F2H_SDRAM1_CLOCK_FREQ" value="80000000" />
<parameter name="F2H_SDRAM2_CLOCK_FREQ" value="100" /> <parameter name="F2H_SDRAM2_CLOCK_FREQ" value="80000000" />
<parameter name="F2H_SDRAM3_CLOCK_FREQ" value="100" /> <parameter name="F2H_SDRAM3_CLOCK_FREQ" value="100" />
<parameter name="F2H_SDRAM4_CLOCK_FREQ" value="100" /> <parameter name="F2H_SDRAM4_CLOCK_FREQ" value="100" />
<parameter name="F2H_SDRAM5_CLOCK_FREQ" value="100" /> <parameter name="F2H_SDRAM5_CLOCK_FREQ" value="100" />
@ -1369,11 +1369,6 @@
version="14.0" version="14.0"
start="sys_clk.clk" start="sys_clk.clk"
end="axi_ad9361.delay_clock" /> end="axi_ad9361.delay_clock" />
<connection
kind="clock"
version="14.0"
start="sys_hps.h2f_user0_clock"
end="sys_hps.f2h_sdram0_clock" />
<connection <connection
kind="clock" kind="clock"
version="14.0" version="14.0"
@ -1403,15 +1398,6 @@
version="14.0" version="14.0"
start="sys_clk.clk_reset" start="sys_clk.clk_reset"
end="axi_dmac_dac.m_src_axi_reset" /> end="axi_dmac_dac.m_src_axi_reset" />
<connection
kind="avalon"
version="14.0"
start="axi_dmac_dac.m_src_axi"
end="sys_hps.f2h_sdram0_data">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection <connection
kind="clock" kind="clock"
version="14.0" version="14.0"
@ -1441,15 +1427,6 @@
version="14.0" version="14.0"
start="sys_clk.clk_reset" start="sys_clk.clk_reset"
end="axi_dmac_adc.m_dest_axi_reset" /> end="axi_dmac_adc.m_dest_axi_reset" />
<connection
kind="avalon"
version="14.0"
start="axi_dmac_adc.m_dest_axi"
end="sys_hps.f2h_sdram0_data">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection <connection
kind="interrupt" kind="interrupt"
version="14.0" version="14.0"
@ -1541,15 +1518,6 @@
version="14.0" version="14.0"
start="vga_frame_reader.avalon_streaming_source" start="vga_frame_reader.avalon_streaming_source"
end="vga_clock_video_output.din" /> end="vga_clock_video_output.din" />
<connection
kind="avalon"
version="14.0"
start="vga_frame_reader.avalon_master"
end="sys_hps.f2h_axi_slave">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection <connection
kind="clock" kind="clock"
version="14.0" version="14.0"
@ -1562,6 +1530,76 @@
end="vga_frame_reader.interrupt_sender"> end="vga_frame_reader.interrupt_sender">
<parameter name="irqNumber" value="4" /> <parameter name="irqNumber" value="4" />
</connection> </connection>
<connection
kind="clock"
version="14.0"
start="sys_clk.clk"
end="sys_hps.f2h_sdram0_clock" />
<connection
kind="avalon"
version="14.0"
start="vga_frame_reader.avalon_master"
end="sys_hps.f2h_sdram0_data">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="14.0"
start="axi_dmac_adc.m_dest_axi"
end="sys_hps.f2h_sdram1_data">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="14.0"
start="axi_dmac_dac.m_src_axi"
end="sys_hps.f2h_sdram2_data">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="clock"
version="14.0"
start="sys_hps.h2f_user0_clock"
end="sys_hps.f2h_sdram2_clock" />
<connection
kind="clock"
version="14.0"
start="sys_hps.h2f_user0_clock"
end="sys_hps.f2h_sdram1_clock" />
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" /> <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="2" /> <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="2" />
<interconnectRequirement
for="mm_interconnect_4|axi_dmac_dac_m_src_axi_agent.write_cp/router.sink"
name="qsys_mm.postTransform.pipelineCount"
value="0" />
<interconnectRequirement
for="mm_interconnect_4|cmd_mux_001"
name="qsys_mm.postTransform.pipelineCount"
value="0" />
<interconnectRequirement
for="mm_interconnect_4|cmd_mux"
name="qsys_mm.postTransform.pipelineCount"
value="0" />
<interconnectRequirement
for="mm_interconnect_3|cmd_mux_001"
name="qsys_mm.postTransform.pipelineCount"
value="0" />
<interconnectRequirement
for="mm_interconnect_3|cmd_mux"
name="qsys_mm.postTransform.pipelineCount"
value="0" />
<interconnectRequirement
for="mm_interconnect_2|cmd_mux"
name="qsys_mm.postTransform.pipelineCount"
value="0" />
<interconnectRequirement
for="mm_interconnect_0|cmd_mux"
name="qsys_mm.postTransform.pipelineCount"
value="0" />
</system> </system>