From ecc498313c58aa143a8906eed658081e88238ee6 Mon Sep 17 00:00:00 2001
From: Lars-Peter Clausen <lars@metafoo.de>
Date: Fri, 12 Sep 2014 16:08:52 +0200
Subject: [PATCH] fmcomms2: c5soc: Connect ADC, DAC and VGA DMA to different
 bridge interconnects

We have enough bridge interconnect to give each DMA its own, so use them.
This makes sure that they do not interfere with each others transfers to
much. The SDRAM controller side of the FPGA2SDRAM bridges FIFO runs at a
much faster frequency then what we are able to use in the fabric. So its
better to do the arbitration on that side of the bus to make sure that we
can utilize the buses in the FPGA fabric to the maximum for each DMA core.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
---
 projects/fmcomms2/c5soc/system_bd.qsys | 544 +++++++++++++------------
 1 file changed, 291 insertions(+), 253 deletions(-)

diff --git a/projects/fmcomms2/c5soc/system_bd.qsys b/projects/fmcomms2/c5soc/system_bd.qsys
index 44b4c4419..c91a72150 100644
--- a/projects/fmcomms2/c5soc/system_bd.qsys
+++ b/projects/fmcomms2/c5soc/system_bd.qsys
@@ -7,222 +7,222 @@
    description=""
    tags=""
    categories="System" />
- <parameter name="bonusData"><![CDATA[bonusData 
-{
-   element $${FILENAME}
-   {
-   }
-   element adc_pack
-   {
-      datum _sortIndex
-      {
-         value = "8";
-         type = "int";
-      }
-   }
-   element vga_frame_reader.avalon_slave
-   {
-      datum baseAddress
-      {
-         value = "36864";
-         type = "String";
-      }
-   }
-   element axi_ad9361
-   {
-      datum _sortIndex
-      {
-         value = "5";
-         type = "int";
-      }
-   }
-   element axi_dmac_adc
-   {
-      datum _sortIndex
-      {
-         value = "9";
-         type = "int";
-      }
-   }
-   element axi_dmac_dac
-   {
-      datum _sortIndex
-      {
-         value = "6";
-         type = "int";
-      }
-   }
-   element sys_id.control_slave
-   {
-      datum _lockedAddress
-      {
-         value = "1";
-         type = "boolean";
-      }
-      datum baseAddress
-      {
-         value = "65536";
-         type = "String";
-      }
-   }
-   element sys_gpio.external_connection
-   {
-      datum _tags
-      {
-         value = "";
-         type = "String";
-      }
-   }
-   element sys_hps.f2h_sdram0_data
-   {
-      datum baseAddress
-      {
-         value = "0";
-         type = "String";
-      }
-   }
-   element sys_int_mem.s1
-   {
-      datum baseAddress
-      {
-         value = "0";
-         type = "String";
-      }
-   }
-   element sys_gpio.s1
-   {
-      datum _lockedAddress
-      {
-         value = "1";
-         type = "boolean";
-      }
-      datum baseAddress
-      {
-         value = "65664";
-         type = "String";
-      }
-   }
-   element axi_ad9361.s_axi
-   {
-      datum baseAddress
-      {
-         value = "131072";
-         type = "String";
-      }
-   }
-   element axi_dmac_dac.s_axi
-   {
-      datum baseAddress
-      {
-         value = "16384";
-         type = "String";
-      }
-   }
-   element axi_dmac_adc.s_axi
-   {
-      datum baseAddress
-      {
-         value = "0";
-         type = "String";
-      }
-   }
-   element spi_ad9361
-   {
-      datum _sortIndex
-      {
-         value = "10";
-         type = "int";
-      }
-   }
-   element spi_ad9361.spi_control_port
-   {
-      datum baseAddress
-      {
-         value = "32768";
-         type = "String";
-      }
-   }
-   element sys_clk
-   {
-      datum _sortIndex
-      {
-         value = "0";
-         type = "int";
-      }
-   }
-   element sys_gpio
-   {
-      datum _sortIndex
-      {
-         value = "4";
-         type = "int";
-      }
-   }
-   element sys_hps
-   {
-      datum _sortIndex
-      {
-         value = "1";
-         type = "int";
-      }
-   }
-   element sys_id
-   {
-      datum _sortIndex
-      {
-         value = "3";
-         type = "int";
-      }
-   }
-   element sys_int_mem
-   {
-      datum _sortIndex
-      {
-         value = "2";
-         type = "int";
-      }
-   }
-   element util_dac_unpack
-   {
-      datum _sortIndex
-      {
-         value = "7";
-         type = "int";
-      }
-   }
-   element vga_clock_video_output
-   {
-      datum _sortIndex
-      {
-         value = "14";
-         type = "int";
-      }
-   }
-   element vga_frame_reader
-   {
-      datum _sortIndex
-      {
-         value = "13";
-         type = "int";
-      }
-   }
-   element vga_pixel_clock_bridge
-   {
-      datum _sortIndex
-      {
-         value = "12";
-         type = "int";
-      }
-   }
-   element vga_pll
-   {
-      datum _sortIndex
-      {
-         value = "11";
-         type = "int";
-      }
-   }
-}
+ <parameter name="bonusData"><![CDATA[bonusData 
+{
+   element $${FILENAME}
+   {
+   }
+   element adc_pack
+   {
+      datum _sortIndex
+      {
+         value = "8";
+         type = "int";
+      }
+   }
+   element vga_frame_reader.avalon_slave
+   {
+      datum baseAddress
+      {
+         value = "36864";
+         type = "String";
+      }
+   }
+   element axi_ad9361
+   {
+      datum _sortIndex
+      {
+         value = "5";
+         type = "int";
+      }
+   }
+   element axi_dmac_adc
+   {
+      datum _sortIndex
+      {
+         value = "9";
+         type = "int";
+      }
+   }
+   element axi_dmac_dac
+   {
+      datum _sortIndex
+      {
+         value = "6";
+         type = "int";
+      }
+   }
+   element sys_id.control_slave
+   {
+      datum _lockedAddress
+      {
+         value = "1";
+         type = "boolean";
+      }
+      datum baseAddress
+      {
+         value = "65536";
+         type = "String";
+      }
+   }
+   element sys_gpio.external_connection
+   {
+      datum _tags
+      {
+         value = "";
+         type = "String";
+      }
+   }
+   element sys_hps.f2h_sdram0_data
+   {
+      datum baseAddress
+      {
+         value = "0";
+         type = "String";
+      }
+   }
+   element sys_int_mem.s1
+   {
+      datum baseAddress
+      {
+         value = "0";
+         type = "String";
+      }
+   }
+   element sys_gpio.s1
+   {
+      datum _lockedAddress
+      {
+         value = "1";
+         type = "boolean";
+      }
+      datum baseAddress
+      {
+         value = "65664";
+         type = "String";
+      }
+   }
+   element axi_ad9361.s_axi
+   {
+      datum baseAddress
+      {
+         value = "131072";
+         type = "String";
+      }
+   }
+   element axi_dmac_adc.s_axi
+   {
+      datum baseAddress
+      {
+         value = "0";
+         type = "String";
+      }
+   }
+   element axi_dmac_dac.s_axi
+   {
+      datum baseAddress
+      {
+         value = "16384";
+         type = "String";
+      }
+   }
+   element spi_ad9361
+   {
+      datum _sortIndex
+      {
+         value = "10";
+         type = "int";
+      }
+   }
+   element spi_ad9361.spi_control_port
+   {
+      datum baseAddress
+      {
+         value = "32768";
+         type = "String";
+      }
+   }
+   element sys_clk
+   {
+      datum _sortIndex
+      {
+         value = "0";
+         type = "int";
+      }
+   }
+   element sys_gpio
+   {
+      datum _sortIndex
+      {
+         value = "4";
+         type = "int";
+      }
+   }
+   element sys_hps
+   {
+      datum _sortIndex
+      {
+         value = "1";
+         type = "int";
+      }
+   }
+   element sys_id
+   {
+      datum _sortIndex
+      {
+         value = "3";
+         type = "int";
+      }
+   }
+   element sys_int_mem
+   {
+      datum _sortIndex
+      {
+         value = "2";
+         type = "int";
+      }
+   }
+   element util_dac_unpack
+   {
+      datum _sortIndex
+      {
+         value = "7";
+         type = "int";
+      }
+   }
+   element vga_clock_video_output
+   {
+      datum _sortIndex
+      {
+         value = "14";
+         type = "int";
+      }
+   }
+   element vga_frame_reader
+   {
+      datum _sortIndex
+      {
+         value = "13";
+         type = "int";
+      }
+   }
+   element vga_pixel_clock_bridge
+   {
+      datum _sortIndex
+      {
+         value = "12";
+         type = "int";
+      }
+   }
+   element vga_pll
+   {
+      datum _sortIndex
+      {
+         value = "11";
+         type = "int";
+      }
+   }
+}
 ]]></parameter>
  <parameter name="clockCrossingAdapter" value="FIFO" />
  <parameter name="device" value="5CSXFC6D6F31C8ES" />
@@ -762,8 +762,8 @@
   <parameter name="F2S_Width" value="2" />
   <parameter name="S2F_Width" value="2" />
   <parameter name="LWH2F_Enable" value="true" />
-  <parameter name="F2SDRAM_Type">Avalon-MM Bidirectional</parameter>
-  <parameter name="F2SDRAM_Width" value="64" />
+  <parameter name="F2SDRAM_Type">Avalon-MM Bidirectional,AXI-3,AXI-3</parameter>
+  <parameter name="F2SDRAM_Width" value="64,64,64" />
   <parameter name="BONDING_OUT_ENABLED" value="false" />
   <parameter name="S2FCLK_COLDRST_Enable" value="false" />
   <parameter name="S2FCLK_PENDINGRST_Enable" value="false" />
@@ -836,9 +836,9 @@
   <parameter name="F2H_AXI_CLOCK_FREQ" value="50000000" />
   <parameter name="H2F_AXI_CLOCK_FREQ" value="50000000" />
   <parameter name="H2F_LW_AXI_CLOCK_FREQ" value="50000000" />
-  <parameter name="F2H_SDRAM0_CLOCK_FREQ" value="80000000" />
-  <parameter name="F2H_SDRAM1_CLOCK_FREQ" value="100" />
-  <parameter name="F2H_SDRAM2_CLOCK_FREQ" value="100" />
+  <parameter name="F2H_SDRAM0_CLOCK_FREQ" value="50000000" />
+  <parameter name="F2H_SDRAM1_CLOCK_FREQ" value="80000000" />
+  <parameter name="F2H_SDRAM2_CLOCK_FREQ" value="80000000" />
   <parameter name="F2H_SDRAM3_CLOCK_FREQ" value="100" />
   <parameter name="F2H_SDRAM4_CLOCK_FREQ" value="100" />
   <parameter name="F2H_SDRAM5_CLOCK_FREQ" value="100" />
@@ -1369,11 +1369,6 @@
    version="14.0"
    start="sys_clk.clk"
    end="axi_ad9361.delay_clock" />
- <connection
-   kind="clock"
-   version="14.0"
-   start="sys_hps.h2f_user0_clock"
-   end="sys_hps.f2h_sdram0_clock" />
  <connection
    kind="clock"
    version="14.0"
@@ -1403,15 +1398,6 @@
    version="14.0"
    start="sys_clk.clk_reset"
    end="axi_dmac_dac.m_src_axi_reset" />
- <connection
-   kind="avalon"
-   version="14.0"
-   start="axi_dmac_dac.m_src_axi"
-   end="sys_hps.f2h_sdram0_data">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
  <connection
    kind="clock"
    version="14.0"
@@ -1441,15 +1427,6 @@
    version="14.0"
    start="sys_clk.clk_reset"
    end="axi_dmac_adc.m_dest_axi_reset" />
- <connection
-   kind="avalon"
-   version="14.0"
-   start="axi_dmac_adc.m_dest_axi"
-   end="sys_hps.f2h_sdram0_data">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
  <connection
    kind="interrupt"
    version="14.0"
@@ -1541,15 +1518,6 @@
    version="14.0"
    start="vga_frame_reader.avalon_streaming_source"
    end="vga_clock_video_output.din" />
- <connection
-   kind="avalon"
-   version="14.0"
-   start="vga_frame_reader.avalon_master"
-   end="sys_hps.f2h_axi_slave">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
  <connection
    kind="clock"
    version="14.0"
@@ -1562,6 +1530,76 @@
    end="vga_frame_reader.interrupt_sender">
   <parameter name="irqNumber" value="4" />
  </connection>
+ <connection
+   kind="clock"
+   version="14.0"
+   start="sys_clk.clk"
+   end="sys_hps.f2h_sdram0_clock" />
+ <connection
+   kind="avalon"
+   version="14.0"
+   start="vga_frame_reader.avalon_master"
+   end="sys_hps.f2h_sdram0_data">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="14.0"
+   start="axi_dmac_adc.m_dest_axi"
+   end="sys_hps.f2h_sdram1_data">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="14.0"
+   start="axi_dmac_dac.m_src_axi"
+   end="sys_hps.f2h_sdram2_data">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="clock"
+   version="14.0"
+   start="sys_hps.h2f_user0_clock"
+   end="sys_hps.f2h_sdram2_clock" />
+ <connection
+   kind="clock"
+   version="14.0"
+   start="sys_hps.h2f_user0_clock"
+   end="sys_hps.f2h_sdram1_clock" />
  <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />
  <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="2" />
+ <interconnectRequirement
+   for="mm_interconnect_4|axi_dmac_dac_m_src_axi_agent.write_cp/router.sink"
+   name="qsys_mm.postTransform.pipelineCount"
+   value="0" />
+ <interconnectRequirement
+   for="mm_interconnect_4|cmd_mux_001"
+   name="qsys_mm.postTransform.pipelineCount"
+   value="0" />
+ <interconnectRequirement
+   for="mm_interconnect_4|cmd_mux"
+   name="qsys_mm.postTransform.pipelineCount"
+   value="0" />
+ <interconnectRequirement
+   for="mm_interconnect_3|cmd_mux_001"
+   name="qsys_mm.postTransform.pipelineCount"
+   value="0" />
+ <interconnectRequirement
+   for="mm_interconnect_3|cmd_mux"
+   name="qsys_mm.postTransform.pipelineCount"
+   value="0" />
+ <interconnectRequirement
+   for="mm_interconnect_2|cmd_mux"
+   name="qsys_mm.postTransform.pipelineCount"
+   value="0" />
+ <interconnectRequirement
+   for="mm_interconnect_0|cmd_mux"
+   name="qsys_mm.postTransform.pipelineCount"
+   value="0" />
 </system>