From eca616a3aeeffd2013c1a7b420cc7b2107560671 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Thu, 23 Apr 2015 10:35:12 +0300
Subject: [PATCH] axi_ad9643: Added CDC and reset constraints

---
 library/axi_ad9643/axi_ad9643_constr.xdc | 45 ++++++++++++++++++++++--
 library/axi_ad9643/axi_ad9643_ip.tcl     |  1 +
 2 files changed, 44 insertions(+), 2 deletions(-)
 mode change 100755 => 100644 library/axi_ad9643/axi_ad9643_constr.xdc
 mode change 100755 => 100644 library/axi_ad9643/axi_ad9643_ip.tcl

diff --git a/library/axi_ad9643/axi_ad9643_constr.xdc b/library/axi_ad9643/axi_ad9643_constr.xdc
old mode 100755
new mode 100644
index 9870305c3..dbc6462af
--- a/library/axi_ad9643/axi_ad9643_constr.xdc
+++ b/library/axi_ad9643/axi_ad9643_constr.xdc
@@ -1,3 +1,44 @@
-set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports adc_clk]]
-set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports s_axi_aclk]]
+set up_clk [get_clocks -of_objects [get_ports s_axi_aclk]]
+set ad9643_clk [get_clocks -of_objects [get_ports adc_clk]]
 
+set_property ASYNC_REG TRUE \
+  [get_cells -hier *toggle_m1_reg*] \
+  [get_cells -hier *toggle_m2_reg*] \
+  [get_cells -hier *state_m1_reg*] \
+  [get_cells -hier *state_m2_reg*]
+
+set_false_path \
+  -from [get_cells -hier up_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
+  -to [get_cells -hier d_xfer_toggle_m1_reg* -filter {primitive_subgroup == flop}]
+set_false_path \
+  -from [get_cells -hier d_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
+  -to [get_cells -hier up_xfer_state_m1_reg* -filter {primitive_subgroup == flop}]
+set_max_delay -datapath_only \
+  -from [get_cells -hier up_xfer_data_reg* -filter {primitive_subgroup == flop}] \
+  -to [get_cells -hier d_data_cntrl_reg* -filter {primitive_subgroup == flop}] \
+  [get_property PERIOD $ad9643_clk]
+
+set_false_path \
+  -from [get_cells -hier d_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
+  -to [get_cells -hier up_xfer_toggle_m1_reg* -filter {primitive_subgroup == flop}]
+set_false_path \
+  -from [get_cells -hier up_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
+  -to [get_cells -hier d_xfer_state_m1_reg* -filter {primitive_subgroup == flop}]
+set_max_delay -datapath_only \
+  -from [get_cells -hier d_xfer_data_reg* -filter {primitive_subgroup == flop}] \
+  -to [get_cells -hier up_data_status_reg* -filter {primitive_subgroup == flop}] \
+  [get_property PERIOD $up_clk]
+
+set_false_path \
+  -from [get_cells -hier up_count_toggle_reg* -filter {primitive_subgroup == flop}] \
+  -to [get_cells -hier d_count_toggle_m1_reg* -filter {primitive_subgroup == flop}]
+set_false_path \
+  -from [get_cells -hier d_count_toggle_reg* -filter {primitive_subgroup == flop}] \
+  -to [get_cells -hier up_count_toggle_m1_reg* -filter {primitive_subgroup == flop}]
+set_max_delay -datapath_only \
+  -from [get_cells -hier d_count_hold_reg* -filter {primitive_subgroup == flop}] \
+  -to [get_cells -hier up_d_count_reg* -filter {primitive_subgroup == flop}] \
+  [get_property PERIOD $up_clk]
+
+set_false_path \
+  -to [get_pins -hier */PRE -filter {NAME =~ *i_*rst_reg*}]
diff --git a/library/axi_ad9643/axi_ad9643_ip.tcl b/library/axi_ad9643/axi_ad9643_ip.tcl
old mode 100755
new mode 100644
index 116ca230c..fd26dd1e5
--- a/library/axi_ad9643/axi_ad9643_ip.tcl
+++ b/library/axi_ad9643/axi_ad9643_ip.tcl
@@ -28,6 +28,7 @@ adi_ip_files axi_ad9643 [list \
   "axi_ad9643.v" ]
 
 adi_ip_properties axi_ad9643
+
 adi_ip_constraints axi_ad9643 [list \
   "axi_ad9643_constr.xdc" ]