From eb8e1142cd2ba1c369dd4073f54246a1ccbcef05 Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Tue, 16 Apr 2019 08:42:04 +0100 Subject: [PATCH] adrv9009/intel: Fix the register address layout The reconfiguration interface for the Stratix10 XCVR has a different address width. Prepare the register map layout of the project to support this new architecture. --- projects/adrv9009/common/adrv9009_qsys.tcl | 46 +++++++++++----------- 1 file changed, 23 insertions(+), 23 deletions(-) diff --git a/projects/adrv9009/common/adrv9009_qsys.tcl b/projects/adrv9009/common/adrv9009_qsys.tcl index b27465d77..3c47af3ea 100644 --- a/projects/adrv9009/common/adrv9009_qsys.tcl +++ b/projects/adrv9009/common/adrv9009_qsys.tcl @@ -290,32 +290,32 @@ for {set i 0} {$i < 4} {incr i} { ad_cpu_interconnect 0x00020000 adrv9009_tx_jesd204.link_reconfig ad_cpu_interconnect 0x00024000 adrv9009_tx_jesd204.link_management -ad_cpu_interconnect 0x00025000 adrv9009_tx_jesd204.link_pll_reconfig -ad_cpu_interconnect 0x00026000 adrv9009_tx_jesd204.lane_pll_reconfig -ad_cpu_interconnect 0x00028000 avl_adxcfg_0.rcfg_s0 -ad_cpu_interconnect 0x00029000 avl_adxcfg_1.rcfg_s0 -ad_cpu_interconnect 0x0002a000 avl_adxcfg_2.rcfg_s0 -ad_cpu_interconnect 0x0002b000 avl_adxcfg_3.rcfg_s0 -ad_cpu_interconnect 0x0002c000 axi_adrv9009_tx_dma.s_axi +ad_cpu_interconnect 0x00026000 adrv9009_tx_jesd204.link_pll_reconfig +ad_cpu_interconnect 0x00028000 adrv9009_tx_jesd204.lane_pll_reconfig +ad_cpu_interconnect 0x0002a000 avl_adxcfg_0.rcfg_s0 +ad_cpu_interconnect 0x0002c000 avl_adxcfg_1.rcfg_s0 +ad_cpu_interconnect 0x0002e000 avl_adxcfg_2.rcfg_s0 +ad_cpu_interconnect 0x00030000 avl_adxcfg_3.rcfg_s0 +ad_cpu_interconnect 0x00032000 axi_adrv9009_tx_dma.s_axi -ad_cpu_interconnect 0x00030000 adrv9009_rx_jesd204.link_reconfig -ad_cpu_interconnect 0x00034000 adrv9009_rx_jesd204.link_management -ad_cpu_interconnect 0x00035000 adrv9009_rx_jesd204.link_pll_reconfig -ad_cpu_interconnect 0x00038000 avl_adxcfg_0.rcfg_s1 -ad_cpu_interconnect 0x00039000 avl_adxcfg_1.rcfg_s1 -ad_cpu_interconnect 0x0003c000 axi_adrv9009_rx_dma.s_axi +ad_cpu_interconnect 0x00040000 adrv9009_rx_jesd204.link_reconfig +ad_cpu_interconnect 0x00044000 adrv9009_rx_jesd204.link_management +ad_cpu_interconnect 0x00046000 adrv9009_rx_jesd204.link_pll_reconfig +ad_cpu_interconnect 0x00048000 avl_adxcfg_0.rcfg_s1 +ad_cpu_interconnect 0x0004a000 avl_adxcfg_1.rcfg_s1 +ad_cpu_interconnect 0x0004c000 axi_adrv9009_rx_dma.s_axi -ad_cpu_interconnect 0x00040000 adrv9009_rx_os_jesd204.link_reconfig -ad_cpu_interconnect 0x00044000 adrv9009_rx_os_jesd204.link_management -ad_cpu_interconnect 0x00045000 adrv9009_rx_os_jesd204.link_pll_reconfig -ad_cpu_interconnect 0x00048000 avl_adxcfg_2.rcfg_s1 -ad_cpu_interconnect 0x00049000 avl_adxcfg_3.rcfg_s1 -ad_cpu_interconnect 0x0004c000 axi_adrv9009_rx_os_dma.s_axi +ad_cpu_interconnect 0x00050000 adrv9009_rx_os_jesd204.link_reconfig +ad_cpu_interconnect 0x00054000 adrv9009_rx_os_jesd204.link_management +ad_cpu_interconnect 0x00056000 adrv9009_rx_os_jesd204.link_pll_reconfig +ad_cpu_interconnect 0x00058000 avl_adxcfg_2.rcfg_s1 +ad_cpu_interconnect 0x0005a000 avl_adxcfg_3.rcfg_s1 +ad_cpu_interconnect 0x0005c000 axi_adrv9009_rx_os_dma.s_axi -ad_cpu_interconnect 0x00050000 axi_adrv9009_rx.s_axi -ad_cpu_interconnect 0x00054000 axi_adrv9009_tx.s_axi -ad_cpu_interconnect 0x00058000 axi_adrv9009_rx_os.s_axi -ad_cpu_interconnect 0x00060000 avl_adrv9009_gpio.s1 +ad_cpu_interconnect 0x00060000 axi_adrv9009_rx.s_axi +ad_cpu_interconnect 0x00064000 axi_adrv9009_tx.s_axi +ad_cpu_interconnect 0x00068000 axi_adrv9009_rx_os.s_axi +ad_cpu_interconnect 0x00070000 avl_adrv9009_gpio.s1 # dma interconnects