prcfg_qpsk: Major update
Add a symbol wrapper to the logic. Wraps the 32 bit data to 2 bit symbols.main
Istvan Csomortani
parent
e450e78f13
commit
eb520b1f75
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@ -59,46 +59,52 @@ module prcfg_adc (
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dst_adc_dovf
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);
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localparam RP_ID = 8'hA2;
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parameter CHANNEL_ID = 0;
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parameter CHANNEL_ID = 0;
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parameter DATA_WIDTH = 32;
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parameter SYMBOL_WIDTH = 2;
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input clk;
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localparam RP_ID = 8'hA2;
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localparam SYMBOLE_CNTR_WIDTH = $clog2(DATA_WIDTH/SYMBOLE_WIDTH);
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localparam NROF_SYMBOLS = DATA_WIDTH/SYMBOL_WIDTH;
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input [31:0] control;
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output [31:0] status;
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input clk;
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input src_adc_dwr;
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input src_adc_dsync;
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input [31:0] src_adc_ddata;
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output src_adc_dovf;
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input [31:0] control;
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output [31:0] status;
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output dst_adc_dwr;
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output dst_adc_dsync;
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output [31:0] dst_adc_ddata;
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input dst_adc_dovf;
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input src_adc_dwr;
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input src_adc_dsync;
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input [(DATA_WIDTH-1):0] src_adc_ddata;
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output src_adc_dovf;
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reg src_adc_dovf;
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reg dst_adc_dwr;
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reg dst_adc_dsync;
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output dst_adc_dwr;
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output dst_adc_dsync;
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output [(DATA_WIDTH-1):0] dst_adc_ddata;
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input dst_adc_dovf;
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reg [31:0] dst_adc_ddata = 0;
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reg [31:0] status = 0;
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reg [ 7:0] adc_pn_data = 0;
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reg adc_dvalid_d = 0;
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reg [ 1:0] adc_ddata = 0;
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reg [ 7:0] adc_pn_oos_count = 0;
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reg adc_pn_oos = 0;
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reg adc_pn_err = 0;
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reg src_adc_dovf = 'h0;
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reg dst_adc_dwr = 'h0;
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reg dst_adc_dsync = 'h0;
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reg [(DATA_WIDTH-1):0] dst_adc_ddata = 'h0;
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reg [ 3:0] mode;
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reg [ 3:0] channel_sel;
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reg [(DATA_WIDTH-1):0] adc_ddata = 'h0;
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reg [ 7:0] adc_pn_data = 'hF1;
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wire adc_dvalid;
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wire [ 1:0] adc_ddata_s;
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wire [31:0] adc_pn_data_s;
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wire adc_pn_update_s;
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wire adc_pn_match_s;
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wire adc_pn_err_s;
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reg [31:0] status = 'h0;
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reg [ 3:0] mode = 'h0;
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reg [ 3:0] channel_sel = 'h0;
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reg [(SYMBOL_WIDTH-1):0] adc_data_buf[(NROF_SYMBOLS-1):0];
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reg [(SYMBOL_CNTR_WIDTH-1):0] symbole_counter = 'h0;
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reg [2:0] sample_counter = 'd0;
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wire adc_dvalid;
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wire dma_dvalid;
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wire [(SYMBOL_WIDTH-1):0] adc_ddata_s;
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wire adc_pn_err_s;
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wire adc_pn_oos_s;
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wire demod_en;
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// prbs function
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function [ 7:0] pn;
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@ -117,6 +123,7 @@ module prcfg_adc (
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end
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endfunction
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// update control and status registers
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always @(posedge clk) begin
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channel_sel <= control[ 3:0];
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mode <= control[ 7:4];
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@ -124,35 +131,56 @@ module prcfg_adc (
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assign adc_dvalid = src_adc_dwr & src_adc_dsync;
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// prbs monitor
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assign adc_pn_data_s = (adc_pn_oos == 1'b1) ? {adc_pn_data[7:2], src_adc_ddata} : adc_pn_data;
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assign adc_pn_update_s = ~(adc_pn_oos ^ adc_pn_match_s);
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assign adc_pn_match_s = (adc_ddata == adc_pn_data[1:0]) ? 1'b1 : 1'b0;
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assign adc_pn_err_s = ~(adc_pn_oos | adc_pn_match_s);
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// data concatanation (MSB first)
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always @(posedge clk) begin
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if(adc_dvalid == 1'b1) begin
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adc_data_buf[(NROF_SYMBOLS - symbole_counter - 1)] <= adc_ddata_s;
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end
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end
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genvar i;
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generate
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for (i=0; i < NROF_SYMBOLS; i = i + 1) begin: SYMBOL_WRAPPER
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always @(posedge clk) begin
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if((adc_dvalid == 1'b1) &&
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(& symbole_counter == 1'b1) &&
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(sample_counter == 'b1) &&
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(mode != 0)) begin
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adc_ddata[((i+1)*SYMBOL_WIDTH)-1:(i*SYMBOL_WIDTH)] <= adc_data_buf[i];
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end
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end
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end
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endgenerate
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ad_pnmon #(
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.DATA_WIDTH(8)
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) i_pn_mon (
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.adc_clk(clk),
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.adc_valid_in(adc_dvalid),
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.adc_data_in({adc_pn_data[7:2], adc_ddata_s}),
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.adc_data_pn(adc_pn_data),
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.adc_pn_oos(adc_pn_oos_s),
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.adc_pn_err(adc_pn_err_s));
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// prbs generation
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always @(posedge clk) begin
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if(adc_dvalid == 1'b1) begin
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adc_pn_data <= pn(adc_pn_data);
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end
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end
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always @(posedge clk) begin
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if(adc_dvalid == 1'b1) begin
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adc_ddata <= src_adc_ddata;
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adc_pn_data <= pn(adc_pn_data_s);
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end
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adc_dvalid_d <= adc_dvalid;
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if(adc_dvalid_d == 1'b1) begin
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adc_pn_err <= adc_pn_err_s;
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if(adc_pn_update_s == 1'b1) begin
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if(adc_pn_oos_count >= 'd16) begin
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adc_pn_oos_count <= 'd0;
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adc_pn_oos <= ~adc_pn_oos;
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end else begin
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adc_pn_oos_count <= adc_pn_oos_count + 1;
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adc_pn_oos <= adc_pn_oos;
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end
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end else begin
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adc_pn_oos_count <= 'd0;
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adc_pn_oos <= adc_pn_oos;
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if(demod_en == 1'b1) begin
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symbole_counter <= symbole_counter + 1;
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end
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sample_counter <= sample_counter + 1;
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end
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end
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assign demod_en = (sample_counter == 7) ? 1'b1 : 1'b0;
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// qpsk demodulator
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qpsk_demod i_qpsk_demod1 (
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.clk(clk),
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@ -166,19 +194,21 @@ module prcfg_adc (
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always @(posedge clk) begin
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src_adc_dovf <= dst_adc_dovf;
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dst_adc_dwr <= src_adc_dwr;
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dst_adc_dsync <= src_adc_dsync;
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if(mode == 0) begin
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dst_adc_dwr <= src_adc_dwr;
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dst_adc_ddata <= src_adc_ddata;
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end else begin
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dst_adc_ddata <= {30'h0, adc_ddata};
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dst_adc_ddata <= adc_ddata;
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dst_adc_dwr <= (& symbole_counter) & (& sample_counter);
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end
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if((mode == 3'd2) && (channel_sel == CHANNEL_ID)) begin
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status <= {22'h0, adc_pn_err, adc_pn_oos, RP_ID};
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status <= {22'h0, adc_pn_err_s, adc_pn_oos_s, RP_ID};
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end else begin
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status <= {24'h0, RP_ID};
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end
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end
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endmodule
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@ -60,40 +60,53 @@ module prcfg_dac(
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dst_dac_dvalid
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);
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localparam RP_ID = 8'hA2;
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parameter CHANNEL_ID = 0;
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parameter CHANNEL_ID = 0;
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parameter DATA_WIDTH = 32;
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parameter SYMBOL_WIDTH = 2;
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input clk;
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localparam RP_ID = 8'hA2;
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localparam SYMBOL_CNTR_WIDTH = $clog2(DATA_WIDTH/SYMBOL_WIDTH);
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localparam NROF_SYMBOLES = DATA_WIDTH/SYMBOL_WIDTH;
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input [31:0] control;
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output [31:0] status;
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input clk;
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output src_dac_en;
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input [31:0] src_dac_ddata;
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input src_dac_dunf;
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input src_dac_dvalid;
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input [31:0] control;
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output [31:0] status;
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input dst_dac_en;
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output [31:0] dst_dac_ddata;
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output dst_dac_dunf;
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output dst_dac_dvalid;
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output src_dac_en;
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input [(DATA_WIDTH-1):0] src_dac_ddata;
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input src_dac_dunf;
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input src_dac_dvalid;
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reg dst_dac_dunf = 0;
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reg [31:0] dst_dac_ddata = 0;
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reg dst_dac_dvalid = 0;
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reg src_dac_en = 0;
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input dst_dac_en;
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output [(DATA_WIDTH-1):0] dst_dac_ddata;
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output dst_dac_dunf;
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output dst_dac_dvalid;
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reg [ 7:0] pn_data = 8'hF2;
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reg [31:0] status = 0;
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// output register to improve timing
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reg dst_dac_dunf = 'h0;
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reg [(DATA_WIDTH-1):0] dst_dac_ddata = 'h0;
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reg dst_dac_dvalid = 'h0;
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reg src_dac_en = 'h0;
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reg [ 3:0] mode;
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// internal registers
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reg [ 7:0] pn_data = 'hF2;
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reg [31:0] status = 'h0;
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reg [ 3:0] mode = 'h0;
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wire [ 1:0] dac_data;
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wire [15:0] dac_data_fltr_i;
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wire [15:0] dac_data_fltr_q;
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reg [(SYMBOL_WIDTH-1):0] dac_data_buf[(NROF_SYMBOLES-1):0];
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reg [(SYMBOL_CNTR_WIDTH-1):0] symbole_counter = 'd0;
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reg [2:0] sample_counter = 'd0;
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wire [31:0] dac_data_mode0;
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wire [31:0] dac_data_mode1_2;
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// internal wires
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wire [(SYMBOL_WIDTH-1):0] mod_data;
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wire [15:0] dac_data_fltr_i;
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wire [15:0] dac_data_fltr_q;
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wire [(DATA_WIDTH-1):0] dac_data_mode0;
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wire [(DATA_WIDTH-1):0] dac_data_mode1_2;
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wire mod_en;
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// prbs function
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function [ 7:0] pn;
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@ -112,43 +125,69 @@ module prcfg_dac(
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end
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endfunction
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// update control and status registers
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always @(posedge clk) begin
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status <= { 24'h0, RP_ID };
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mode <= control[ 7:4];
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end
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// pass through mode
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assign dac_data_mode0 = src_dac_ddata;
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// prbs geenration
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// prbs generation
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always @(posedge clk) begin
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if(dst_dac_en == 1) begin
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pn_data = pn(pn_data);
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pn_data <= pn(pn_data);
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end
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end
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// data source for the modulator
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assign dac_data = (mode == 1) ? pn_data[ 1:0] : src_dac_ddata[ 1:0];
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// symbol wrapper, data is transmitted MSB first
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genvar i;
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generate
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for (i = 0; i < NROF_SYMBOLES; i = i + 1) begin : SYMBOLE_WRAPPER
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// flop the incoming data when it's valid and all the symbols are pushed out
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always @(posedge clk) begin
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if((src_dac_dvalid == 1'b1) && (symbole_counter == 'd0)) begin
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dac_data_buf[(NROF_SYMBOLES-i-1)] <= src_dac_ddata[((i+1)*SYMBOL_WIDTH)-1:(i*SYMBOL_WIDTH)];
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end
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end
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end
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endgenerate
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// modulated data
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assign dac_data_mode1_2 = { dac_data_fltr_q, dac_data_fltr_i };
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// increment to counter for the symbol mux
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always @(posedge clk) begin
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if((src_dac_dvalid == 1'b1) && (dst_dac_en == 1'b1)) begin
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if(mod_en == 1'b1) begin
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symbole_counter <= symbole_counter + 1;
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end
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sample_counter <= sample_counter + 1;
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end
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end
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// the modulator generate eight samples from each symbol
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// to prevent data loss, need to keep each symbol at data_input port for 8 samples
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assign mod_en = (sample_counter == 7) ? 1'b1 : 1'b0;
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// data for the modulator (prbs or dma)
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assign mod_data = (mode == 1) ? pn_data[ 1:0] : dac_data_buf[symbole_counter];
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// qpsk modulator
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qpsk_mod i_qpsk_mod (
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.clk(clk),
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.data_input(dac_data),
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.data_input(mod_data),
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.data_valid(dst_dac_en),
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.data_qpsk_i(dac_data_fltr_i),
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.data_qpsk_q(dac_data_fltr_q)
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);
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// output logic for tx side
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// pass through mode
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assign dac_data_mode0 = src_dac_ddata;
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// modulated data
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assign dac_data_mode1_2 = { dac_data_fltr_q, dac_data_fltr_i };
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// output logic
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always @(posedge clk) begin
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src_dac_en <= (mode == 1) ? 1'b0 : dst_dac_en;
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src_dac_en <= (& symbole_counter) & (& sample_counter);
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dst_dac_dunf <= (mode == 1) ? 1'b0 : src_dac_dunf;
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dst_dac_ddata <= (mode == 0) ? dac_data_mode0 : dac_data_mode1_2;
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dst_dac_dvalid <= (mode == 0) ? src_dac_dvalid :
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((dst_dac_en == 1'b1) ? 1'b1 : 1'b0);
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dst_dac_dvalid <= (mode == 0) ? src_dac_dvalid : ((dst_dac_en == 1'b1) ? 1'b1 : 1'b0);
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end
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endmodule
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