From eb113c8698995444a84db2def033b70f772db621 Mon Sep 17 00:00:00 2001 From: AndreiGrozav Date: Mon, 24 Jul 2017 18:45:48 +0300 Subject: [PATCH] fmcomms2_kcu105: Initial commit --- projects/fmcomms2/kcu105/Makefile | 82 ++++++++ projects/fmcomms2/kcu105/system_bd.tcl | 10 + projects/fmcomms2/kcu105/system_constr.xdc | 66 ++++++ projects/fmcomms2/kcu105/system_project.tcl | 16 ++ projects/fmcomms2/kcu105/system_top.v | 213 ++++++++++++++++++++ 5 files changed, 387 insertions(+) create mode 100644 projects/fmcomms2/kcu105/Makefile create mode 100644 projects/fmcomms2/kcu105/system_bd.tcl create mode 100644 projects/fmcomms2/kcu105/system_constr.xdc create mode 100644 projects/fmcomms2/kcu105/system_project.tcl create mode 100644 projects/fmcomms2/kcu105/system_top.v diff --git a/projects/fmcomms2/kcu105/Makefile b/projects/fmcomms2/kcu105/Makefile new file mode 100644 index 000000000..eebaa3fc2 --- /dev/null +++ b/projects/fmcomms2/kcu105/Makefile @@ -0,0 +1,82 @@ +#################################################################################### +#################################################################################### +## Copyright 2011(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### +#################################################################################### + +M_DEPS += system_top.v +M_DEPS += system_project.tcl +M_DEPS += system_constr.xdc +M_DEPS += system_bd.tcl +M_DEPS += ../common/fmcomms2_bd.tcl +M_DEPS += ../../scripts/adi_project.tcl +M_DEPS += ../../scripts/adi_env.tcl +M_DEPS += ../../scripts/adi_board.tcl +M_DEPS += ../../common/kcu105/kcu105_system_constr.xdc +M_DEPS += ../../common/kcu105/kcu105_system_bd.tcl +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v +M_DEPS += ../../../library/axi_ad9361/axi_ad9361_delay.tcl +M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr +M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr +M_DEPS += ../../../library/util_clkdiv/util_clkdiv.xpr +M_DEPS += ../../../library/util_cpack/util_cpack.xpr +M_DEPS += ../../../library/util_rfifo/util_rfifo.xpr +M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr +M_DEPS += ../../../library/util_upack/util_upack.xpr +M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr + +M_VIVADO := vivado -mode batch -source + +M_FLIST := *.cache +M_FLIST += *.data +M_FLIST += *.xpr +M_FLIST += *.log +M_FLIST += *.jou +M_FLIST += xgui +M_FLIST += *.runs +M_FLIST += *.srcs +M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim +M_FLIST += .Xil +M_FLIST += *.ip_user_files + + + +.PHONY: all lib clean clean-all +all: lib fmcomms2_kcu105.sdk/system_top.hdf + + +clean: + rm -rf $(M_FLIST) + + +clean-all:clean + make -C ../../../library/axi_ad9361 clean + make -C ../../../library/axi_dmac clean + make -C ../../../library/util_clkdiv clean + make -C ../../../library/util_cpack clean + make -C ../../../library/util_rfifo clean + make -C ../../../library/util_tdd_sync clean + make -C ../../../library/util_upack clean + make -C ../../../library/util_wfifo clean + + +fmcomms2_kcu105.sdk/system_top.hdf: $(M_DEPS) + -rm -rf $(M_FLIST) + $(M_VIVADO) system_project.tcl >> fmcomms2_kcu105_vivado.log 2>&1 + + +lib: + make -C ../../../library/axi_ad9361 + make -C ../../../library/axi_dmac + make -C ../../../library/util_clkdiv + make -C ../../../library/util_cpack + make -C ../../../library/util_rfifo + make -C ../../../library/util_tdd_sync + make -C ../../../library/util_upack + make -C ../../../library/util_wfifo + +#################################################################################### +#################################################################################### diff --git a/projects/fmcomms2/kcu105/system_bd.tcl b/projects/fmcomms2/kcu105/system_bd.tcl new file mode 100644 index 000000000..60709d667 --- /dev/null +++ b/projects/fmcomms2/kcu105/system_bd.tcl @@ -0,0 +1,10 @@ + +source $ad_hdl_dir/projects/common/kcu105/kcu105_system_bd.tcl +source $ad_hdl_dir/projects/common/kcu105/kcu105_system_mig.tcl +source ../common/fmcomms2_bd.tcl + +ad_ip_parameter clkdiv CONFIG.SIM_DEVICE ULTRASCALE + +ad_ip_parameter axi_ad9361 CONFIG.DEVICE_TYPE 3 +ad_ip_parameter axi_ad9361 CONFIG.ADC_INIT_DELAY 11 + diff --git a/projects/fmcomms2/kcu105/system_constr.xdc b/projects/fmcomms2/kcu105/system_constr.xdc new file mode 100644 index 000000000..4f92d1823 --- /dev/null +++ b/projects/fmcomms2/kcu105/system_constr.xdc @@ -0,0 +1,66 @@ + +# constraints +# ad9361 + +set_property -dict {PACKAGE_PIN W23 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_clk_in_p] ; ## G6 FMC_LPC_LA00_CC_P +set_property -dict {PACKAGE_PIN W24 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_clk_in_n] ; ## G7 FMC_LPC_LA00_CC_N +set_property -dict {PACKAGE_PIN W25 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_frame_in_p] ; ## D8 FMC_LPC_LA01_CC_P +set_property -dict {PACKAGE_PIN Y25 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_frame_in_n] ; ## D9 FMC_LPC_LA01_CC_N +set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[0]] ; ## H7 FMC_LPC_LA02_P +set_property -dict {PACKAGE_PIN AB22 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[0]] ; ## H8 FMC_LPC_LA02_N +set_property -dict {PACKAGE_PIN W28 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[1]] ; ## G9 FMC_LPC_LA03_P +set_property -dict {PACKAGE_PIN Y28 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[1]] ; ## G10 FMC_LPC_LA03_N +set_property -dict {PACKAGE_PIN U26 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[2]] ; ## H10 FMC_LPC_LA04_P +set_property -dict {PACKAGE_PIN U27 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[2]] ; ## H11 FMC_LPC_LA04_N +set_property -dict {PACKAGE_PIN V27 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[3]] ; ## D11 FMC_LPC_LA05_P +set_property -dict {PACKAGE_PIN V28 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[3]] ; ## D12 FMC_LPC_LA05_N +set_property -dict {PACKAGE_PIN V29 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[4]] ; ## C10 FMC_LPC_LA06_P +set_property -dict {PACKAGE_PIN W29 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[4]] ; ## C11 FMC_LPC_LA06_N +set_property -dict {PACKAGE_PIN V22 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[5]] ; ## H13 FMC_LPC_LA07_P +set_property -dict {PACKAGE_PIN V23 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[5]] ; ## H14 FMC_LPC_LA07_N +set_property -dict {PACKAGE_PIN U24 IOSTANDARD LVDS} [get_ports tx_clk_out_p] ; ## G12 FMC_LPC_LA08_P +set_property -dict {PACKAGE_PIN U25 IOSTANDARD LVDS} [get_ports tx_clk_out_n] ; ## G13 FMC_LPC_LA08_N +set_property -dict {PACKAGE_PIN V26 IOSTANDARD LVDS} [get_ports tx_frame_out_p] ; ## D14 FMC_LPC_LA09_P +set_property -dict {PACKAGE_PIN W26 IOSTANDARD LVDS} [get_ports tx_frame_out_n] ; ## D15 FMC_LPC_LA09_N +set_property -dict {PACKAGE_PIN V21 IOSTANDARD LVDS} [get_ports tx_data_out_p[0]] ; ## H16 FMC_LPC_LA11_P +set_property -dict {PACKAGE_PIN W21 IOSTANDARD LVDS} [get_ports tx_data_out_n[0]] ; ## H17 FMC_LPC_LA11_N +set_property -dict {PACKAGE_PIN AC22 IOSTANDARD LVDS} [get_ports tx_data_out_p[1]] ; ## G15 FMC_LPC_LA12_P +set_property -dict {PACKAGE_PIN AC23 IOSTANDARD LVDS} [get_ports tx_data_out_n[1]] ; ## G16 FMC_LPC_LA12_N +set_property -dict {PACKAGE_PIN AA20 IOSTANDARD LVDS} [get_ports tx_data_out_p[2]] ; ## D17 FMC_LPC_LA13_P +set_property -dict {PACKAGE_PIN AB20 IOSTANDARD LVDS} [get_ports tx_data_out_n[2]] ; ## D18 FMC_LPC_LA13_N +set_property -dict {PACKAGE_PIN T22 IOSTANDARD LVDS} [get_ports tx_data_out_p[3]] ; ## C14 FMC_LPC_LA10_P +set_property -dict {PACKAGE_PIN T23 IOSTANDARD LVDS} [get_ports tx_data_out_n[3]] ; ## C15 FMC_LPC_LA10_N +set_property -dict {PACKAGE_PIN U21 IOSTANDARD LVDS} [get_ports tx_data_out_p[4]] ; ## C18 FMC_LPC_LA14_P +set_property -dict {PACKAGE_PIN U22 IOSTANDARD LVDS} [get_ports tx_data_out_n[4]] ; ## C19 FMC_LPC_LA14_N +set_property -dict {PACKAGE_PIN AB25 IOSTANDARD LVDS} [get_ports tx_data_out_p[5]] ; ## H19 FMC_LPC_LA15_P +set_property -dict {PACKAGE_PIN AB26 IOSTANDARD LVDS} [get_ports tx_data_out_n[5]] ; ## H20 FMC_LPC_LA15_N + + +set_property -dict {PACKAGE_PIN AA34 IOSTANDARD LVCMOS18} [get_ports gpio_status[0]] ; ## G21 FMC_LPC_LA20_P +set_property -dict {PACKAGE_PIN AB34 IOSTANDARD LVCMOS18} [get_ports gpio_status[1]] ; ## G22 FMC_LPC_LA20_N +set_property -dict {PACKAGE_PIN AC33 IOSTANDARD LVCMOS18} [get_ports gpio_status[2]] ; ## H25 FMC_LPC_LA21_P +set_property -dict {PACKAGE_PIN AD33 IOSTANDARD LVCMOS18} [get_ports gpio_status[3]] ; ## H26 FMC_LPC_LA21_N +set_property -dict {PACKAGE_PIN AC34 IOSTANDARD LVCMOS18} [get_ports gpio_status[4]] ; ## G24 FMC_LPC_LA22_P +set_property -dict {PACKAGE_PIN AD34 IOSTANDARD LVCMOS18} [get_ports gpio_status[5]] ; ## G25 FMC_LPC_LA22_N +set_property -dict {PACKAGE_PIN AD30 IOSTANDARD LVCMOS18} [get_ports gpio_status[6]] ; ## D23 FMC_LPC_LA23_P +set_property -dict {PACKAGE_PIN AD31 IOSTANDARD LVCMOS18} [get_ports gpio_status[7]] ; ## D24 FMC_LPC_LA23_N +set_property -dict {PACKAGE_PIN AE32 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[0]] ; ## H28 FMC_LPC_LA24_P +set_property -dict {PACKAGE_PIN AF32 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[1]] ; ## H29 FMC_LPC_LA24_N +set_property -dict {PACKAGE_PIN AE33 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[2]] ; ## G27 FMC_LPC_LA25_P +set_property -dict {PACKAGE_PIN AF34 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[3]] ; ## G28 FMC_LPC_LA25_N +set_property -dict {PACKAGE_PIN AA29 IOSTANDARD LVCMOS18} [get_ports gpio_en_agc] ; ## H22 FMC_LPC_LA19_P +set_property -dict {PACKAGE_PIN AB29 IOSTANDARD LVCMOS18} [get_ports gpio_sync] ; ## H23 FMC_LPC_LA19_N +set_property -dict {PACKAGE_PIN V31 IOSTANDARD LVCMOS18} [get_ports gpio_resetb] ; ## H31 FMC_LPC_LA28_P + +set_property -dict {PACKAGE_PIN AB21 IOSTANDARD LVCMOS18} [get_ports enable] ; ## G18 FMC_LPC_LA16_P +set_property -dict {PACKAGE_PIN AC21 IOSTANDARD LVCMOS18} [get_ports txnrx] ; ## G19 FMC_LPC_LA16_N + +set_property -dict {PACKAGE_PIN AF33 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports spi_csn_0] ; ## D26 FMC_LPC_LA26_P +set_property -dict {PACKAGE_PIN AG34 IOSTANDARD LVCMOS18} [get_ports spi_clk] ; ## D27 FMC_LPC_LA26_N +set_property -dict {PACKAGE_PIN AG31 IOSTANDARD LVCMOS18} [get_ports spi_mosi] ; ## C26 FMC_LPC_LA27_P +set_property -dict {PACKAGE_PIN AG32 IOSTANDARD LVCMOS18} [get_ports spi_miso] ; ## C27 FMC_LPC_LA27_N + +# clocks + +create_clock -name rx_clk -period 4.00 [get_ports rx_clk_in_p] +#set_property CFGBVS 1.8V fmcomms2_kcu105 diff --git a/projects/fmcomms2/kcu105/system_project.tcl b/projects/fmcomms2/kcu105/system_project.tcl new file mode 100644 index 000000000..5801d73d2 --- /dev/null +++ b/projects/fmcomms2/kcu105/system_project.tcl @@ -0,0 +1,16 @@ + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +adi_project_xilinx fmcomms2_kcu105 +adi_project_files fmcomms2_kcu105 [list \ + "system_top.v" \ + "system_constr.xdc"\ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ + "$ad_hdl_dir/projects/common/kcu105/kcu105_system_constr.xdc" \ + "$ad_hdl_dir/projects/common/kcu105/kcu105_system_lutram_constr.xdc" ] + +adi_project_run fmcomms2_kcu105 +source $ad_hdl_dir/library/axi_ad9361/axi_ad9361_delay.tcl + diff --git a/projects/fmcomms2/kcu105/system_top.v b/projects/fmcomms2/kcu105/system_top.v new file mode 100644 index 000000000..9e4e57e7f --- /dev/null +++ b/projects/fmcomms2/kcu105/system_top.v @@ -0,0 +1,213 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsabilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + input sys_rst, + input sys_clk_p, + input sys_clk_n, + + input uart_sin, + output uart_sout, + + output ddr4_act_n, + output [16:0] ddr4_addr, + output [ 1:0] ddr4_ba, + output [ 0:0] ddr4_bg, + output ddr4_ck_p, + output ddr4_ck_n, + output [ 0:0] ddr4_cke, + output [ 0:0] ddr4_cs_n, + inout [ 7:0] ddr4_dm_n, + inout [63:0] ddr4_dq, + inout [ 7:0] ddr4_dqs_p, + inout [ 7:0] ddr4_dqs_n, + output [ 0:0] ddr4_odt, + output ddr4_reset_n, + + output mdio_mdc, + inout mdio_mdio, + input phy_clk_p, + input phy_clk_n, + output phy_rst_n, + input phy_rx_p, + input phy_rx_n, + output phy_tx_p, + output phy_tx_n, + + output fan_pwm, + inout [16:0] gpio_bd, + + inout iic_scl, + inout iic_sda, + + input rx_clk_in_p, + input rx_clk_in_n, + input rx_frame_in_p, + input rx_frame_in_n, + input [ 5:0] rx_data_in_p, + input [ 5:0] rx_data_in_n, + output tx_clk_out_p, + output tx_clk_out_n, + output tx_frame_out_p, + output tx_frame_out_n, + output [ 5:0] tx_data_out_p, + output [ 5:0] tx_data_out_n, + + output enable, + output txnrx, + + output gpio_resetb, + output gpio_sync, + output gpio_en_agc, + output [ 3:0] gpio_ctl, + input [ 7:0] gpio_status, + + output spi_csn_0, + output spi_clk, + output spi_mosi, + input spi_miso); + + // internal signals + + wire [63:0] gpio_i; + wire [63:0] gpio_o; + wire [63:0] gpio_t; + wire [ 7:0] spi_csn; + // wire spi_clk; redeclaration + wire spi_mosi; + wire spi_miso; + + // defaults + + assign fan_pwm = 1'b1; + assign spi_csn_0 = spi_csn[0]; + + // instantiations + + ad_iobuf #(.DATA_WIDTH(15)) i_iobuf ( + .dio_t (gpio_t[46:32]), + .dio_i (gpio_o[46:32]), + .dio_o (gpio_i[46:32]), + .dio_p ({ gpio_resetb, + gpio_sync, + gpio_en_agc, + gpio_ctl, + gpio_status})); + + ad_iobuf #(.DATA_WIDTH(17)) i_iobuf_bd ( + .dio_t (gpio_t[16:0]), + .dio_i (gpio_o[16:0]), + .dio_o (gpio_i[16:0]), + .dio_p (gpio_bd)); + + system_wrapper i_system_wrapper ( + .c0_ddr4_act_n (ddr4_act_n), + .c0_ddr4_adr (ddr4_addr), + .c0_ddr4_ba (ddr4_ba), + .c0_ddr4_bg (ddr4_bg), + .c0_ddr4_ck_c (ddr4_ck_n), + .c0_ddr4_ck_t (ddr4_ck_p), + .c0_ddr4_cke (ddr4_cke), + .c0_ddr4_cs_n (ddr4_cs_n), + .c0_ddr4_dm_n (ddr4_dm_n), + .c0_ddr4_dq (ddr4_dq), + .c0_ddr4_dqs_c (ddr4_dqs_n), + .c0_ddr4_dqs_t (ddr4_dqs_p), + .c0_ddr4_odt (ddr4_odt), + .c0_ddr4_reset_n (ddr4_reset_n), + .gpio0_i (gpio_i[31:0]), + .gpio0_o (gpio_o[31:0]), + .gpio0_t (gpio_t[31:0]), + .gpio1_i (gpio_i[63:32]), + .gpio1_o (gpio_o[63:32]), + .gpio1_t (gpio_t[63:32]), + .iic_main_scl_io (iic_scl), + .iic_main_sda_io (iic_sda), + .mb_intr_05 (1'b0), + .mb_intr_06 (1'b0), + .mb_intr_07 (1'b0), + .mb_intr_08 (1'b0), + .mdio_mdc (mdio_mdc), + .mdio_mdio_io (mdio_mdio), + .phy_clk_clk_n (phy_clk_n), + .phy_clk_clk_p (phy_clk_p), + .phy_rst_n (phy_rst_n), + .phy_sd (1'b1), + .sgmii_rxn (phy_rx_n), + .sgmii_rxp (phy_rx_p), + .sgmii_txn (phy_tx_n), + .sgmii_txp (phy_tx_p), + + .spi_clk_i (spi_clk), + .spi_clk_o (spi_clk), + .spi_csn_i (spi_csn), + .spi_csn_o (spi_csn), + .spi_sdi_i (spi_miso), + .spi_sdo_i (spi_mosi), + .spi_sdo_o (spi_mosi), + .sys_clk_clk_n (sys_clk_n), + .sys_clk_clk_p (sys_clk_p), + .sys_rst (sys_rst), + + .rx_clk_in_n (rx_clk_in_n), + .rx_clk_in_p (rx_clk_in_p), + .rx_data_in_n (rx_data_in_n), + .rx_data_in_p (rx_data_in_p), + .rx_frame_in_n (rx_frame_in_n), + .rx_frame_in_p (rx_frame_in_p), + + .tdd_sync_i (1'b0), + .tdd_sync_o (), + .tdd_sync_t (), + + .tx_clk_out_n (tx_clk_out_n), + .tx_clk_out_p (tx_clk_out_p), + .tx_data_out_n (tx_data_out_n), + .tx_data_out_p (tx_data_out_p), + .tx_frame_out_n (tx_frame_out_n), + .tx_frame_out_p (tx_frame_out_p), + .txnrx (txnrx), + .up_enable (gpio_o[47]), + .up_txnrx (gpio_o[48]), + .uart_sin (uart_sin), + .uart_sout (uart_sout)); + +endmodule + +// *************************************************************************** +// ***************************************************************************