fmcomms2_kcu105: Initial commit
AndreiGrozav
parent
374c49ff48
commit
eb113c8698
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@ -0,0 +1,82 @@
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####################################################################################
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####################################################################################
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## Copyright 2011(c) Analog Devices, Inc.
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## Auto-generated, do not modify!
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####################################################################################
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####################################################################################
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M_DEPS += system_top.v
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M_DEPS += system_project.tcl
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M_DEPS += system_constr.xdc
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M_DEPS += system_bd.tcl
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M_DEPS += ../common/fmcomms2_bd.tcl
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M_DEPS += ../../scripts/adi_project.tcl
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M_DEPS += ../../scripts/adi_env.tcl
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M_DEPS += ../../scripts/adi_board.tcl
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M_DEPS += ../../common/kcu105/kcu105_system_constr.xdc
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M_DEPS += ../../common/kcu105/kcu105_system_bd.tcl
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M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
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M_DEPS += ../../../library/axi_ad9361/axi_ad9361_delay.tcl
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M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
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M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
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M_DEPS += ../../../library/util_clkdiv/util_clkdiv.xpr
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M_DEPS += ../../../library/util_cpack/util_cpack.xpr
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M_DEPS += ../../../library/util_rfifo/util_rfifo.xpr
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M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr
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M_DEPS += ../../../library/util_upack/util_upack.xpr
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M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
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M_VIVADO := vivado -mode batch -source
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M_FLIST := *.cache
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M_FLIST += *.data
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M_FLIST += *.xpr
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M_FLIST += *.log
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M_FLIST += *.jou
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M_FLIST += xgui
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M_FLIST += *.runs
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M_FLIST += *.srcs
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M_FLIST += *.sdk
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M_FLIST += *.hw
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M_FLIST += *.sim
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M_FLIST += .Xil
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M_FLIST += *.ip_user_files
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.PHONY: all lib clean clean-all
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all: lib fmcomms2_kcu105.sdk/system_top.hdf
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clean:
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rm -rf $(M_FLIST)
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clean-all:clean
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make -C ../../../library/axi_ad9361 clean
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make -C ../../../library/axi_dmac clean
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make -C ../../../library/util_clkdiv clean
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make -C ../../../library/util_cpack clean
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make -C ../../../library/util_rfifo clean
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make -C ../../../library/util_tdd_sync clean
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make -C ../../../library/util_upack clean
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make -C ../../../library/util_wfifo clean
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fmcomms2_kcu105.sdk/system_top.hdf: $(M_DEPS)
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-rm -rf $(M_FLIST)
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$(M_VIVADO) system_project.tcl >> fmcomms2_kcu105_vivado.log 2>&1
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lib:
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make -C ../../../library/axi_ad9361
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make -C ../../../library/axi_dmac
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make -C ../../../library/util_clkdiv
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make -C ../../../library/util_cpack
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make -C ../../../library/util_rfifo
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make -C ../../../library/util_tdd_sync
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make -C ../../../library/util_upack
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make -C ../../../library/util_wfifo
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####################################################################################
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####################################################################################
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@ -0,0 +1,10 @@
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source $ad_hdl_dir/projects/common/kcu105/kcu105_system_bd.tcl
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source $ad_hdl_dir/projects/common/kcu105/kcu105_system_mig.tcl
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source ../common/fmcomms2_bd.tcl
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ad_ip_parameter clkdiv CONFIG.SIM_DEVICE ULTRASCALE
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ad_ip_parameter axi_ad9361 CONFIG.DEVICE_TYPE 3
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ad_ip_parameter axi_ad9361 CONFIG.ADC_INIT_DELAY 11
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# constraints
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# ad9361
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set_property -dict {PACKAGE_PIN W23 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_clk_in_p] ; ## G6 FMC_LPC_LA00_CC_P
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set_property -dict {PACKAGE_PIN W24 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_clk_in_n] ; ## G7 FMC_LPC_LA00_CC_N
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set_property -dict {PACKAGE_PIN W25 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_frame_in_p] ; ## D8 FMC_LPC_LA01_CC_P
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set_property -dict {PACKAGE_PIN Y25 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_frame_in_n] ; ## D9 FMC_LPC_LA01_CC_N
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set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[0]] ; ## H7 FMC_LPC_LA02_P
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set_property -dict {PACKAGE_PIN AB22 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[0]] ; ## H8 FMC_LPC_LA02_N
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set_property -dict {PACKAGE_PIN W28 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[1]] ; ## G9 FMC_LPC_LA03_P
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set_property -dict {PACKAGE_PIN Y28 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[1]] ; ## G10 FMC_LPC_LA03_N
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set_property -dict {PACKAGE_PIN U26 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[2]] ; ## H10 FMC_LPC_LA04_P
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set_property -dict {PACKAGE_PIN U27 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[2]] ; ## H11 FMC_LPC_LA04_N
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set_property -dict {PACKAGE_PIN V27 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[3]] ; ## D11 FMC_LPC_LA05_P
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set_property -dict {PACKAGE_PIN V28 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[3]] ; ## D12 FMC_LPC_LA05_N
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set_property -dict {PACKAGE_PIN V29 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[4]] ; ## C10 FMC_LPC_LA06_P
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set_property -dict {PACKAGE_PIN W29 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[4]] ; ## C11 FMC_LPC_LA06_N
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set_property -dict {PACKAGE_PIN V22 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[5]] ; ## H13 FMC_LPC_LA07_P
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set_property -dict {PACKAGE_PIN V23 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[5]] ; ## H14 FMC_LPC_LA07_N
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set_property -dict {PACKAGE_PIN U24 IOSTANDARD LVDS} [get_ports tx_clk_out_p] ; ## G12 FMC_LPC_LA08_P
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set_property -dict {PACKAGE_PIN U25 IOSTANDARD LVDS} [get_ports tx_clk_out_n] ; ## G13 FMC_LPC_LA08_N
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set_property -dict {PACKAGE_PIN V26 IOSTANDARD LVDS} [get_ports tx_frame_out_p] ; ## D14 FMC_LPC_LA09_P
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set_property -dict {PACKAGE_PIN W26 IOSTANDARD LVDS} [get_ports tx_frame_out_n] ; ## D15 FMC_LPC_LA09_N
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set_property -dict {PACKAGE_PIN V21 IOSTANDARD LVDS} [get_ports tx_data_out_p[0]] ; ## H16 FMC_LPC_LA11_P
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set_property -dict {PACKAGE_PIN W21 IOSTANDARD LVDS} [get_ports tx_data_out_n[0]] ; ## H17 FMC_LPC_LA11_N
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set_property -dict {PACKAGE_PIN AC22 IOSTANDARD LVDS} [get_ports tx_data_out_p[1]] ; ## G15 FMC_LPC_LA12_P
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set_property -dict {PACKAGE_PIN AC23 IOSTANDARD LVDS} [get_ports tx_data_out_n[1]] ; ## G16 FMC_LPC_LA12_N
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set_property -dict {PACKAGE_PIN AA20 IOSTANDARD LVDS} [get_ports tx_data_out_p[2]] ; ## D17 FMC_LPC_LA13_P
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set_property -dict {PACKAGE_PIN AB20 IOSTANDARD LVDS} [get_ports tx_data_out_n[2]] ; ## D18 FMC_LPC_LA13_N
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set_property -dict {PACKAGE_PIN T22 IOSTANDARD LVDS} [get_ports tx_data_out_p[3]] ; ## C14 FMC_LPC_LA10_P
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set_property -dict {PACKAGE_PIN T23 IOSTANDARD LVDS} [get_ports tx_data_out_n[3]] ; ## C15 FMC_LPC_LA10_N
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set_property -dict {PACKAGE_PIN U21 IOSTANDARD LVDS} [get_ports tx_data_out_p[4]] ; ## C18 FMC_LPC_LA14_P
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set_property -dict {PACKAGE_PIN U22 IOSTANDARD LVDS} [get_ports tx_data_out_n[4]] ; ## C19 FMC_LPC_LA14_N
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set_property -dict {PACKAGE_PIN AB25 IOSTANDARD LVDS} [get_ports tx_data_out_p[5]] ; ## H19 FMC_LPC_LA15_P
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set_property -dict {PACKAGE_PIN AB26 IOSTANDARD LVDS} [get_ports tx_data_out_n[5]] ; ## H20 FMC_LPC_LA15_N
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set_property -dict {PACKAGE_PIN AA34 IOSTANDARD LVCMOS18} [get_ports gpio_status[0]] ; ## G21 FMC_LPC_LA20_P
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set_property -dict {PACKAGE_PIN AB34 IOSTANDARD LVCMOS18} [get_ports gpio_status[1]] ; ## G22 FMC_LPC_LA20_N
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set_property -dict {PACKAGE_PIN AC33 IOSTANDARD LVCMOS18} [get_ports gpio_status[2]] ; ## H25 FMC_LPC_LA21_P
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set_property -dict {PACKAGE_PIN AD33 IOSTANDARD LVCMOS18} [get_ports gpio_status[3]] ; ## H26 FMC_LPC_LA21_N
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set_property -dict {PACKAGE_PIN AC34 IOSTANDARD LVCMOS18} [get_ports gpio_status[4]] ; ## G24 FMC_LPC_LA22_P
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set_property -dict {PACKAGE_PIN AD34 IOSTANDARD LVCMOS18} [get_ports gpio_status[5]] ; ## G25 FMC_LPC_LA22_N
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set_property -dict {PACKAGE_PIN AD30 IOSTANDARD LVCMOS18} [get_ports gpio_status[6]] ; ## D23 FMC_LPC_LA23_P
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set_property -dict {PACKAGE_PIN AD31 IOSTANDARD LVCMOS18} [get_ports gpio_status[7]] ; ## D24 FMC_LPC_LA23_N
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set_property -dict {PACKAGE_PIN AE32 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[0]] ; ## H28 FMC_LPC_LA24_P
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set_property -dict {PACKAGE_PIN AF32 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[1]] ; ## H29 FMC_LPC_LA24_N
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set_property -dict {PACKAGE_PIN AE33 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[2]] ; ## G27 FMC_LPC_LA25_P
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set_property -dict {PACKAGE_PIN AF34 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[3]] ; ## G28 FMC_LPC_LA25_N
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set_property -dict {PACKAGE_PIN AA29 IOSTANDARD LVCMOS18} [get_ports gpio_en_agc] ; ## H22 FMC_LPC_LA19_P
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set_property -dict {PACKAGE_PIN AB29 IOSTANDARD LVCMOS18} [get_ports gpio_sync] ; ## H23 FMC_LPC_LA19_N
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set_property -dict {PACKAGE_PIN V31 IOSTANDARD LVCMOS18} [get_ports gpio_resetb] ; ## H31 FMC_LPC_LA28_P
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set_property -dict {PACKAGE_PIN AB21 IOSTANDARD LVCMOS18} [get_ports enable] ; ## G18 FMC_LPC_LA16_P
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set_property -dict {PACKAGE_PIN AC21 IOSTANDARD LVCMOS18} [get_ports txnrx] ; ## G19 FMC_LPC_LA16_N
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set_property -dict {PACKAGE_PIN AF33 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports spi_csn_0] ; ## D26 FMC_LPC_LA26_P
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set_property -dict {PACKAGE_PIN AG34 IOSTANDARD LVCMOS18} [get_ports spi_clk] ; ## D27 FMC_LPC_LA26_N
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set_property -dict {PACKAGE_PIN AG31 IOSTANDARD LVCMOS18} [get_ports spi_mosi] ; ## C26 FMC_LPC_LA27_P
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set_property -dict {PACKAGE_PIN AG32 IOSTANDARD LVCMOS18} [get_ports spi_miso] ; ## C27 FMC_LPC_LA27_N
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# clocks
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create_clock -name rx_clk -period 4.00 [get_ports rx_clk_in_p]
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#set_property CFGBVS 1.8V fmcomms2_kcu105
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@ -0,0 +1,16 @@
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source ../../scripts/adi_env.tcl
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source $ad_hdl_dir/projects/scripts/adi_project.tcl
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source $ad_hdl_dir/projects/scripts/adi_board.tcl
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adi_project_xilinx fmcomms2_kcu105
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adi_project_files fmcomms2_kcu105 [list \
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"system_top.v" \
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"system_constr.xdc"\
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"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
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"$ad_hdl_dir/projects/common/kcu105/kcu105_system_constr.xdc" \
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"$ad_hdl_dir/projects/common/kcu105/kcu105_system_lutram_constr.xdc" ]
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adi_project_run fmcomms2_kcu105
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source $ad_hdl_dir/library/axi_ad9361/axi_ad9361_delay.tcl
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsabilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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input sys_rst,
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input sys_clk_p,
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input sys_clk_n,
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input uart_sin,
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output uart_sout,
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output ddr4_act_n,
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output [16:0] ddr4_addr,
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output [ 1:0] ddr4_ba,
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output [ 0:0] ddr4_bg,
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output ddr4_ck_p,
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output ddr4_ck_n,
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output [ 0:0] ddr4_cke,
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output [ 0:0] ddr4_cs_n,
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inout [ 7:0] ddr4_dm_n,
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inout [63:0] ddr4_dq,
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inout [ 7:0] ddr4_dqs_p,
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inout [ 7:0] ddr4_dqs_n,
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output [ 0:0] ddr4_odt,
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output ddr4_reset_n,
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output mdio_mdc,
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inout mdio_mdio,
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input phy_clk_p,
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input phy_clk_n,
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output phy_rst_n,
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input phy_rx_p,
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input phy_rx_n,
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output phy_tx_p,
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output phy_tx_n,
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output fan_pwm,
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inout [16:0] gpio_bd,
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inout iic_scl,
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inout iic_sda,
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input rx_clk_in_p,
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input rx_clk_in_n,
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input rx_frame_in_p,
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input rx_frame_in_n,
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input [ 5:0] rx_data_in_p,
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input [ 5:0] rx_data_in_n,
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output tx_clk_out_p,
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output tx_clk_out_n,
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output tx_frame_out_p,
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output tx_frame_out_n,
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output [ 5:0] tx_data_out_p,
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output [ 5:0] tx_data_out_n,
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output enable,
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output txnrx,
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output gpio_resetb,
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output gpio_sync,
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output gpio_en_agc,
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output [ 3:0] gpio_ctl,
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input [ 7:0] gpio_status,
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output spi_csn_0,
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output spi_clk,
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output spi_mosi,
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input spi_miso);
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// internal signals
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wire [63:0] gpio_i;
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wire [63:0] gpio_o;
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wire [63:0] gpio_t;
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wire [ 7:0] spi_csn;
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// wire spi_clk; redeclaration
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wire spi_mosi;
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wire spi_miso;
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// defaults
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assign fan_pwm = 1'b1;
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assign spi_csn_0 = spi_csn[0];
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// instantiations
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ad_iobuf #(.DATA_WIDTH(15)) i_iobuf (
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.dio_t (gpio_t[46:32]),
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.dio_i (gpio_o[46:32]),
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.dio_o (gpio_i[46:32]),
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.dio_p ({ gpio_resetb,
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gpio_sync,
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gpio_en_agc,
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gpio_ctl,
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gpio_status}));
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ad_iobuf #(.DATA_WIDTH(17)) i_iobuf_bd (
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.dio_t (gpio_t[16:0]),
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.dio_i (gpio_o[16:0]),
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.dio_o (gpio_i[16:0]),
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.dio_p (gpio_bd));
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system_wrapper i_system_wrapper (
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.c0_ddr4_act_n (ddr4_act_n),
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.c0_ddr4_adr (ddr4_addr),
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.c0_ddr4_ba (ddr4_ba),
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.c0_ddr4_bg (ddr4_bg),
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.c0_ddr4_ck_c (ddr4_ck_n),
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.c0_ddr4_ck_t (ddr4_ck_p),
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.c0_ddr4_cke (ddr4_cke),
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.c0_ddr4_cs_n (ddr4_cs_n),
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.c0_ddr4_dm_n (ddr4_dm_n),
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.c0_ddr4_dq (ddr4_dq),
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.c0_ddr4_dqs_c (ddr4_dqs_n),
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.c0_ddr4_dqs_t (ddr4_dqs_p),
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.c0_ddr4_odt (ddr4_odt),
|
||||
.c0_ddr4_reset_n (ddr4_reset_n),
|
||||
.gpio0_i (gpio_i[31:0]),
|
||||
.gpio0_o (gpio_o[31:0]),
|
||||
.gpio0_t (gpio_t[31:0]),
|
||||
.gpio1_i (gpio_i[63:32]),
|
||||
.gpio1_o (gpio_o[63:32]),
|
||||
.gpio1_t (gpio_t[63:32]),
|
||||
.iic_main_scl_io (iic_scl),
|
||||
.iic_main_sda_io (iic_sda),
|
||||
.mb_intr_05 (1'b0),
|
||||
.mb_intr_06 (1'b0),
|
||||
.mb_intr_07 (1'b0),
|
||||
.mb_intr_08 (1'b0),
|
||||
.mdio_mdc (mdio_mdc),
|
||||
.mdio_mdio_io (mdio_mdio),
|
||||
.phy_clk_clk_n (phy_clk_n),
|
||||
.phy_clk_clk_p (phy_clk_p),
|
||||
.phy_rst_n (phy_rst_n),
|
||||
.phy_sd (1'b1),
|
||||
.sgmii_rxn (phy_rx_n),
|
||||
.sgmii_rxp (phy_rx_p),
|
||||
.sgmii_txn (phy_tx_n),
|
||||
.sgmii_txp (phy_tx_p),
|
||||
|
||||
.spi_clk_i (spi_clk),
|
||||
.spi_clk_o (spi_clk),
|
||||
.spi_csn_i (spi_csn),
|
||||
.spi_csn_o (spi_csn),
|
||||
.spi_sdi_i (spi_miso),
|
||||
.spi_sdo_i (spi_mosi),
|
||||
.spi_sdo_o (spi_mosi),
|
||||
.sys_clk_clk_n (sys_clk_n),
|
||||
.sys_clk_clk_p (sys_clk_p),
|
||||
.sys_rst (sys_rst),
|
||||
|
||||
.rx_clk_in_n (rx_clk_in_n),
|
||||
.rx_clk_in_p (rx_clk_in_p),
|
||||
.rx_data_in_n (rx_data_in_n),
|
||||
.rx_data_in_p (rx_data_in_p),
|
||||
.rx_frame_in_n (rx_frame_in_n),
|
||||
.rx_frame_in_p (rx_frame_in_p),
|
||||
|
||||
.tdd_sync_i (1'b0),
|
||||
.tdd_sync_o (),
|
||||
.tdd_sync_t (),
|
||||
|
||||
.tx_clk_out_n (tx_clk_out_n),
|
||||
.tx_clk_out_p (tx_clk_out_p),
|
||||
.tx_data_out_n (tx_data_out_n),
|
||||
.tx_data_out_p (tx_data_out_p),
|
||||
.tx_frame_out_n (tx_frame_out_n),
|
||||
.tx_frame_out_p (tx_frame_out_p),
|
||||
.txnrx (txnrx),
|
||||
.up_enable (gpio_o[47]),
|
||||
.up_txnrx (gpio_o[48]),
|
||||
.uart_sin (uart_sin),
|
||||
.uart_sout (uart_sout));
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
Loading…
Reference in New Issue