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prcfg: Initial check in of PR modules 

Initial check in of the partial reconfiguraiton modules.
main
Istvan Csomortani 2014-06-05 14:58:14 +03:00
parent f452e40192
commit ea22d29862
15 changed files with 3496 additions and 0 deletions
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187
library/prcfg/bist/prcfg_adc.v Normal file
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// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ns
module prcfg_adc (
clk,
// control ports
control,
status,
// FIFO interface
src_adc_dwr,
src_adc_dsync,
src_adc_ddata,
src_adc_dovf,
dst_adc_dwr,
dst_adc_dsync,
dst_adc_ddata,
dst_adc_dovf
);
localparam RP_ID = 8'hA0;
parameter CHANNEL_ID = 0;
input clk;
input [31:0] control;
output [31:0] status;
input src_adc_dwr;
input src_adc_dsync;
input [31:0] src_adc_ddata;
output src_adc_dovf;
output dst_adc_dwr;
output dst_adc_dsync;
output [31:0] dst_adc_ddata;
input dst_adc_dovf;
reg [31:0] status = 0;
reg [31:0] adc_pn_data = 0;
reg adc_dvalid_d = 0;
reg [31:0] adc_data = 0;
reg [ 7:0] adc_pn_oos_count = 0;
reg adc_pn_oos = 0;
reg adc_pn_err = 0;
wire [ 3:0] mode;
wire [ 3:0] channel_sel;
wire adc_dvalid;
wire [31:0] adc_pn_data_s;
wire adc_pn_update_s;
wire adc_pn_match_s;
wire adc_pn_err_s;
// prbs function
function [31:0] pn;
input [31:0] din;
reg [31:0] dout;
begin
dout[31] = din[14] ^ din[13];
dout[30] = din[13] ^ din[12];
dout[29] = din[12] ^ din[11];
dout[28] = din[11] ^ din[10];
dout[27] = din[10] ^ din[9];
dout[26] = din[9] ^ din[8];
dout[25] = din[8] ^ din[7];
dout[24] = din[7] ^ din[6];
dout[23] = din[6] ^ din[5];
dout[22] = din[5] ^ din[4];
dout[21] = din[4] ^ din[3];
dout[20] = din[3] ^ din[2];
dout[19] = din[2] ^ din[1];
dout[18] = din[1] ^ din[0];
dout[17] = din[0] ^ din[14] ^ din[13];
dout[16] = din[14] ^ din[12];
dout[15] = din[13] ^ din[11];
dout[14] = din[12] ^ din[10];
dout[13] = din[11] ^ din[9];
dout[12] = din[10] ^ din[8];
dout[11] = din[9] ^ din[7];
dout[10] = din[8] ^ din[6];
dout[9] = din[7] ^ din[5];
dout[8] = din[6] ^ din[4];
dout[7] = din[5] ^ din[3];
dout[6] = din[4] ^ din[2];
dout[5] = din[3] ^ din[1];
dout[4] = din[2] ^ din[0];
dout[3] = din[1] ^ din[14] ^ din[13];
dout[2] = din[0] ^ din[13] ^ din[12];
dout[1] = din[14] ^ din[12] ^ din[13] ^ din[11];
dout[0] = din[13] ^ din[11] ^ din[12] ^ din[10];
pn = dout;
end
endfunction
assign channel_sel = control[3:0];
assign mode = control[7:4];
assign adc_dvalid = src_adc_dwr & src_adc_dsync;
// prbs monitor
assign adc_pn_data_s = (adc_pn_oos == 1'b1) ? src_adc_ddata : adc_pn_data;
assign adc_pn_update_s = ~(adc_pn_oos ^ adc_pn_match_s);
assign adc_pn_match_s = (adc_data == adc_pn_data) ? 1'b1 : 1'b0;
assign adc_pn_err_s = ~(adc_pn_oos | adc_pn_match_s);
always @(posedge clk) begin
if(adc_dvalid == 1'b1) begin
adc_data <= src_adc_ddata;
adc_pn_data <= pn(adc_pn_data_s);
end
adc_dvalid_d <= adc_dvalid;
if(adc_dvalid_d == 1'b1) begin
adc_pn_err <= adc_pn_err_s;
if(adc_pn_update_s == 1'b1) begin
if(adc_pn_oos_count >= 'd16) begin
adc_pn_oos_count <= 'd0;
adc_pn_oos <= ~adc_pn_oos;
end else begin
adc_pn_oos_count <= adc_pn_oos_count + 1;
adc_pn_oos <= adc_pn_oos;
end
end else begin
adc_pn_oos_count <= 'd0;
adc_pn_oos <= adc_pn_oos;
end
end
end
// rx path are passed through on test mode
assign dst_adc_dwr = src_adc_dwr;
assign dst_adc_dsync = src_adc_dsync;
assign dst_adc_ddata = src_adc_ddata;
assign src_adc_dovf = dst_adc_dovf;
// setup status bits for gpio_out
always @(posedge clk) begin
if((mode == 3'd2) && (channel_sel == CHANNEL_ID)) begin
status <= {22'h0, adc_pn_err, adc_pn_oos, RP_ID};
end else begin
status <= {24'h0, RP_ID};
end
end
endmodule

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library/prcfg/bist/prcfg_dac.v Normal file
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// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ns
module prcfg_dac(
clk,
// control ports
control,
status,
// FIFO interface
src_dac_drd,
src_dac_ddata,
src_dac_dunf,
dst_dac_drd,
dst_dac_ddata,
dst_dac_dunf
);
localparam RP_ID = 8'hA1;
parameter CHANNEL_ID = 0;
input clk;
input [31:0] control;
output [31:0] status;
output src_dac_drd;
input [31:0] src_dac_ddata;
input src_dac_dunf;
input dst_dac_drd;
output [31:0] dst_dac_ddata;
output dst_dac_dunf;
reg dst_dac_dunf = 0;
reg [31:0] dst_dac_ddata = 0;
reg src_dac_drd = 0;
reg [31:0] dac_prbs = 0;
reg [ 2:0] counter = 0;
reg pattern = 0;
reg [15:0] sin_tone = 0;
reg [15:0] cos_tone = 0;
wire [ 3:0] mode;
wire [31:0] dac_data_mode0;
wire [31:0] dac_data_mode1;
wire [31:0] dac_data_mode2;
wire [31:0] dac_data_mode3;
// prbs function
function [31:0] pn;
input [31:0] din;
reg [31:0] dout;
begin
dout[31] = din[14] ^ din[13];
dout[30] = din[13] ^ din[12];
dout[29] = din[12] ^ din[11];
dout[28] = din[11] ^ din[10];
dout[27] = din[10] ^ din[9];
dout[26] = din[9] ^ din[8];
dout[25] = din[8] ^ din[7];
dout[24] = din[7] ^ din[6];
dout[23] = din[6] ^ din[5];
dout[22] = din[5] ^ din[4];
dout[21] = din[4] ^ din[3];
dout[20] = din[3] ^ din[2];
dout[19] = din[2] ^ din[1];
dout[18] = din[1] ^ din[0];
dout[17] = din[0] ^ din[14] ^ din[13];
dout[16] = din[14] ^ din[12];
dout[15] = din[13] ^ din[11];
dout[14] = din[12] ^ din[10];
dout[13] = din[11] ^ din[9];
dout[12] = din[10] ^ din[8];
dout[11] = din[9] ^ din[7];
dout[10] = din[8] ^ din[6];
dout[9] = din[7] ^ din[5];
dout[8] = din[6] ^ din[4];
dout[7] = din[5] ^ din[3];
dout[6] = din[4] ^ din[2];
dout[5] = din[3] ^ din[1];
dout[4] = din[2] ^ din[0];
dout[3] = din[1] ^ din[14] ^ din[13];
dout[2] = din[0] ^ din[13] ^ din[12];
dout[1] = din[14] ^ din[12] ^ din[13] ^ din[11];
dout[0] = din[13] ^ din[11] ^ din[12] ^ din[10];
pn = dout;
end
endfunction
assign status = {24'h0, RP_ID};
assign mode = control[7:4];
// pass through for tx/rx side
assign dac_data_mode0 = src_dac_ddata;
// sine tone generation
always @(posedge clk) begin
if (dst_dac_drd == 1'h1) begin
counter <= counter + 1;
end
end
always @(counter) begin
case(counter)
3'd0 : begin
sin_tone <= 16'h0000;
cos_tone <= 16'h7FFF;
end
3'd1 : begin
sin_tone <= 16'h5A82;
cos_tone <= 16'h5A82;
end
3'd2 : begin
sin_tone <= 16'h7FFF;
cos_tone <= 16'h0000;
end
3'd3 : begin
sin_tone <= 16'h5A82;
cos_tone <= 16'hA57E;
end
3'd4 : begin
sin_tone <= 16'h0000;
cos_tone <= 16'h7FFF;
end
3'd5 : begin
sin_tone <= 16'hA57E;
cos_tone <= 16'hA57E;
end
3'd6 : begin
sin_tone <= 16'h8001;
cos_tone <= 16'h0000;
end
3'd7 : begin
sin_tone <= 16'hA57E;
cos_tone <= 16'h5A82;
end
endcase
end
assign dac_data_mode1 = {sin_tone, cos_tone};
// prbs generation
always @(posedge clk) begin
if(dst_dac_drd == 1'h1) begin
dac_prbs <= pn(dac_prbs);
end
end
assign dac_data_mode2 = dac_prbs;
// constant pattern generator
always @(posedge clk) begin
if(dst_dac_drd == 1'h1) begin
pattern <= ~pattern;
end
end
assign dac_data_mode3 = (pattern == 1'h1) ?
{16'h5555, 16'hAAAA, 16'h5555, 16'hAAAA} :
{16'hAAAA, 16'h5555, 16'hAAAA, 16'h5555};
// output mux for tx side
always @(posedge clk) begin
src_dac_drd <= (mode == 0) ? dst_dac_drd : 1'b0;
dst_dac_dunf <= (mode == 0) ? src_dac_dunf : 1'b0;
end
always @(posedge clk) begin
case(mode)
4'h0 : begin
dst_dac_ddata <= dac_data_mode0;
end
4'h1 : begin
dst_dac_ddata <= dac_data_mode1;
end
4'h2 : begin
dst_dac_ddata <= dac_data_mode2;
end
4'h3 : begin
dst_dac_ddata <= dac_data_mode3;
end
default : begin
dst_dac_ddata <= dac_data_mode0;
end
endcase
end
endmodule

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// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ns
module prcfg_top(
clk,
// gpio
gpio_input,
gpio_output,
// TX side
dma_dac_drd,
dma_dac_dunf,
dma_dac_ddata,
core_dac_drd,
core_dac_dunf,
core_dac_ddata,
// RX side
core_adc_dwr,
core_adc_dsync,
core_adc_ddata,
core_adc_ovf,
dma_adc_dwr,
dma_adc_dsync,
dma_adc_ddata,
dma_adc_ovf
);
localparam ENABELED = 1;
localparam DATA_WIDTH = 32;
parameter NUM_CHANNEL = 2;
parameter ADC_EN = 1;
parameter DAC_EN = 1;
localparam DBUS_WIDTH = DATA_WIDTH * NUM_CHANNEL;
input clk;
input [31:0] gpio_input;
output [31:0] gpio_output;
output dma_dac_drd;
input dma_dac_dunf;
input [(DBUS_WIDTH - 1):0] dma_dac_ddata;
input core_dac_drd;
output core_dac_dunf;
output [(DBUS_WIDTH - 1):0] core_dac_ddata;
input core_adc_dwr;
input core_adc_dsync;
input [(DBUS_WIDTH - 1):0] core_adc_ddata;
output core_adc_ovf;
output dma_adc_dwr;
output dma_adc_dsync;
output [(DBUS_WIDTH - 1):0] dma_adc_ddata;
input dma_adc_ovf;
wire [31:0] adc_status_s[(NUM_CHANNEL - 1):0];
wire [31:0] dac_status_s[(NUM_CHANNEL - 1):0];
genvar l_inst;
generate
for(l_inst = 0; l_inst < NUM_CHANNEL; l_inst = l_inst + 1) begin: tx_rx_data_path
if(ADC_EN == ENABELED) begin
if(l_inst == 0) begin
prcfg_adc #(
.CHANNEL_ID(l_inst)
) i_prcfg_adc_1 (
.clk(clk),
.control(gpio_input),
.status(adc_status_s[l_inst]),
.src_adc_dwr(core_adc_dwr),
.src_adc_dsync(core_adc_dsync),
.src_adc_ddata(core_adc_ddata[(DATA_WIDTH - 1):0]),
.src_adc_dovf(core_adc_ovf),
.dst_adc_dwr(dma_adc_dwr),
.dst_adc_dsync(dma_adc_dsync),
.dst_adc_ddata(dma_adc_ddata[(DATA_WIDTH - 1):0]),
.dst_adc_dovf(dma_adc_ovf)
);
end else begin
prcfg_adc #(
.CHANNEL_ID(l_inst)
) i_prcfg_adc_1 (
.clk(clk),
.control(gpio_input),
.status(adc_status_s[l_inst]),
.src_adc_dwr(core_adc_dwr),
.src_adc_dsync(core_adc_dsync),
.src_adc_ddata(core_adc_ddata[((DATA_WIDTH * (l_inst + 1)) - 1):(DATA_WIDTH * l_inst)]),
.src_adc_dovf(),
.dst_adc_dwr(),
.dst_adc_dsync(),
.dst_adc_ddata(dma_adc_ddata[((DATA_WIDTH * (l_inst + 1)) - 1):(DATA_WIDTH * l_inst)]),
.dst_adc_dovf(dma_adc_ovf)
);
end
end
if(DAC_EN == ENABELED) begin
if(l_inst == 0) begin
prcfg_dac #(
.CHANNEL_ID(l_inst)
) i_prcfg_dac_1 (
.clk(clk),
.control(gpio_input),
.status(dac_status_s[l_inst]),
.src_dac_drd(dma_dac_drd),
.src_dac_ddata(dma_dac_ddata[(DATA_WIDTH - 1):0]),
.src_dac_dunf(dma_dac_dunf),
.dst_dac_drd(core_dac_drd),
.dst_dac_ddata(core_dac_ddata[(DATA_WIDTH - 1):0]),
.dst_dac_dunf(core_dac_dunf)
);
end else begin
prcfg_dac #(
.CHANNEL_ID(l_inst)
) i_prcfg_dac_1 (
.clk(clk),
.control(gpio_input),
.status(dac_status_s[l_inst]),
.src_dac_drd(),
.src_dac_ddata(dma_dac_ddata[((DATA_WIDTH * (l_inst + 1)) - 1):(DATA_WIDTH * l_inst)]),
.src_dac_dunf(dma_dac_dunf),
.dst_dac_drd(core_dac_drd),
.dst_dac_ddata(core_dac_ddata[((DATA_WIDTH * (l_inst + 1)) - 1):(DATA_WIDTH * l_inst)]),
.dst_dac_dunf()
);
end
end
assign gpio_output = gpio_output | adc_status_s[l_inst] | dac_status_s[l_inst];
end
endgenerate
endmodule

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library/prcfg/default/prcfg_adc.v Normal file
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// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ns
module prcfg_adc (
clk,
// control ports
control,
status,
// FIFO interface
src_adc_dwr,
src_adc_dsync,
src_adc_ddata,
src_adc_dovf,
dst_adc_dwr,
dst_adc_dsync,
dst_adc_ddata,
dst_adc_dovf
);
localparam RP_ID = 8'hA0;
parameter CHANNEL_ID = 0;
input clk;
input [31:0] control;
output [31:0] status;
input src_adc_dwr;
input src_adc_dsync;
input [31:0] src_adc_ddata;
output src_adc_dovf;
output dst_adc_dwr;
output dst_adc_dsync;
output [31:0] dst_adc_ddata;
input dst_adc_dovf;
assign status = {24'h0, RP_ID};
assign dst_adc_dwr = src_adc_dwr;
assign dst_adc_dsync = src_adc_dsync;
assign dst_adc_ddata = src_adc_ddata;
assign src_adc_dovf = dst_adc_dovf;
endmodule

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library/prcfg/default/prcfg_dac.v Normal file
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// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ns
module prcfg_dac(
clk,
// control ports
control,
status,
// FIFO interface
src_dac_drd,
src_dac_ddata,
src_dac_dunf,
dst_dac_drd,
dst_dac_ddata,
dst_dac_dunf
);
localparam RP_ID = 8'hA0;
parameter CHANNEL_ID = 0;
input clk;
input [31:0] control;
output [31:0] status;
output src_dac_drd;
input [31:0] src_dac_ddata;
input src_dac_dunf;
input dst_dac_drd;
output [31:0] dst_dac_ddata;
output dst_dac_dunf;
assign status = {24'h0, RP_ID};
assign src_dac_drd = dst_dac_drd;
assign dst_dac_ddata = src_dac_ddata;
assign dst_dac_dunf = src_dac_dunf;
endmodule

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// ------------------------------------------------------------
//
// File Name: hdlsrc\qpskhdltest\FIR_Interpolation
// Created: 2014-04-21 15:30:32
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// ------------------------------------------------------------
//
//
// ------------------------------------------------------------
//
// Module: FIR_Interpolation
// Source Path: /FIR_Interpolation
//
// ------------------------------------------------------------
//
// HDL Implementation : Fully parallel
// Multipliers : 6
// Folding Factor : 1
`timescale 1 ns / 1 ns
module FIR_Interpolation
(
clk,
enb_1_1_1,
reset,
FIR_Interpolation_in_re,
FIR_Interpolation_in_im,
FIR_Interpolation_out_re,
FIR_Interpolation_out_im
);
input clk;
input enb_1_1_1;
input reset;
input signed [15:0] FIR_Interpolation_in_re; //sfix16_En15
input signed [15:0] FIR_Interpolation_in_im; //sfix16_En15
output signed [15:0] FIR_Interpolation_out_re; //sfix16_En15
output signed [15:0] FIR_Interpolation_out_im; //sfix16_En15
////////////////////////////////////////////////////////////////
//Module Architecture: FIR_Interpolation
////////////////////////////////////////////////////////////////
// Local Functions
// Type Definitions
// Constants
parameter signed [15:0] coeffphase1_1 = 16'b1111111100110010; //sfix16_En16
parameter signed [15:0] coeffphase1_2 = 16'b1111111000101100; //sfix16_En16
parameter signed [15:0] coeffphase1_3 = 16'b1111100001010001; //sfix16_En16
parameter signed [15:0] coeffphase1_4 = 16'b0111001100111111; //sfix16_En16
parameter signed [15:0] coeffphase1_5 = 16'b1111100001010001; //sfix16_En16
parameter signed [15:0] coeffphase1_6 = 16'b1111111000101100; //sfix16_En16
parameter signed [15:0] coeffphase1_7 = 16'b1111111100110010; //sfix16_En16
parameter signed [15:0] coeffphase2_1 = 16'b1111111101100001; //sfix16_En16
parameter signed [15:0] coeffphase2_2 = 16'b1111111010000110; //sfix16_En16
parameter signed [15:0] coeffphase2_3 = 16'b1111100011000010; //sfix16_En16
parameter signed [15:0] coeffphase2_4 = 16'b0110110010100111; //sfix16_En16
parameter signed [15:0] coeffphase2_5 = 16'b1111101111000100; //sfix16_En16
parameter signed [15:0] coeffphase2_6 = 16'b1111111011011011; //sfix16_En16
parameter signed [15:0] coeffphase2_7 = 16'b0000000000000000; //sfix16_En16
parameter signed [15:0] coeffphase3_1 = 16'b0000000000000000; //sfix16_En16
parameter signed [15:0] coeffphase3_2 = 16'b0000000000000000; //sfix16_En16
parameter signed [15:0] coeffphase3_3 = 16'b0000000000000000; //sfix16_En16
parameter signed [15:0] coeffphase3_4 = 16'b0101101010000011; //sfix16_En16
parameter signed [15:0] coeffphase3_5 = 16'b0000000000000000; //sfix16_En16
parameter signed [15:0] coeffphase3_6 = 16'b0000000000000000; //sfix16_En16
parameter signed [15:0] coeffphase3_7 = 16'b0000000000000000; //sfix16_En16
parameter signed [15:0] coeffphase4_1 = 16'b0000000010111111; //sfix16_En16
parameter signed [15:0] coeffphase4_2 = 16'b0000000111111010; //sfix16_En16
parameter signed [15:0] coeffphase4_3 = 16'b0000111110000110; //sfix16_En16
parameter signed [15:0] coeffphase4_4 = 16'b0100000100110001; //sfix16_En16
parameter signed [15:0] coeffphase4_5 = 16'b0000001011001001; //sfix16_En16
parameter signed [15:0] coeffphase4_6 = 16'b0000000011101010; //sfix16_En16
parameter signed [15:0] coeffphase4_7 = 16'b0000000000000000; //sfix16_En16
parameter signed [15:0] coeffphase5_1 = 16'b0000000100101010; //sfix16_En16
parameter signed [15:0] coeffphase5_2 = 16'b0000001101001011; //sfix16_En16
parameter signed [15:0] coeffphase5_3 = 16'b0010011001101010; //sfix16_En16
parameter signed [15:0] coeffphase5_4 = 16'b0010011001101010; //sfix16_En16
parameter signed [15:0] coeffphase5_5 = 16'b0000001101001011; //sfix16_En16
parameter signed [15:0] coeffphase5_6 = 16'b0000000100101010; //sfix16_En16
parameter signed [15:0] coeffphase5_7 = 16'b0000000000000000; //sfix16_En16
parameter signed [15:0] coeffphase6_1 = 16'b0000000011101010; //sfix16_En16
parameter signed [15:0] coeffphase6_2 = 16'b0000001011001001; //sfix16_En16
parameter signed [15:0] coeffphase6_3 = 16'b0100000100110001; //sfix16_En16
parameter signed [15:0] coeffphase6_4 = 16'b0000111110000110; //sfix16_En16
parameter signed [15:0] coeffphase6_5 = 16'b0000000111111010; //sfix16_En16
parameter signed [15:0] coeffphase6_6 = 16'b0000000010111111; //sfix16_En16
parameter signed [15:0] coeffphase6_7 = 16'b0000000000000000; //sfix16_En16
parameter signed [15:0] coeffphase7_1 = 16'b0000000000000000; //sfix16_En16
parameter signed [15:0] coeffphase7_2 = 16'b0000000000000000; //sfix16_En16
parameter signed [15:0] coeffphase7_3 = 16'b0101101010000011; //sfix16_En16
parameter signed [15:0] coeffphase7_4 = 16'b0000000000000000; //sfix16_En16
parameter signed [15:0] coeffphase7_5 = 16'b0000000000000000; //sfix16_En16
parameter signed [15:0] coeffphase7_6 = 16'b0000000000000000; //sfix16_En16
parameter signed [15:0] coeffphase7_7 = 16'b0000000000000000; //sfix16_En16
parameter signed [15:0] coeffphase8_1 = 16'b1111111011011011; //sfix16_En16
parameter signed [15:0] coeffphase8_2 = 16'b1111101111000100; //sfix16_En16
parameter signed [15:0] coeffphase8_3 = 16'b0110110010100111; //sfix16_En16
parameter signed [15:0] coeffphase8_4 = 16'b1111100011000010; //sfix16_En16
parameter signed [15:0] coeffphase8_5 = 16'b1111111010000110; //sfix16_En16
parameter signed [15:0] coeffphase8_6 = 16'b1111111101100001; //sfix16_En16
parameter signed [15:0] coeffphase8_7 = 16'b0000000000000000; //sfix16_En16
// Signals
reg [2:0] cur_count; // ufix3
wire phase_7; // boolean
reg signed [15:0] delay_pipeline_re [0:5] ; // sfix16_En15
reg signed [15:0] delay_pipeline_im [0:5] ; // sfix16_En15
wire signed [15:0] product_re; // sfix16_En15
wire signed [15:0] product_im; // sfix16_En15
wire signed [15:0] product_mux; // sfix16_En16
wire signed [31:0] mul_temp; // sfix32_En31
wire signed [31:0] mul_temp_1; // sfix32_En31
wire signed [15:0] product_1_re; // sfix16_En15
wire signed [15:0] product_1_im; // sfix16_En15
wire signed [15:0] product_mux_1; // sfix16_En16
wire signed [31:0] mul_temp_2; // sfix32_En31
wire signed [31:0] mul_temp_3; // sfix32_En31
wire signed [15:0] product_2_re; // sfix16_En15
wire signed [15:0] product_2_im; // sfix16_En15
wire signed [15:0] product_mux_2; // sfix16_En16
wire signed [31:0] mul_temp_4; // sfix32_En31
wire signed [31:0] mul_temp_5; // sfix32_En31
wire signed [15:0] product_3_re; // sfix16_En15
wire signed [15:0] product_3_im; // sfix16_En15
wire signed [15:0] product_mux_3; // sfix16_En16
wire signed [31:0] mul_temp_6; // sfix32_En31
wire signed [31:0] mul_temp_7; // sfix32_En31
wire signed [15:0] product_4_re; // sfix16_En15
wire signed [15:0] product_4_im; // sfix16_En15
wire signed [15:0] product_mux_4; // sfix16_En16
wire signed [31:0] mul_temp_8; // sfix32_En31
wire signed [31:0] mul_temp_9; // sfix32_En31
wire signed [15:0] product_5_re; // sfix16_En15
wire signed [15:0] product_5_im; // sfix16_En15
wire signed [15:0] product_mux_5; // sfix16_En16
wire signed [31:0] mul_temp_10; // sfix32_En31
wire signed [31:0] mul_temp_11; // sfix32_En31
wire signed [15:0] product_6_re; // sfix16_En15
wire signed [15:0] product_6_im; // sfix16_En15
wire signed [15:0] product_mux_6; // sfix16_En16
wire signed [31:0] mul_temp_12; // sfix32_En31
wire signed [31:0] mul_temp_13; // sfix32_En31
wire signed [15:0] sum1_re; // sfix16_En15
wire signed [15:0] sum1_im; // sfix16_En15
wire signed [15:0] add_cast; // sfix16_En15
wire signed [15:0] add_cast_1; // sfix16_En15
wire signed [16:0] add_temp; // sfix17_En15
wire signed [15:0] add_cast_2; // sfix16_En15
wire signed [15:0] add_cast_3; // sfix16_En15
wire signed [16:0] add_temp_1; // sfix17_En15
wire signed [15:0] sum2_re; // sfix16_En15
wire signed [15:0] sum2_im; // sfix16_En15
wire signed [15:0] add_cast_4; // sfix16_En15
wire signed [15:0] add_cast_5; // sfix16_En15
wire signed [16:0] add_temp_2; // sfix17_En15
wire signed [15:0] add_cast_6; // sfix16_En15
wire signed [15:0] add_cast_7; // sfix16_En15
wire signed [16:0] add_temp_3; // sfix17_En15
wire signed [15:0] sum3_re; // sfix16_En15
wire signed [15:0] sum3_im; // sfix16_En15
wire signed [15:0] add_cast_8; // sfix16_En15
wire signed [15:0] add_cast_9; // sfix16_En15
wire signed [16:0] add_temp_4; // sfix17_En15
wire signed [15:0] add_cast_10; // sfix16_En15
wire signed [15:0] add_cast_11; // sfix16_En15
wire signed [16:0] add_temp_5; // sfix17_En15
wire signed [15:0] sum4_re; // sfix16_En15
wire signed [15:0] sum4_im; // sfix16_En15
wire signed [15:0] add_cast_12; // sfix16_En15
wire signed [15:0] add_cast_13; // sfix16_En15
wire signed [16:0] add_temp_6; // sfix17_En15
wire signed [15:0] add_cast_14; // sfix16_En15
wire signed [15:0] add_cast_15; // sfix16_En15
wire signed [16:0] add_temp_7; // sfix17_En15
wire signed [15:0] sum5_re; // sfix16_En15
wire signed [15:0] sum5_im; // sfix16_En15
wire signed [15:0] add_cast_16; // sfix16_En15
wire signed [15:0] add_cast_17; // sfix16_En15
wire signed [16:0] add_temp_8; // sfix17_En15
wire signed [15:0] add_cast_18; // sfix16_En15
wire signed [15:0] add_cast_19; // sfix16_En15
wire signed [16:0] add_temp_9; // sfix17_En15
wire signed [15:0] sum6_re; // sfix16_En15
wire signed [15:0] sum6_im; // sfix16_En15
wire signed [15:0] add_cast_20; // sfix16_En15
wire signed [15:0] add_cast_21; // sfix16_En15
wire signed [16:0] add_temp_10; // sfix17_En15
wire signed [15:0] add_cast_22; // sfix16_En15
wire signed [15:0] add_cast_23; // sfix16_En15
wire signed [16:0] add_temp_11; // sfix17_En15
reg signed [15:0] regout_re; // sfix16_En15
reg signed [15:0] regout_im; // sfix16_En15
wire signed [15:0] muxout_re; // sfix16_En15
wire signed [15:0] muxout_im; // sfix16_En15
// Block Statements
always @ (posedge clk or posedge reset)
begin: ce_output
if (reset == 1'b1) begin
cur_count <= 3'b000;
end
else begin
if (enb_1_1_1 == 1'b1) begin
if (cur_count == 3'b111) begin
cur_count <= 3'b000;
end
else begin
cur_count <= cur_count + 1;
end
end
end
end // ce_output
assign phase_7 = (cur_count == 3'b111 && enb_1_1_1 == 1'b1)? 1 : 0;
// ---------------- Delay Registers ----------------
always @( posedge clk or posedge reset)
begin: Delay_Pipeline_process
if (reset == 1'b1) begin
delay_pipeline_re[0] <= 0;
delay_pipeline_re[1] <= 0;
delay_pipeline_re[2] <= 0;
delay_pipeline_re[3] <= 0;
delay_pipeline_re[4] <= 0;
delay_pipeline_re[5] <= 0;
delay_pipeline_im[0] <= 0;
delay_pipeline_im[1] <= 0;
delay_pipeline_im[2] <= 0;
delay_pipeline_im[3] <= 0;
delay_pipeline_im[4] <= 0;
delay_pipeline_im[5] <= 0;
end
else begin
if (phase_7 == 1'b1) begin
delay_pipeline_re[0] <= FIR_Interpolation_in_re;
delay_pipeline_re[1] <= delay_pipeline_re[0];
delay_pipeline_re[2] <= delay_pipeline_re[1];
delay_pipeline_re[3] <= delay_pipeline_re[2];
delay_pipeline_re[4] <= delay_pipeline_re[3];
delay_pipeline_re[5] <= delay_pipeline_re[4];
delay_pipeline_im[0] <= FIR_Interpolation_in_im;
delay_pipeline_im[1] <= delay_pipeline_im[0];
delay_pipeline_im[2] <= delay_pipeline_im[1];
delay_pipeline_im[3] <= delay_pipeline_im[2];
delay_pipeline_im[4] <= delay_pipeline_im[3];
delay_pipeline_im[5] <= delay_pipeline_im[4];
end
end
end // Delay_Pipeline_process
assign product_mux = (cur_count == 3'b000) ? coeffphase1_7 :
(cur_count == 3'b001) ? coeffphase2_7 :
(cur_count == 3'b010) ? coeffphase3_7 :
(cur_count == 3'b011) ? coeffphase4_7 :
(cur_count == 3'b100) ? coeffphase5_7 :
(cur_count == 3'b101) ? coeffphase6_7 :
(cur_count == 3'b110) ? coeffphase7_7 :
coeffphase8_7;
assign mul_temp = delay_pipeline_re[5] * product_mux;
assign product_re = mul_temp[31:16];
assign mul_temp_1 = delay_pipeline_im[5] * product_mux;
assign product_im = mul_temp_1[31:16];
assign product_mux_1 = (cur_count == 3'b000) ? coeffphase1_6 :
(cur_count == 3'b001) ? coeffphase2_6 :
(cur_count == 3'b010) ? coeffphase3_6 :
(cur_count == 3'b011) ? coeffphase4_6 :
(cur_count == 3'b100) ? coeffphase5_6 :
(cur_count == 3'b101) ? coeffphase6_6 :
(cur_count == 3'b110) ? coeffphase7_6 :
coeffphase8_6;
assign mul_temp_2 = delay_pipeline_re[4] * product_mux_1;
assign product_1_re = mul_temp_2[31:16];
assign mul_temp_3 = delay_pipeline_im[4] * product_mux_1;
assign product_1_im = mul_temp_3[31:16];
assign product_mux_2 = (cur_count == 3'b000) ? coeffphase1_5 :
(cur_count == 3'b001) ? coeffphase2_5 :
(cur_count == 3'b010) ? coeffphase3_5 :
(cur_count == 3'b011) ? coeffphase4_5 :
(cur_count == 3'b100) ? coeffphase5_5 :
(cur_count == 3'b101) ? coeffphase6_5 :
(cur_count == 3'b110) ? coeffphase7_5 :
coeffphase8_5;
assign mul_temp_4 = delay_pipeline_re[3] * product_mux_2;
assign product_2_re = mul_temp_4[31:16];
assign mul_temp_5 = delay_pipeline_im[3] * product_mux_2;
assign product_2_im = mul_temp_5[31:16];
assign product_mux_3 = (cur_count == 3'b000) ? coeffphase1_4 :
(cur_count == 3'b001) ? coeffphase2_4 :
(cur_count == 3'b010) ? coeffphase3_4 :
(cur_count == 3'b011) ? coeffphase4_4 :
(cur_count == 3'b100) ? coeffphase5_4 :
(cur_count == 3'b101) ? coeffphase6_4 :
(cur_count == 3'b110) ? coeffphase7_4 :
coeffphase8_4;
assign mul_temp_6 = delay_pipeline_re[2] * product_mux_3;
assign product_3_re = mul_temp_6[31:16];
assign mul_temp_7 = delay_pipeline_im[2] * product_mux_3;
assign product_3_im = mul_temp_7[31:16];
assign product_mux_4 = (cur_count == 3'b000) ? coeffphase1_3 :
(cur_count == 3'b001) ? coeffphase2_3 :
(cur_count == 3'b010) ? coeffphase3_3 :
(cur_count == 3'b011) ? coeffphase4_3 :
(cur_count == 3'b100) ? coeffphase5_3 :
(cur_count == 3'b101) ? coeffphase6_3 :
(cur_count == 3'b110) ? coeffphase7_3 :
coeffphase8_3;
assign mul_temp_8 = delay_pipeline_re[1] * product_mux_4;
assign product_4_re = mul_temp_8[31:16];
assign mul_temp_9 = delay_pipeline_im[1] * product_mux_4;
assign product_4_im = mul_temp_9[31:16];
assign product_mux_5 = (cur_count == 3'b000) ? coeffphase1_2 :
(cur_count == 3'b001) ? coeffphase2_2 :
(cur_count == 3'b010) ? coeffphase3_2 :
(cur_count == 3'b011) ? coeffphase4_2 :
(cur_count == 3'b100) ? coeffphase5_2 :
(cur_count == 3'b101) ? coeffphase6_2 :
(cur_count == 3'b110) ? coeffphase7_2 :
coeffphase8_2;
assign mul_temp_10 = delay_pipeline_re[0] * product_mux_5;
assign product_5_re = mul_temp_10[31:16];
assign mul_temp_11 = delay_pipeline_im[0] * product_mux_5;
assign product_5_im = mul_temp_11[31:16];
assign product_mux_6 = (cur_count == 3'b000) ? coeffphase1_1 :
(cur_count == 3'b001) ? coeffphase2_1 :
(cur_count == 3'b010) ? coeffphase3_1 :
(cur_count == 3'b011) ? coeffphase4_1 :
(cur_count == 3'b100) ? coeffphase5_1 :
(cur_count == 3'b101) ? coeffphase6_1 :
(cur_count == 3'b110) ? coeffphase7_1 :
coeffphase8_1;
assign mul_temp_12 = FIR_Interpolation_in_re * product_mux_6;
assign product_6_re = mul_temp_12[31:16];
assign mul_temp_13 = FIR_Interpolation_in_im * product_mux_6;
assign product_6_im = mul_temp_13[31:16];
assign add_cast = product_6_re;
assign add_cast_1 = product_5_re;
assign add_temp = add_cast + add_cast_1;
assign sum1_re = add_temp[15:0];
assign add_cast_2 = product_6_im;
assign add_cast_3 = product_5_im;
assign add_temp_1 = add_cast_2 + add_cast_3;
assign sum1_im = add_temp_1[15:0];
assign add_cast_4 = sum1_re;
assign add_cast_5 = product_4_re;
assign add_temp_2 = add_cast_4 + add_cast_5;
assign sum2_re = add_temp_2[15:0];
assign add_cast_6 = sum1_im;
assign add_cast_7 = product_4_im;
assign add_temp_3 = add_cast_6 + add_cast_7;
assign sum2_im = add_temp_3[15:0];
assign add_cast_8 = sum2_re;
assign add_cast_9 = product_3_re;
assign add_temp_4 = add_cast_8 + add_cast_9;
assign sum3_re = add_temp_4[15:0];
assign add_cast_10 = sum2_im;
assign add_cast_11 = product_3_im;
assign add_temp_5 = add_cast_10 + add_cast_11;
assign sum3_im = add_temp_5[15:0];
assign add_cast_12 = sum3_re;
assign add_cast_13 = product_2_re;
assign add_temp_6 = add_cast_12 + add_cast_13;
assign sum4_re = add_temp_6[15:0];
assign add_cast_14 = sum3_im;
assign add_cast_15 = product_2_im;
assign add_temp_7 = add_cast_14 + add_cast_15;
assign sum4_im = add_temp_7[15:0];
assign add_cast_16 = sum4_re;
assign add_cast_17 = product_1_re;
assign add_temp_8 = add_cast_16 + add_cast_17;
assign sum5_re = add_temp_8[15:0];
assign add_cast_18 = sum4_im;
assign add_cast_19 = product_1_im;
assign add_temp_9 = add_cast_18 + add_cast_19;
assign sum5_im = add_temp_9[15:0];
assign add_cast_20 = sum5_re;
assign add_cast_21 = product_re;
assign add_temp_10 = add_cast_20 + add_cast_21;
assign sum6_re = add_temp_10[15:0];
assign add_cast_22 = sum5_im;
assign add_cast_23 = product_im;
assign add_temp_11 = add_cast_22 + add_cast_23;
assign sum6_im = add_temp_11[15:0];
always @ (posedge clk or posedge reset)
begin: DataHoldRegister_process
if (reset == 1'b1) begin
regout_re <= 0;
regout_im <= 0;
end
else begin
if (enb_1_1_1 == 1'b1) begin
regout_re <= sum6_re;
regout_im <= sum6_im;
end
end
end // DataHoldRegister_process
assign muxout_re = (enb_1_1_1 == 1'b1) ? sum6_re :
regout_re;
assign muxout_im = (enb_1_1_1 == 1'b1) ? sum6_im :
regout_im;
// Assignment Statements
assign FIR_Interpolation_out_re = muxout_re;
assign FIR_Interpolation_out_im = muxout_im;
endmodule // FIR_Interpolation

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// -------------------------------------------------------------
//
// File Name: hdlsrc\qpskhdltest\QPSK_Demodulator_Baseband.v
// Created: 2014-04-21 15:30:34
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: QPSK_Demodulator_Baseband
// Source Path: qpskhdltest/QPSK Demodulator Baseband
// Hierarchy Level: 0
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module QPSK_Demodulator_Baseband
(
in0_re,
in0_im,
out0
);
input signed [15:0] in0_re; // sfix16_En15
input signed [15:0] in0_im; // sfix16_En15
output [1:0] out0; // ufix2
wire inphase_lt_zero;
wire inphase_eq_zero;
wire quadrature_lt_zero;
wire quadrature_eq_zero;
wire [3:0] decisionLUTaddr; // ufix4
wire [1:0] DirectLookupTable_1 [0:15]; // ufix2 [16]
wire [1:0] hardDecision; // ufix2
assign inphase_lt_zero = (in0_re < 16'sb0000000000000000 ? 1'b1 :
1'b0);
assign inphase_eq_zero = (in0_re == 16'sb0000000000000000 ? 1'b1 :
1'b0);
assign quadrature_lt_zero = (in0_im < 16'sb0000000000000000 ? 1'b1 :
1'b0);
assign quadrature_eq_zero = (in0_im == 16'sb0000000000000000 ? 1'b1 :
1'b0);
assign decisionLUTaddr = {inphase_lt_zero, inphase_eq_zero, quadrature_lt_zero, quadrature_eq_zero};
assign DirectLookupTable_1[0] = 2'b00;
assign DirectLookupTable_1[1] = 2'b00;
assign DirectLookupTable_1[2] = 2'b10;
assign DirectLookupTable_1[3] = 2'b00;
assign DirectLookupTable_1[4] = 2'b01;
assign DirectLookupTable_1[5] = 2'b00;
assign DirectLookupTable_1[6] = 2'b10;
assign DirectLookupTable_1[7] = 2'b00;
assign DirectLookupTable_1[8] = 2'b01;
assign DirectLookupTable_1[9] = 2'b11;
assign DirectLookupTable_1[10] = 2'b11;
assign DirectLookupTable_1[11] = 2'b00;
assign DirectLookupTable_1[12] = 2'b00;
assign DirectLookupTable_1[13] = 2'b00;
assign DirectLookupTable_1[14] = 2'b00;
assign DirectLookupTable_1[15] = 2'b00;
assign hardDecision = DirectLookupTable_1[decisionLUTaddr];
assign out0 = hardDecision;
endmodule // QPSK_Demodulator_Baseband

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// -------------------------------------------------------------
//
// File Name: hdlsrc\qpskhdltest\QPSK_Modulator.v
// Created: 2014-04-21 15:30:34
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: QPSK_Modulator
// Source Path: qpskhdltest/QPSK Modulator
// Hierarchy Level: 0
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module QPSK_Modulator
(
in0,
out0_re,
out0_im
);
input [1:0] in0; // ufix2
output signed [15:0] out0_re; // sfix16_En15
output signed [15:0] out0_im; // sfix16_En15
parameter signed [15:0] t1_re_0 = 23170; // sfix16
parameter signed [15:0] t1_re_1 = -23170; // sfix16
parameter signed [15:0] t1_re_2 = -23170; // sfix16
parameter signed [15:0] t1_re_3 = 23170; // sfix16
parameter signed [15:0] t1_im_0 = 23170; // sfix16
parameter signed [15:0] t1_im_1 = 23170; // sfix16
parameter signed [15:0] t1_im_2 = -23170; // sfix16
parameter signed [15:0] t1_im_3 = -23170; // sfix16
wire [1:0] constellationLUTaddress; // ufix2
wire signed [15:0] constellationLUT_t1_re [0:3]; // sfix16_En15 [4]
wire signed [15:0] constellationLUT_t1_im [0:3]; // sfix16_En15 [4]
assign constellationLUTaddress = in0;
assign constellationLUT_t1_re[0] = t1_re_0;
assign constellationLUT_t1_re[1] = t1_re_1;
assign constellationLUT_t1_re[2] = t1_re_2;
assign constellationLUT_t1_re[3] = t1_re_3;
assign constellationLUT_t1_im[0] = t1_im_0;
assign constellationLUT_t1_im[1] = t1_im_1;
assign constellationLUT_t1_im[2] = t1_im_2;
assign constellationLUT_t1_im[3] = t1_im_3;
assign out0_re = constellationLUT_t1_re[constellationLUTaddress];
assign out0_im = constellationLUT_t1_im[constellationLUTaddress];
endmodule // QPSK_Modulator

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// -------------------------------------------------------------
//
// File Name: hdlsrc\qpskhdltest\Raised_Cosine_Rx_Filter.v
// Created: 2014-04-21 15:30:32
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: Raised_Cosine_Rx_Filter
// Source Path: qpskhdltest/Raised Cosine Rx Filter
// Hierarchy Level: 0
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module Raised_Cosine_Rx_Filter
(
clk,
reset,
enb_1_1_1,
In1_re,
In1_im,
Out1_re,
Out1_im
);
input clk;
input reset;
input enb_1_1_1;
input signed [15:0] In1_re; // sfix16_En15
input signed [15:0] In1_im; // sfix16_En15
output signed [15:0] Out1_re; // sfix16_En15
output signed [15:0] Out1_im; // sfix16_En15
wire signed [15:0] FIR_Decimation_out1_re; // sfix16_En15
wire signed [15:0] FIR_Decimation_out1_im; // sfix16_En15
FIR_Decimation u_FIR_Decimation (.clk(clk),
.enb_1_1_1(enb_1_1_1),
.reset(reset),
.FIR_Decimation_in_re(In1_re), // sfix16_En15
.FIR_Decimation_in_im(In1_im), // sfix16_En15
.FIR_Decimation_out_re(FIR_Decimation_out1_re), // sfix16_En15
.FIR_Decimation_out_im(FIR_Decimation_out1_im) // sfix16_En15
);
assign Out1_re = FIR_Decimation_out1_re;
assign Out1_im = FIR_Decimation_out1_im;
endmodule // Raised_Cosine_Rx_Filter

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// -------------------------------------------------------------
//
// File Name: hdlsrc\qpskhdltest\Raised_Cosine_Tx_Filter.v
// Created: 2014-04-21 15:30:34
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: Raised_Cosine_Tx_Filter
// Source Path: qpskhdltest/Raised Cosine Tx Filter
// Hierarchy Level: 0
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module Raised_Cosine_Tx_Filter
(
clk,
reset,
enb_1_1_1,
In1_re,
In1_im,
Out1_re,
Out1_im
);
input clk;
input reset;
input enb_1_1_1;
input signed [15:0] In1_re; // sfix16_En15
input signed [15:0] In1_im; // sfix16_En15
output signed [15:0] Out1_re; // sfix16_En15
output signed [15:0] Out1_im; // sfix16_En15
wire signed [15:0] FIR_Interpolation_out1_re; // sfix16_En15
wire signed [15:0] FIR_Interpolation_out1_im; // sfix16_En15
FIR_Interpolation u_FIR_Interpolation (.clk(clk),
.enb_1_1_1(enb_1_1_1),
.reset(reset),
.FIR_Interpolation_in_re(In1_re), // sfix16_En15
.FIR_Interpolation_in_im(In1_im), // sfix16_En15
.FIR_Interpolation_out_re(FIR_Interpolation_out1_re), // sfix16_En15
.FIR_Interpolation_out_im(FIR_Interpolation_out1_im) // sfix16_En15
);
assign Out1_re = FIR_Interpolation_out1_re;
assign Out1_im = FIR_Interpolation_out1_im;
endmodule // Raised_Cosine_Tx_Filter

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// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ns
module prcfg_adc (
clk,
// control ports
control,
status,
// FIFO interface
src_adc_dwr,
src_adc_dsync,
src_adc_ddata,
src_adc_dovf,
dst_adc_dwr,
dst_adc_dsync,
dst_adc_ddata,
dst_adc_dovf
);
localparam RP_ID = 8'hA2;
parameter CHANNEL_ID = 0;
input clk;
input [31:0] control;
output [31:0] status;
input src_adc_dwr;
input src_adc_dsync;
input [31:0] src_adc_ddata;
output src_adc_dovf;
output dst_adc_dwr;
output dst_adc_dsync;
output [31:0] dst_adc_ddata;
input dst_adc_dovf;
reg [31:0] dst_adc_ddata = 0;
reg [31:0] status = 0;
reg [ 7:0] adc_pn_data = 0;
reg adc_dvalid_d = 0;
reg [ 1:0] adc_ddata = 0;
reg [ 7:0] adc_pn_oos_count = 0;
reg adc_pn_oos = 0;
reg adc_pn_err = 0;
wire [ 3:0] mode;
wire [ 3:0] channel_sel;
wire adc_dvalid;
wire [ 1:0] adc_ddata_s;
wire [31:0] adc_pn_data_s;
wire adc_pn_update_s;
wire adc_pn_match_s;
wire adc_pn_err_s;
// prbs function
function [ 7:0] pn;
input [ 7:0] din;
reg [ 7:0] dout;
begin
dout[7] = din[6];
dout[6] = din[5];
dout[5] = din[4];
dout[4] = din[3];
dout[3] = din[2];
dout[2] = din[1];
dout[1] = din[8] ^ din[4];
dout[0] = din[7] ^ din[3];
pn = dout;
end
endfunction
assign channel_sel = control[ 3:0];
assign mode = control[ 7:4];
assign adc_dvalid = src_adc_dwr & src_adc_dsync;
// prbs monitor
assign adc_pn_data_s = (adc_pn_oos == 1'b1) ? {adc_pn_data[7:2], src_adc_ddata} : adc_pn_data;
assign adc_pn_update_s = ~(adc_pn_oos ^ adc_pn_match_s);
assign adc_pn_match_s = (adc_ddata == adc_pn_data[1:0]) ? 1'b1 : 1'b0;
assign adc_pn_err_s = ~(adc_pn_oos | adc_pn_match_s);
always @(posedge clk) begin
if(adc_dvalid == 1'b1) begin
adc_ddata <= src_adc_ddata;
adc_pn_data <= pn(adc_pn_data_s);
end
adc_dvalid_d <= adc_dvalid;
if(adc_dvalid_d == 1'b1) begin
adc_pn_err <= adc_pn_err_s;
if(adc_pn_update_s == 1'b1) begin
if(adc_pn_oos_count >= 'd16) begin
adc_pn_oos_count <= 'd0;
adc_pn_oos <= ~adc_pn_oos;
end else begin
adc_pn_oos_count <= adc_pn_oos_count + 1;
adc_pn_oos <= adc_pn_oos;
end
end else begin
adc_pn_oos_count <= 'd0;
adc_pn_oos <= adc_pn_oos;
end
end
end
// qpsk demodulator
qpsk_demod i_qpsk_demod1 (
.clk(clk),
.data_qpsk_i(src_adc_ddata[15: 0]),
.data_qpsk_q(src_adc_ddata[31:16]),
.data_valid(adc_dvalid),
.data_output(adc_ddata_s)
);
// output logic for rx side
assign src_adc_dovf = dst_adc_dovf;
assign dst_adc_dwr = src_adc_dwr;
assign dst_adc_dsync = src_adc_dsync;
// output logic for data ans status
always @(posedge clk) begin
if(mode == 0) begin
dst_adc_ddata <= src_adc_ddata;
end else begin
dst_adc_ddata <= {30'h0, adc_ddata};
end
if((mode == 3'd2) && (channel_sel == CHANNEL_ID)) begin
status <= {22'h0, adc_pn_err, adc_pn_oos, RP_ID};
end else begin
status <= {24'h0, RP_ID};
end
end
endmodule

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// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ns
module prcfg_dac(
clk,
// control ports
control,
status,
// FIFO interface
src_dac_drd,
src_dac_ddata,
src_dac_dunf,
dst_dac_drd,
dst_dac_ddata,
dst_dac_dunf
);
localparam RP_ID = 8'hA2;
parameter CHANNEL_ID = 0;
input clk;
input [31:0] control;
output [31:0] status;
output src_dac_drd;
input [31:0] src_dac_ddata;
input src_dac_dunf;
input dst_dac_drd;
output [31:0] dst_dac_ddata;
output dst_dac_dunf;
reg dst_dac_dunf = 0;
reg [31:0] dst_dac_ddata = 0;
reg dst_dac_dvalid = 0;
reg src_dac_drd = 0;
reg [ 1:0] pn_data = 0;
wire [ 1:0] dac_data;
wire [15:0] dac_data_fltr_i;
wire [15:0] dac_data_fltr_q;
wire [ 3:0] mode;
wire [31:0] dac_data_mode0;
wire [31:0] dac_data_mode1_2;
// prbs function
function [ 7:0] pn;
input [ 7:0] din;
reg [ 7:0] dout;
begin
dout[7] = din[6];
dout[6] = din[5];
dout[5] = din[4];
dout[4] = din[3];
dout[3] = din[2];
dout[2] = din[1];
dout[1] = din[8] ^ din[4];
dout[0] = din[7] ^ din[3];
pn = dout;
end
endfunction
assign status = { 24'h0, RP_ID };
assign mode = control[ 7:4];
// pass through mode
assign dac_data_mode0 = src_dac_ddata;
// prbs geenration
always @(posedge clk) begin
if(dst_dac_drd == 1) begin
pn_data = pn(pn_data);
end
end
// data source for the modulator
assign dac_data = (mode == 1) ? pn_data : src_dac_ddata[ 1: 0];
// modulated data
assign dac_data_mode1_2 = { dac_data_fltr_q, dac_data_fltr_i };
// qpsk modulator
qpsk_mod i_qpsk_mod (
.clk(clk),
.data_input(dac_data),
.data_valid(dst_dac_drd),
.data_qpsk_i(dac_data_fltr_i),
.data_qpsk_q(dac_data_fltr_q)
);
// output logic for tx side
always @(posedge clk) begin
src_dac_drd <= (mode == 1) ? 1'b0 : dst_dac_drd;
dst_dac_dunf <= (mode == 1) ? 1'b0 : src_dac_dunf;
dst_dac_ddata <= (mode == 0) ? dac_data_mode0 : dac_data_mode1_2;
end
endmodule

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// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ns
module qpsk_demod (
clk,
data_qpsk_i,
data_qpsk_q,
data_valid,
data_output
);
input clk;
input [15:0] data_qpsk_i;
input [15:0] data_qpsk_q;
input data_valid;
output [ 1:0] data_output;
wire [15:0] filtered_data_i;
wire [15:0] filtered_data_q;
wire [ 1:0] demodulated_data;
// output logic
assign data_output = demodulated_data;
// instantiation
Raised_Cosine_Rx_Filter i_rx_filter (
.clk(clk),
.reset(),
.enb_1_1_1(data_valid),
.In1_re(data_qpsk_i),
.In1_im(data_qpsk_q),
.Out1_im(filtered_data_i),
.Out1_re(filtered_data_q)
);
QPSK_Demodulator_Baseband i_qpsk_demod(
.in0_re(filtered_data_i),
.in0_im(filtered_data_q),
.out0(demodulated_data)
);
endmodule

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// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ns
module qpsk_mod (
clk,
data_input,
data_valid,
data_qpsk_i,
data_qpsk_q
);
input clk;
input [ 1:0] data_input;
input data_valid;
output [15:0] data_qpsk_i;
output [15:0] data_qpsk_q;
wire [15:0] modulated_data_i;
wire [15:0] modulated_data_q;
wire [15:0] filtered_data_i;
wire [15:0] filtered_data_q;
// output logic
assign data_qpsk_i = filtered_data_i;
assign data_qpsk_q = filtered_data_q;
// instantiations
QPSK_Modulator i_qpsk_mod (
.in0(data_input),
.out0_re(modulated_data_i),
.out0_im(modulated_data_q)
);
Raised_Cosine_Tx_Filter i_tx_filter (
.clk(clk),
.reset(),
.enb_1_1_1(data_valid),
.In1_re(modulated_data_i),
.In1_im(modulated_data_q),
.Out1_re(filtered_data_i),
.Out1_im(filtered_data_q)
);
endmodule