prcfg: Upgrade the QPSK logic
Regenerate the qpsk logic, with the new HDL coder, and modify the design to support the new files.main
Istvan Csomortani
parent
16cdae3001
commit
ea194755e1
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@ -1,24 +1,24 @@
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// -------------------------------------------------------------
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//
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// File Name: hdlsrc\qpskhdltest\QPSK_Modulator.v
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// Created: 2014-04-21 15:30:34
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// File Name: hdlsrc\qpsk\QPSK_Modulator_Baseband.v
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// Created: 2014-10-24 12:50:40
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//
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// Generated by MATLAB 8.2 and HDL Coder 3.3
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// Generated by MATLAB 8.3 and HDL Coder 3.4
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//
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// -------------------------------------------------------------
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// -------------------------------------------------------------
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//
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// Module: QPSK_Modulator
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// Source Path: qpskhdltest/QPSK Modulator
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// Hierarchy Level: 0
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// Module: QPSK_Modulator_Baseband
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// Source Path: qpsk/Subsystem/QPSK Modulator Baseband
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// Hierarchy Level: 1
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//
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// -------------------------------------------------------------
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`timescale 1 ns / 1 ns
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module QPSK_Modulator
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module QPSK_Modulator_Baseband
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(
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in0,
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out0_re,
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@ -26,14 +26,14 @@ module QPSK_Modulator
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);
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input [1:0] in0; // ufix2
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input [7:0] in0; // uint8
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output signed [15:0] out0_re; // sfix16_En15
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output signed [15:0] out0_im; // sfix16_En15
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parameter signed [15:0] t1_re_0 = 23170; // sfix16
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parameter signed [15:0] t1_re_1 = -23170; // sfix16
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parameter signed [15:0] t1_re_2 = -23170; // sfix16
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parameter signed [15:0] t1_re_3 = 23170; // sfix16
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parameter signed [15:0] t1_re_2 = 23170; // sfix16
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parameter signed [15:0] t1_re_3 = -23170; // sfix16
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parameter signed [15:0] t1_im_0 = 23170; // sfix16
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parameter signed [15:0] t1_im_1 = 23170; // sfix16
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parameter signed [15:0] t1_im_2 = -23170; // sfix16
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@ -44,7 +44,7 @@ module QPSK_Modulator
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wire signed [15:0] constellationLUT_t1_im [0:3]; // sfix16_En15 [4]
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assign constellationLUTaddress = in0;
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assign constellationLUTaddress = in0[1:0];
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@ -61,5 +61,5 @@ module QPSK_Modulator
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endmodule // QPSK_Modulator
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endmodule // QPSK_Modulator_Baseband
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@ -1,24 +1,24 @@
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// -------------------------------------------------------------
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//
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// File Name: hdlsrc\qpskhdltest\Raised_Cosine_Rx_Filter.v
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// Created: 2014-04-21 15:30:32
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// File Name: hdlsrc\qpsk\Raised_Cosine_Receive_Filter.v
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// Created: 2014-10-24 12:50:39
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//
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// Generated by MATLAB 8.2 and HDL Coder 3.3
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// Generated by MATLAB 8.3 and HDL Coder 3.4
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//
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// -------------------------------------------------------------
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// -------------------------------------------------------------
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//
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// Module: Raised_Cosine_Rx_Filter
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// Source Path: qpskhdltest/Raised Cosine Rx Filter
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// Hierarchy Level: 0
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// Module: Raised_Cosine_Receive_Filter
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// Source Path: qpsk/Subsystem/Raised Cosine Receive Filter
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// Hierarchy Level: 1
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//
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// -------------------------------------------------------------
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`timescale 1 ns / 1 ns
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module Raised_Cosine_Rx_Filter
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module Raised_Cosine_Receive_Filter
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(
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clk,
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reset,
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@ -56,5 +56,5 @@ module Raised_Cosine_Rx_Filter
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assign Out1_im = FIR_Decimation_out1_im;
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endmodule // Raised_Cosine_Rx_Filter
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endmodule // Raised_Cosine_Receive_Filter
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@ -1,24 +1,24 @@
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// -------------------------------------------------------------
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//
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// File Name: hdlsrc\qpskhdltest\Raised_Cosine_Tx_Filter.v
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// Created: 2014-04-21 15:30:34
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// File Name: hdlsrc\qpsk\Raised_Cosine_Transmit_Filter.v
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// Created: 2014-10-24 12:50:40
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//
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// Generated by MATLAB 8.2 and HDL Coder 3.3
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// Generated by MATLAB 8.3 and HDL Coder 3.4
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//
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// -------------------------------------------------------------
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// -------------------------------------------------------------
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//
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// Module: Raised_Cosine_Tx_Filter
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// Source Path: qpskhdltest/Raised Cosine Tx Filter
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// Hierarchy Level: 0
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// Module: Raised_Cosine_Transmit_Filter
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// Source Path: qpsk/Subsystem/Raised Cosine Transmit Filter
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// Hierarchy Level: 1
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//
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// -------------------------------------------------------------
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`timescale 1 ns / 1 ns
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module Raised_Cosine_Tx_Filter
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module Raised_Cosine_Transmit_Filter
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(
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clk,
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reset,
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@ -56,5 +56,5 @@ module Raised_Cosine_Tx_Filter
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assign Out1_im = FIR_Interpolation_out1_im;
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endmodule // Raised_Cosine_Tx_Filter
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endmodule // Raised_Cosine_Transmit_Filter
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@ -54,15 +54,15 @@ module qpsk_demod (
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wire [15:0] filtered_data_i;
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wire [15:0] filtered_data_q;
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wire [ 1:0] demodulated_data;
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wire [ 7:0] demodulated_data;
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// output logic
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assign data_output = demodulated_data;
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assign data_output = demodulated_data[1:0];
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// instantiation
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Raised_Cosine_Rx_Filter i_rx_filter (
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Raised_Cosine_Receive_Filter i_rx_filter (
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.clk(clk),
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.reset(),
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.reset(1'b0),
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.enb_1_1_1(data_valid),
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.In1_re(data_qpsk_i),
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.In1_im(data_qpsk_q),
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@ -62,13 +62,13 @@ module qpsk_mod (
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assign data_qpsk_q = filtered_data_q;
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// instantiations
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QPSK_Modulator i_qpsk_mod (
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.in0(data_input),
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QPSK_Modulator_Baseband i_qpsk_mod (
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.in0({6'b0, data_input}),
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.out0_re(modulated_data_i),
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.out0_im(modulated_data_q)
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);
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Raised_Cosine_Tx_Filter i_tx_filter (
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Raised_Cosine_Transmit_Filter i_tx_filter (
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.clk(clk),
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.reset(),
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.enb_1_1_1(data_valid),
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@ -56,12 +56,12 @@ if { $runSynth == 1 } {
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"${ad_hdl_dir}/library/prcfg/${prcfg_name}/prcfg_adc.v" \
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"${ad_hdl_dir}/library/prcfg/${prcfg_name}/qpsk_mod.v" \
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"${ad_hdl_dir}/library/prcfg/${prcfg_name}/qpsk_demod.v" \
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"${ad_hdl_dir}/library/prcfg/${prcfg_name}/QPSK_Modulator.v" \
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"${ad_hdl_dir}/library/prcfg/${prcfg_name}/QPSK_Modulator_Baseband.v" \
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"${ad_hdl_dir}/library/prcfg/${prcfg_name}/QPSK_Demodulator_Baseband.v" \
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"${ad_hdl_dir}/library/prcfg/${prcfg_name}/FIR_Interpolation.v" \
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"${ad_hdl_dir}/library/prcfg/${prcfg_name}/FIR_Decimation.v" \
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"${ad_hdl_dir}/library/prcfg/${prcfg_name}/Raised_Cosine_Tx_Filter.v" \
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"${ad_hdl_dir}/library/prcfg/${prcfg_name}/Raised_Cosine_Rx_Filter.v"]
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"${ad_hdl_dir}/library/prcfg/${prcfg_name}/Raised_Cosine_Transmit_Filter.v" \
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"${ad_hdl_dir}/library/prcfg/${prcfg_name}/Raised_Cosine_Receive_Filter.v"]
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}
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###############################################################################
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