prcfg: Upgrade the QPSK logic

Regenerate the qpsk logic, with the new HDL coder, and modify the design to support the new files.
main
Istvan Csomortani 2014-10-31 11:59:29 +02:00
parent 16cdae3001
commit ea194755e1
6 changed files with 38 additions and 38 deletions

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@ -1,24 +1,24 @@
// ------------------------------------------------------------- // -------------------------------------------------------------
// //
// File Name: hdlsrc\qpskhdltest\QPSK_Modulator.v // File Name: hdlsrc\qpsk\QPSK_Modulator_Baseband.v
// Created: 2014-04-21 15:30:34 // Created: 2014-10-24 12:50:40
// //
// Generated by MATLAB 8.2 and HDL Coder 3.3 // Generated by MATLAB 8.3 and HDL Coder 3.4
// //
// ------------------------------------------------------------- // -------------------------------------------------------------
// ------------------------------------------------------------- // -------------------------------------------------------------
// //
// Module: QPSK_Modulator // Module: QPSK_Modulator_Baseband
// Source Path: qpskhdltest/QPSK Modulator // Source Path: qpsk/Subsystem/QPSK Modulator Baseband
// Hierarchy Level: 0 // Hierarchy Level: 1
// //
// ------------------------------------------------------------- // -------------------------------------------------------------
`timescale 1 ns / 1 ns `timescale 1 ns / 1 ns
module QPSK_Modulator module QPSK_Modulator_Baseband
( (
in0, in0,
out0_re, out0_re,
@ -26,14 +26,14 @@ module QPSK_Modulator
); );
input [1:0] in0; // ufix2 input [7:0] in0; // uint8
output signed [15:0] out0_re; // sfix16_En15 output signed [15:0] out0_re; // sfix16_En15
output signed [15:0] out0_im; // sfix16_En15 output signed [15:0] out0_im; // sfix16_En15
parameter signed [15:0] t1_re_0 = 23170; // sfix16 parameter signed [15:0] t1_re_0 = 23170; // sfix16
parameter signed [15:0] t1_re_1 = -23170; // sfix16 parameter signed [15:0] t1_re_1 = -23170; // sfix16
parameter signed [15:0] t1_re_2 = -23170; // sfix16 parameter signed [15:0] t1_re_2 = 23170; // sfix16
parameter signed [15:0] t1_re_3 = 23170; // sfix16 parameter signed [15:0] t1_re_3 = -23170; // sfix16
parameter signed [15:0] t1_im_0 = 23170; // sfix16 parameter signed [15:0] t1_im_0 = 23170; // sfix16
parameter signed [15:0] t1_im_1 = 23170; // sfix16 parameter signed [15:0] t1_im_1 = 23170; // sfix16
parameter signed [15:0] t1_im_2 = -23170; // sfix16 parameter signed [15:0] t1_im_2 = -23170; // sfix16
@ -44,7 +44,7 @@ module QPSK_Modulator
wire signed [15:0] constellationLUT_t1_im [0:3]; // sfix16_En15 [4] wire signed [15:0] constellationLUT_t1_im [0:3]; // sfix16_En15 [4]
assign constellationLUTaddress = in0; assign constellationLUTaddress = in0[1:0];
@ -61,5 +61,5 @@ module QPSK_Modulator
endmodule // QPSK_Modulator endmodule // QPSK_Modulator_Baseband

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@ -1,24 +1,24 @@
// ------------------------------------------------------------- // -------------------------------------------------------------
// //
// File Name: hdlsrc\qpskhdltest\Raised_Cosine_Rx_Filter.v // File Name: hdlsrc\qpsk\Raised_Cosine_Receive_Filter.v
// Created: 2014-04-21 15:30:32 // Created: 2014-10-24 12:50:39
// //
// Generated by MATLAB 8.2 and HDL Coder 3.3 // Generated by MATLAB 8.3 and HDL Coder 3.4
// //
// ------------------------------------------------------------- // -------------------------------------------------------------
// ------------------------------------------------------------- // -------------------------------------------------------------
// //
// Module: Raised_Cosine_Rx_Filter // Module: Raised_Cosine_Receive_Filter
// Source Path: qpskhdltest/Raised Cosine Rx Filter // Source Path: qpsk/Subsystem/Raised Cosine Receive Filter
// Hierarchy Level: 0 // Hierarchy Level: 1
// //
// ------------------------------------------------------------- // -------------------------------------------------------------
`timescale 1 ns / 1 ns `timescale 1 ns / 1 ns
module Raised_Cosine_Rx_Filter module Raised_Cosine_Receive_Filter
( (
clk, clk,
reset, reset,
@ -56,5 +56,5 @@ module Raised_Cosine_Rx_Filter
assign Out1_im = FIR_Decimation_out1_im; assign Out1_im = FIR_Decimation_out1_im;
endmodule // Raised_Cosine_Rx_Filter endmodule // Raised_Cosine_Receive_Filter

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@ -1,24 +1,24 @@
// ------------------------------------------------------------- // -------------------------------------------------------------
// //
// File Name: hdlsrc\qpskhdltest\Raised_Cosine_Tx_Filter.v // File Name: hdlsrc\qpsk\Raised_Cosine_Transmit_Filter.v
// Created: 2014-04-21 15:30:34 // Created: 2014-10-24 12:50:40
// //
// Generated by MATLAB 8.2 and HDL Coder 3.3 // Generated by MATLAB 8.3 and HDL Coder 3.4
// //
// ------------------------------------------------------------- // -------------------------------------------------------------
// ------------------------------------------------------------- // -------------------------------------------------------------
// //
// Module: Raised_Cosine_Tx_Filter // Module: Raised_Cosine_Transmit_Filter
// Source Path: qpskhdltest/Raised Cosine Tx Filter // Source Path: qpsk/Subsystem/Raised Cosine Transmit Filter
// Hierarchy Level: 0 // Hierarchy Level: 1
// //
// ------------------------------------------------------------- // -------------------------------------------------------------
`timescale 1 ns / 1 ns `timescale 1 ns / 1 ns
module Raised_Cosine_Tx_Filter module Raised_Cosine_Transmit_Filter
( (
clk, clk,
reset, reset,
@ -56,5 +56,5 @@ module Raised_Cosine_Tx_Filter
assign Out1_im = FIR_Interpolation_out1_im; assign Out1_im = FIR_Interpolation_out1_im;
endmodule // Raised_Cosine_Tx_Filter endmodule // Raised_Cosine_Transmit_Filter

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@ -54,15 +54,15 @@ module qpsk_demod (
wire [15:0] filtered_data_i; wire [15:0] filtered_data_i;
wire [15:0] filtered_data_q; wire [15:0] filtered_data_q;
wire [ 1:0] demodulated_data; wire [ 7:0] demodulated_data;
// output logic // output logic
assign data_output = demodulated_data; assign data_output = demodulated_data[1:0];
// instantiation // instantiation
Raised_Cosine_Rx_Filter i_rx_filter ( Raised_Cosine_Receive_Filter i_rx_filter (
.clk(clk), .clk(clk),
.reset(), .reset(1'b0),
.enb_1_1_1(data_valid), .enb_1_1_1(data_valid),
.In1_re(data_qpsk_i), .In1_re(data_qpsk_i),
.In1_im(data_qpsk_q), .In1_im(data_qpsk_q),

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@ -62,13 +62,13 @@ module qpsk_mod (
assign data_qpsk_q = filtered_data_q; assign data_qpsk_q = filtered_data_q;
// instantiations // instantiations
QPSK_Modulator i_qpsk_mod ( QPSK_Modulator_Baseband i_qpsk_mod (
.in0(data_input), .in0({6'b0, data_input}),
.out0_re(modulated_data_i), .out0_re(modulated_data_i),
.out0_im(modulated_data_q) .out0_im(modulated_data_q)
); );
Raised_Cosine_Tx_Filter i_tx_filter ( Raised_Cosine_Transmit_Filter i_tx_filter (
.clk(clk), .clk(clk),
.reset(), .reset(),
.enb_1_1_1(data_valid), .enb_1_1_1(data_valid),

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@ -56,12 +56,12 @@ if { $runSynth == 1 } {
"${ad_hdl_dir}/library/prcfg/${prcfg_name}/prcfg_adc.v" \ "${ad_hdl_dir}/library/prcfg/${prcfg_name}/prcfg_adc.v" \
"${ad_hdl_dir}/library/prcfg/${prcfg_name}/qpsk_mod.v" \ "${ad_hdl_dir}/library/prcfg/${prcfg_name}/qpsk_mod.v" \
"${ad_hdl_dir}/library/prcfg/${prcfg_name}/qpsk_demod.v" \ "${ad_hdl_dir}/library/prcfg/${prcfg_name}/qpsk_demod.v" \
"${ad_hdl_dir}/library/prcfg/${prcfg_name}/QPSK_Modulator.v" \ "${ad_hdl_dir}/library/prcfg/${prcfg_name}/QPSK_Modulator_Baseband.v" \
"${ad_hdl_dir}/library/prcfg/${prcfg_name}/QPSK_Demodulator_Baseband.v" \ "${ad_hdl_dir}/library/prcfg/${prcfg_name}/QPSK_Demodulator_Baseband.v" \
"${ad_hdl_dir}/library/prcfg/${prcfg_name}/FIR_Interpolation.v" \ "${ad_hdl_dir}/library/prcfg/${prcfg_name}/FIR_Interpolation.v" \
"${ad_hdl_dir}/library/prcfg/${prcfg_name}/FIR_Decimation.v" \ "${ad_hdl_dir}/library/prcfg/${prcfg_name}/FIR_Decimation.v" \
"${ad_hdl_dir}/library/prcfg/${prcfg_name}/Raised_Cosine_Tx_Filter.v" \ "${ad_hdl_dir}/library/prcfg/${prcfg_name}/Raised_Cosine_Transmit_Filter.v" \
"${ad_hdl_dir}/library/prcfg/${prcfg_name}/Raised_Cosine_Rx_Filter.v"] "${ad_hdl_dir}/library/prcfg/${prcfg_name}/Raised_Cosine_Receive_Filter.v"]
} }
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