diff --git a/library/xilinx/util_adxcvr/bd/bd.tcl b/library/xilinx/util_adxcvr/bd/bd.tcl index 8355f1e3e..6465308f3 100644 --- a/library/xilinx/util_adxcvr/bd/bd.tcl +++ b/library/xilinx/util_adxcvr/bd/bd.tcl @@ -3,7 +3,8 @@ proc init {cellpath otherInfo} { set ip [get_bd_cells $cellpath] bd::mark_propagate_override $ip " \ - XCVR_TYPE CH_HSPMUX PPF0_CFG RXPI_CFG0 RXPI_CFG1 RTX_BUF_CML_CTRL" + XCVR_TYPE CH_HSPMUX PPF0_CFG RXPI_CFG0 RXPI_CFG1 RTX_BUF_CML_CTRL \ + QPLL_LPF RXCDR_CFG3_GEN2 RXCDR_CFG3_GEN3 RXCDR_CFG3_GEN4 TX_PI_BIASSET" adi_auto_assign_device_spec $cellpath } diff --git a/library/xilinx/util_adxcvr/util_adxcvr.v b/library/xilinx/util_adxcvr/util_adxcvr.v index 9f4875d5f..6c7aaac48 100644 --- a/library/xilinx/util_adxcvr/util_adxcvr.v +++ b/library/xilinx/util_adxcvr/util_adxcvr.v @@ -94,12 +94,21 @@ module util_adxcvr #( parameter [31:0] RX_PMA_CFG = 32'h001e7080, parameter [72:0] RX_CDR_CFG = 72'h0b000023ff10400020, parameter [15:0] RXCDR_CFG0 = 16'b0000000000000010, + parameter [15:0] RXCDR_CFG2 = 16'b0000001001101001, parameter [ 9:0] RXCDR_CFG2_GEN2 = 10'b1001100101, parameter [15:0] RXCDR_CFG2_GEN4 = 16'b0000000010110100, parameter [15:0] RXCDR_CFG3 = 16'b0000000000010010, parameter [ 5:0] RXCDR_CFG3_GEN2 = 6'b011010, parameter [15:0] RXCDR_CFG3_GEN3 = 16'b0000000000010010, parameter [15:0] RXCDR_CFG3_GEN4 = 16'b0000000000100100, + parameter [ 1:0] RX_WIDEMODE_CDR = 2'b00, + parameter [ 0:0] RX_XMODE_SEL = 1'b1, + parameter integer TXDRV_FREQBAND = 0, + parameter [15:0] TXFE_CFG1 = 16'b0110110000000000, + parameter [15:0] TXFE_CFG2 = 16'b0110110000000000, + parameter [15:0] TXFE_CFG3 = 16'b0110110000000000, + parameter [15:0] TXPI_CFG0 = 16'b0000001100000000, + parameter [15:0] TXPI_CFG1 = 16'b0001000000000000, parameter integer RX_LANE_INVERT = 0) ( input up_rstn, @@ -1209,12 +1218,21 @@ module util_adxcvr #( .RX_CDR_CFG (RX_CDR_CFG), .RX_POLARITY ((RX_LANE_INVERT >> 0) & 1), .RXCDR_CFG0 (RXCDR_CFG0), + .RXCDR_CFG2 (RXCDR_CFG2), .RXCDR_CFG2_GEN2 (RXCDR_CFG2_GEN2), .RXCDR_CFG2_GEN4 (RXCDR_CFG2_GEN4), .RXCDR_CFG3 (RXCDR_CFG3), .RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2), .RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3), .RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4), + .RX_WIDEMODE_CDR (RX_WIDEMODE_CDR), + .RX_XMODE_SEL (RX_XMODE_SEL), + .TXDRV_FREQBAND (TXDRV_FREQBAND), + .TXFE_CFG1 (TXFE_CFG1), + .TXFE_CFG2 (TXFE_CFG2), + .TXFE_CFG3 (TXFE_CFG3), + .TXPI_CFG0 (TXPI_CFG0), + .TXPI_CFG1 (TXPI_CFG1), .CH_HSPMUX (CH_HSPMUX), .PREIQ_FREQ_BST (PREIQ_FREQ_BST), .RXPI_CFG0 (RXPI_CFG0), @@ -1330,12 +1348,21 @@ module util_adxcvr #( .RX_CDR_CFG (RX_CDR_CFG), .RX_POLARITY ((RX_LANE_INVERT >> 1) & 1), .RXCDR_CFG0 (RXCDR_CFG0), + .RXCDR_CFG2 (RXCDR_CFG2), .RXCDR_CFG2_GEN2 (RXCDR_CFG2_GEN2), .RXCDR_CFG2_GEN4 (RXCDR_CFG2_GEN4), .RXCDR_CFG3 (RXCDR_CFG3), .RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2), .RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3), .RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4), + .RX_WIDEMODE_CDR (RX_WIDEMODE_CDR), + .RX_XMODE_SEL (RX_XMODE_SEL), + .TXDRV_FREQBAND (TXDRV_FREQBAND), + .TXFE_CFG1 (TXFE_CFG1), + .TXFE_CFG2 (TXFE_CFG2), + .TXFE_CFG3 (TXFE_CFG3), + .TXPI_CFG0 (TXPI_CFG0), + .TXPI_CFG1 (TXPI_CFG1), .CH_HSPMUX (CH_HSPMUX), .PREIQ_FREQ_BST (PREIQ_FREQ_BST), .RXPI_CFG0 (RXPI_CFG0), @@ -1451,12 +1478,21 @@ module util_adxcvr #( .RX_CDR_CFG (RX_CDR_CFG), .RX_POLARITY ((RX_LANE_INVERT >> 2) & 1), .RXCDR_CFG0 (RXCDR_CFG0), + .RXCDR_CFG2 (RXCDR_CFG2), .RXCDR_CFG2_GEN2 (RXCDR_CFG2_GEN2), .RXCDR_CFG2_GEN4 (RXCDR_CFG2_GEN4), .RXCDR_CFG3 (RXCDR_CFG3), .RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2), .RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3), .RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4), + .RX_WIDEMODE_CDR (RX_WIDEMODE_CDR), + .RX_XMODE_SEL (RX_XMODE_SEL), + .TXDRV_FREQBAND (TXDRV_FREQBAND), + .TXFE_CFG1 (TXFE_CFG1), + .TXFE_CFG2 (TXFE_CFG2), + .TXFE_CFG3 (TXFE_CFG3), + .TXPI_CFG0 (TXPI_CFG0), + .TXPI_CFG1 (TXPI_CFG1), .CH_HSPMUX (CH_HSPMUX), .PREIQ_FREQ_BST (PREIQ_FREQ_BST), .RXPI_CFG0 (RXPI_CFG0), @@ -1572,12 +1608,21 @@ module util_adxcvr #( .RX_CDR_CFG (RX_CDR_CFG), .RX_POLARITY ((RX_LANE_INVERT >> 3) & 1), .RXCDR_CFG0 (RXCDR_CFG0), + .RXCDR_CFG2 (RXCDR_CFG2), .RXCDR_CFG2_GEN2 (RXCDR_CFG2_GEN2), .RXCDR_CFG2_GEN4 (RXCDR_CFG2_GEN4), .RXCDR_CFG3 (RXCDR_CFG3), .RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2), .RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3), .RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4), + .RX_WIDEMODE_CDR (RX_WIDEMODE_CDR), + .RX_XMODE_SEL (RX_XMODE_SEL), + .TXDRV_FREQBAND (TXDRV_FREQBAND), + .TXFE_CFG1 (TXFE_CFG1), + .TXFE_CFG2 (TXFE_CFG2), + .TXFE_CFG3 (TXFE_CFG3), + .TXPI_CFG0 (TXPI_CFG0), + .TXPI_CFG1 (TXPI_CFG1), .CH_HSPMUX (CH_HSPMUX), .PREIQ_FREQ_BST (PREIQ_FREQ_BST), .RXPI_CFG0 (RXPI_CFG0), @@ -1742,12 +1787,21 @@ module util_adxcvr #( .RX_CDR_CFG (RX_CDR_CFG), .RX_POLARITY ((RX_LANE_INVERT >> 4) & 1), .RXCDR_CFG0 (RXCDR_CFG0), + .RXCDR_CFG2 (RXCDR_CFG2), .RXCDR_CFG2_GEN2 (RXCDR_CFG2_GEN2), .RXCDR_CFG2_GEN4 (RXCDR_CFG2_GEN4), .RXCDR_CFG3 (RXCDR_CFG3), .RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2), .RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3), .RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4), + .RX_WIDEMODE_CDR (RX_WIDEMODE_CDR), + .RX_XMODE_SEL (RX_XMODE_SEL), + .TXDRV_FREQBAND (TXDRV_FREQBAND), + .TXFE_CFG1 (TXFE_CFG1), + .TXFE_CFG2 (TXFE_CFG2), + .TXFE_CFG3 (TXFE_CFG3), + .TXPI_CFG0 (TXPI_CFG0), + .TXPI_CFG1 (TXPI_CFG1), .CH_HSPMUX (CH_HSPMUX), .PREIQ_FREQ_BST (PREIQ_FREQ_BST), .RXPI_CFG0 (RXPI_CFG0), @@ -1863,12 +1917,21 @@ module util_adxcvr #( .RX_CDR_CFG (RX_CDR_CFG), .RX_POLARITY ((RX_LANE_INVERT >> 5) & 1), .RXCDR_CFG0 (RXCDR_CFG0), + .RXCDR_CFG2 (RXCDR_CFG2), .RXCDR_CFG2_GEN2 (RXCDR_CFG2_GEN2), .RXCDR_CFG2_GEN4 (RXCDR_CFG2_GEN4), .RXCDR_CFG3 (RXCDR_CFG3), .RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2), .RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3), .RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4), + .RX_WIDEMODE_CDR (RX_WIDEMODE_CDR), + .RX_XMODE_SEL (RX_XMODE_SEL), + .TXDRV_FREQBAND (TXDRV_FREQBAND), + .TXFE_CFG1 (TXFE_CFG1), + .TXFE_CFG2 (TXFE_CFG2), + .TXFE_CFG3 (TXFE_CFG3), + .TXPI_CFG0 (TXPI_CFG0), + .TXPI_CFG1 (TXPI_CFG1), .CH_HSPMUX (CH_HSPMUX), .PREIQ_FREQ_BST (PREIQ_FREQ_BST), .RXPI_CFG0 (RXPI_CFG0), @@ -1984,12 +2047,21 @@ module util_adxcvr #( .RX_CDR_CFG (RX_CDR_CFG), .RX_POLARITY ((RX_LANE_INVERT >> 6) & 1), .RXCDR_CFG0 (RXCDR_CFG0), + .RXCDR_CFG2 (RXCDR_CFG2), .RXCDR_CFG2_GEN2 (RXCDR_CFG2_GEN2), .RXCDR_CFG2_GEN4 (RXCDR_CFG2_GEN4), .RXCDR_CFG3 (RXCDR_CFG3), .RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2), .RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3), .RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4), + .RX_WIDEMODE_CDR (RX_WIDEMODE_CDR), + .RX_XMODE_SEL (RX_XMODE_SEL), + .TXDRV_FREQBAND (TXDRV_FREQBAND), + .TXFE_CFG1 (TXFE_CFG1), + .TXFE_CFG2 (TXFE_CFG2), + .TXFE_CFG3 (TXFE_CFG3), + .TXPI_CFG0 (TXPI_CFG0), + .TXPI_CFG1 (TXPI_CFG1), .CH_HSPMUX (CH_HSPMUX), .PREIQ_FREQ_BST (PREIQ_FREQ_BST), .RXPI_CFG0 (RXPI_CFG0), @@ -2105,12 +2177,21 @@ module util_adxcvr #( .RX_CDR_CFG (RX_CDR_CFG), .RX_POLARITY ((RX_LANE_INVERT >> 7) & 1), .RXCDR_CFG0 (RXCDR_CFG0), + .RXCDR_CFG2 (RXCDR_CFG2), .RXCDR_CFG2_GEN2 (RXCDR_CFG2_GEN2), .RXCDR_CFG2_GEN4 (RXCDR_CFG2_GEN4), .RXCDR_CFG3 (RXCDR_CFG3), .RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2), .RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3), .RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4), + .RX_WIDEMODE_CDR (RX_WIDEMODE_CDR), + .RX_XMODE_SEL (RX_XMODE_SEL), + .TXDRV_FREQBAND (TXDRV_FREQBAND), + .TXFE_CFG1 (TXFE_CFG1), + .TXFE_CFG2 (TXFE_CFG2), + .TXFE_CFG3 (TXFE_CFG3), + .TXPI_CFG0 (TXPI_CFG0), + .TXPI_CFG1 (TXPI_CFG1), .CH_HSPMUX (CH_HSPMUX), .PREIQ_FREQ_BST (PREIQ_FREQ_BST), .RXPI_CFG0 (RXPI_CFG0), @@ -2275,12 +2356,21 @@ module util_adxcvr #( .RX_CDR_CFG (RX_CDR_CFG), .RX_POLARITY ((RX_LANE_INVERT >> 8) & 1), .RXCDR_CFG0 (RXCDR_CFG0), + .RXCDR_CFG2 (RXCDR_CFG2), .RXCDR_CFG2_GEN2 (RXCDR_CFG2_GEN2), .RXCDR_CFG2_GEN4 (RXCDR_CFG2_GEN4), .RXCDR_CFG3 (RXCDR_CFG3), .RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2), .RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3), .RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4), + .RX_WIDEMODE_CDR (RX_WIDEMODE_CDR), + .RX_XMODE_SEL (RX_XMODE_SEL), + .TXDRV_FREQBAND (TXDRV_FREQBAND), + .TXFE_CFG1 (TXFE_CFG1), + .TXFE_CFG2 (TXFE_CFG2), + .TXFE_CFG3 (TXFE_CFG3), + .TXPI_CFG0 (TXPI_CFG0), + .TXPI_CFG1 (TXPI_CFG1), .CH_HSPMUX (CH_HSPMUX), .PREIQ_FREQ_BST (PREIQ_FREQ_BST), .RXPI_CFG0 (RXPI_CFG0), @@ -2396,12 +2486,21 @@ module util_adxcvr #( .RX_CDR_CFG (RX_CDR_CFG), .RX_POLARITY ((RX_LANE_INVERT >> 9) & 1), .RXCDR_CFG0 (RXCDR_CFG0), + .RXCDR_CFG2 (RXCDR_CFG2), .RXCDR_CFG2_GEN2 (RXCDR_CFG2_GEN2), .RXCDR_CFG2_GEN4 (RXCDR_CFG2_GEN4), .RXCDR_CFG3 (RXCDR_CFG3), .RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2), .RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3), .RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4), + .RX_WIDEMODE_CDR (RX_WIDEMODE_CDR), + .RX_XMODE_SEL (RX_XMODE_SEL), + .TXDRV_FREQBAND (TXDRV_FREQBAND), + .TXFE_CFG1 (TXFE_CFG1), + .TXFE_CFG2 (TXFE_CFG2), + .TXFE_CFG3 (TXFE_CFG3), + .TXPI_CFG0 (TXPI_CFG0), + .TXPI_CFG1 (TXPI_CFG1), .CH_HSPMUX (CH_HSPMUX), .PREIQ_FREQ_BST (PREIQ_FREQ_BST), .RXPI_CFG0 (RXPI_CFG0), @@ -2517,12 +2616,21 @@ module util_adxcvr #( .RX_CDR_CFG (RX_CDR_CFG), .RX_POLARITY ((RX_LANE_INVERT >> 10) & 1), .RXCDR_CFG0 (RXCDR_CFG0), + .RXCDR_CFG2 (RXCDR_CFG2), .RXCDR_CFG2_GEN2 (RXCDR_CFG2_GEN2), .RXCDR_CFG2_GEN4 (RXCDR_CFG2_GEN4), .RXCDR_CFG3 (RXCDR_CFG3), .RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2), .RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3), .RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4), + .RX_WIDEMODE_CDR (RX_WIDEMODE_CDR), + .RX_XMODE_SEL (RX_XMODE_SEL), + .TXDRV_FREQBAND (TXDRV_FREQBAND), + .TXFE_CFG1 (TXFE_CFG1), + .TXFE_CFG2 (TXFE_CFG2), + .TXFE_CFG3 (TXFE_CFG3), + .TXPI_CFG0 (TXPI_CFG0), + .TXPI_CFG1 (TXPI_CFG1), .CH_HSPMUX (CH_HSPMUX), .PREIQ_FREQ_BST (PREIQ_FREQ_BST), .RXPI_CFG0 (RXPI_CFG0), @@ -2638,12 +2746,21 @@ module util_adxcvr #( .RX_CDR_CFG (RX_CDR_CFG), .RX_POLARITY ((RX_LANE_INVERT >> 11) & 1), .RXCDR_CFG0 (RXCDR_CFG0), + .RXCDR_CFG2 (RXCDR_CFG2), .RXCDR_CFG2_GEN2 (RXCDR_CFG2_GEN2), .RXCDR_CFG2_GEN4 (RXCDR_CFG2_GEN4), .RXCDR_CFG3 (RXCDR_CFG3), .RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2), .RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3), .RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4), + .RX_WIDEMODE_CDR (RX_WIDEMODE_CDR), + .RX_XMODE_SEL (RX_XMODE_SEL), + .TXDRV_FREQBAND (TXDRV_FREQBAND), + .TXFE_CFG1 (TXFE_CFG1), + .TXFE_CFG2 (TXFE_CFG2), + .TXFE_CFG3 (TXFE_CFG3), + .TXPI_CFG0 (TXPI_CFG0), + .TXPI_CFG1 (TXPI_CFG1), .CH_HSPMUX (CH_HSPMUX), .PREIQ_FREQ_BST (PREIQ_FREQ_BST), .RXPI_CFG0 (RXPI_CFG0), @@ -2808,12 +2925,21 @@ module util_adxcvr #( .RX_CDR_CFG (RX_CDR_CFG), .RX_POLARITY ((RX_LANE_INVERT >> 12) & 1), .RXCDR_CFG0 (RXCDR_CFG0), + .RXCDR_CFG2 (RXCDR_CFG2), .RXCDR_CFG2_GEN2 (RXCDR_CFG2_GEN2), .RXCDR_CFG2_GEN4 (RXCDR_CFG2_GEN4), .RXCDR_CFG3 (RXCDR_CFG3), .RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2), .RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3), .RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4), + .RX_WIDEMODE_CDR (RX_WIDEMODE_CDR), + .RX_XMODE_SEL (RX_XMODE_SEL), + .TXDRV_FREQBAND (TXDRV_FREQBAND), + .TXFE_CFG1 (TXFE_CFG1), + .TXFE_CFG2 (TXFE_CFG2), + .TXFE_CFG3 (TXFE_CFG3), + .TXPI_CFG0 (TXPI_CFG0), + .TXPI_CFG1 (TXPI_CFG1), .CH_HSPMUX (CH_HSPMUX), .PREIQ_FREQ_BST (PREIQ_FREQ_BST), .RXPI_CFG0 (RXPI_CFG0), @@ -2929,12 +3055,21 @@ module util_adxcvr #( .RX_CDR_CFG (RX_CDR_CFG), .RX_POLARITY ((RX_LANE_INVERT >> 13) & 1), .RXCDR_CFG0 (RXCDR_CFG0), + .RXCDR_CFG2 (RXCDR_CFG2), .RXCDR_CFG2_GEN2 (RXCDR_CFG2_GEN2), .RXCDR_CFG2_GEN4 (RXCDR_CFG2_GEN4), .RXCDR_CFG3 (RXCDR_CFG3), .RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2), .RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3), .RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4), + .RX_WIDEMODE_CDR (RX_WIDEMODE_CDR), + .RX_XMODE_SEL (RX_XMODE_SEL), + .TXDRV_FREQBAND (TXDRV_FREQBAND), + .TXFE_CFG1 (TXFE_CFG1), + .TXFE_CFG2 (TXFE_CFG2), + .TXFE_CFG3 (TXFE_CFG3), + .TXPI_CFG0 (TXPI_CFG0), + .TXPI_CFG1 (TXPI_CFG1), .CH_HSPMUX (CH_HSPMUX), .PREIQ_FREQ_BST (PREIQ_FREQ_BST), .RXPI_CFG0 (RXPI_CFG0), @@ -3050,12 +3185,21 @@ module util_adxcvr #( .RX_CDR_CFG (RX_CDR_CFG), .RX_POLARITY ((RX_LANE_INVERT >> 14) & 1), .RXCDR_CFG0 (RXCDR_CFG0), + .RXCDR_CFG2 (RXCDR_CFG2), .RXCDR_CFG2_GEN2 (RXCDR_CFG2_GEN2), .RXCDR_CFG2_GEN4 (RXCDR_CFG2_GEN4), .RXCDR_CFG3 (RXCDR_CFG3), .RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2), .RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3), .RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4), + .RX_WIDEMODE_CDR (RX_WIDEMODE_CDR), + .RX_XMODE_SEL (RX_XMODE_SEL), + .TXDRV_FREQBAND (TXDRV_FREQBAND), + .TXFE_CFG1 (TXFE_CFG1), + .TXFE_CFG2 (TXFE_CFG2), + .TXFE_CFG3 (TXFE_CFG3), + .TXPI_CFG0 (TXPI_CFG0), + .TXPI_CFG1 (TXPI_CFG1), .CH_HSPMUX (CH_HSPMUX), .PREIQ_FREQ_BST (PREIQ_FREQ_BST), .RXPI_CFG0 (RXPI_CFG0), @@ -3171,12 +3315,21 @@ module util_adxcvr #( .RX_CDR_CFG (RX_CDR_CFG), .RX_POLARITY ((RX_LANE_INVERT >> 15) & 1), .RXCDR_CFG0 (RXCDR_CFG0), + .RXCDR_CFG2 (RXCDR_CFG2), .RXCDR_CFG2_GEN2 (RXCDR_CFG2_GEN2), .RXCDR_CFG2_GEN4 (RXCDR_CFG2_GEN4), .RXCDR_CFG3 (RXCDR_CFG3), .RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2), .RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3), .RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4), + .RX_WIDEMODE_CDR (RX_WIDEMODE_CDR), + .RX_XMODE_SEL (RX_XMODE_SEL), + .TXDRV_FREQBAND (TXDRV_FREQBAND), + .TXFE_CFG1 (TXFE_CFG1), + .TXFE_CFG2 (TXFE_CFG2), + .TXFE_CFG3 (TXFE_CFG3), + .TXPI_CFG0 (TXPI_CFG0), + .TXPI_CFG1 (TXPI_CFG1), .CH_HSPMUX (CH_HSPMUX), .PREIQ_FREQ_BST (PREIQ_FREQ_BST), .RXPI_CFG0 (RXPI_CFG0), diff --git a/library/xilinx/util_adxcvr/util_adxcvr_ip.tcl b/library/xilinx/util_adxcvr/util_adxcvr_ip.tcl index b31300331..7d4de9b9c 100644 --- a/library/xilinx/util_adxcvr/util_adxcvr_ip.tcl +++ b/library/xilinx/util_adxcvr/util_adxcvr_ip.tcl @@ -838,6 +838,27 @@ set_property -dict [list \ value_tcl_expr {[format "0x%x" [expr {$XCVR_TYPE == 9} ? 0x3 : 0x0]]} \ ] $param +set param [ipx::get_user_parameters QPLL_LPF -of_objects $cc] +set_property -dict [list \ + value_tcl_expr {[format "0x%x" [expr {$XCVR_TYPE == 9} ? 0x37f : 0x137]]} \ +] $param + +set param [ipx::get_user_parameters RXCDR_CFG3_GEN2 -of_objects $cc] +set_property -dict [list \ + value_tcl_expr {[format "0x%x" [expr {$XCVR_TYPE == 9} ? 0x12 : 0x1a ]]} \ +] $param + +set param [ipx::get_user_parameters RXCDR_CFG3_GEN4 -of_objects $cc] +set_property -dict [list \ + value_tcl_expr {[format "0x%x" [expr {$XCVR_TYPE == 9} ? 0x12 : 0x24 ]]} \ +] $param + +set param [ipx::get_user_parameters TX_PI_BIASSET -of_objects $cc] +set_property -dict [list \ + value_tcl_expr {expr {$XCVR_TYPE == 9} ? 0 : 1} \ +] $param + + ipx::create_xgui_files [ipx::current_core] ipx::save_core [ipx::current_core] diff --git a/library/xilinx/util_adxcvr/util_adxcvr_xch.v b/library/xilinx/util_adxcvr/util_adxcvr_xch.v index 2a52d8947..15e0567b3 100644 --- a/library/xilinx/util_adxcvr/util_adxcvr_xch.v +++ b/library/xilinx/util_adxcvr/util_adxcvr_xch.v @@ -68,12 +68,21 @@ module util_adxcvr_xch #( parameter [31:0] RX_PMA_CFG = 32'h001e7080, parameter [72:0] RX_CDR_CFG = 72'h0b000023ff10400020, parameter [15:0] RXCDR_CFG0 = 16'b0000000000000010, + parameter [15:0] RXCDR_CFG2 = 16'b0000001001101001, parameter [ 9:0] RXCDR_CFG2_GEN2 = 10'b1001100101, parameter [15:0] RXCDR_CFG2_GEN4 = 16'b0000000010110100, parameter [15:0] RXCDR_CFG3 = 16'b0000000000010010, parameter [ 5:0] RXCDR_CFG3_GEN2 = 6'b011010, parameter [15:0] RXCDR_CFG3_GEN3 = 16'b0000000000010010, parameter [15:0] RXCDR_CFG3_GEN4 = 16'b0000000000100100, + parameter [ 1:0] RX_WIDEMODE_CDR = 2'b00, + parameter [ 0:0] RX_XMODE_SEL = 1'b1, + parameter integer TXDRV_FREQBAND = 0, + parameter [15:0] TXFE_CFG1 = 16'b0110110000000000, + parameter [15:0] TXFE_CFG2 = 16'b0110110000000000, + parameter [15:0] TXFE_CFG3 = 16'b0110110000000000, + parameter [15:0] TXPI_CFG0 = 16'b0000001100000000, + parameter [15:0] TXPI_CFG1 = 16'b0001000000000000, parameter integer RX_POLARITY = 0) ( // pll interface @@ -2631,14 +2640,14 @@ module util_adxcvr_xch #( .RXCDR_CFG0_GEN3 (16'b0000000000000011), .RXCDR_CFG1 (16'b0000000000000000), .RXCDR_CFG1_GEN3 (16'b0000000000000000), - .RXCDR_CFG2 (16'b0000001001101001), + .RXCDR_CFG2 (RXCDR_CFG2), .RXCDR_CFG2_GEN2 (10'b1001101001), .RXCDR_CFG2_GEN3 (16'b0000001001101001), .RXCDR_CFG2_GEN4 (16'b0000000101100100), .RXCDR_CFG3 (16'b0000000000010010), - .RXCDR_CFG3_GEN2 (6'b010010), - .RXCDR_CFG3_GEN3 (16'b0000000000010010), - .RXCDR_CFG3_GEN4 (16'b0000000000010010), + .RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2), + .RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3), + .RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4), .RXCDR_CFG4 (16'b0101110011110110), .RXCDR_CFG4_GEN3 (16'b0101110011110110), .RXCDR_CFG5 (16'b1011010001101011), @@ -2800,11 +2809,11 @@ module util_adxcvr_xch #( .RX_TUNE_AFE_OS (2'b10), .RX_VREG_CTRL (3'b010), .RX_VREG_PDB (1'b1), - .RX_WIDEMODE_CDR (2'b00), + .RX_WIDEMODE_CDR (RX_WIDEMODE_CDR), .RX_WIDEMODE_CDR_GEN3 (2'b00), .RX_WIDEMODE_CDR_GEN4 (2'b01), .RX_XCLK_SEL ("RXDES"), - .RX_XMODE_SEL (1'b1), + .RX_XMODE_SEL (RX_XMODE_SEL), .SAMPLE_CLK_PHASE (1'b0), .SAS_12G_MODE (1'b0), .SATA_BURST_SEQ_LEN (4'b1111), @@ -2828,11 +2837,11 @@ module util_adxcvr_xch #( .TXBUF_RESET_ON_RATE_CHANGE ("TRUE"), .TXDLY_CFG (16'b1000000000010000), .TXDLY_LCFG (16'b0000000000110000), - .TXDRV_FREQBAND (0), + .TXDRV_FREQBAND (TXDRV_FREQBAND), .TXFE_CFG0 (16'b0000001111000010), - .TXFE_CFG1 (16'b0110110000000000), - .TXFE_CFG2 (16'b0110110000000000), - .TXFE_CFG3 (16'b0110110000000000), + .TXFE_CFG1 (TXFE_CFG1), + .TXFE_CFG2 (TXFE_CFG2), + .TXFE_CFG3 (TXFE_CFG3), .TXFIFO_ADDR_CFG ("LOW"), .TXGBOX_FIFO_INIT_RD_ADDR (4), .TXGEARBOX_EN ("FALSE"), @@ -2843,8 +2852,8 @@ module util_adxcvr_xch #( .TXPH_CFG (16'b0000001100100011), .TXPH_CFG2 (16'b0000000000000000), .TXPH_MONITOR_SEL (5'b00000), - .TXPI_CFG0 (16'b0000001100000000), - .TXPI_CFG1 (16'b0001000000000000), + .TXPI_CFG0 (TXPI_CFG0), + .TXPI_CFG1 (TXPI_CFG1), .TXPI_GRAY_SEL (1'b0), .TXPI_INVSTROBE_SEL (1'b0), .TXPI_PPM (1'b0), @@ -2888,7 +2897,7 @@ module util_adxcvr_xch #( .TX_MARGIN_LOW_4 (7'b1000000), .TX_PHICAL_CFG0 (16'b0000000000100000), .TX_PHICAL_CFG1 (16'b0000000001000000), - .TX_PI_BIASSET (0), + .TX_PI_BIASSET (TX_PI_BIASSET), .TX_PMADATA_OPT (1'b0), .TX_PMA_POWER_SAVE (1'b0), .TX_PMA_RSV0 (16'b0000000000000000), diff --git a/library/xilinx/util_adxcvr/util_adxcvr_xcm.v b/library/xilinx/util_adxcvr/util_adxcvr_xcm.v index ae2fa0380..26f7ac7b2 100644 --- a/library/xilinx/util_adxcvr/util_adxcvr_xcm.v +++ b/library/xilinx/util_adxcvr/util_adxcvr_xcm.v @@ -574,7 +574,7 @@ module util_adxcvr_xcm #( .QPLL0_INIT_CFG1 (8'b00000000), .QPLL0_LOCK_CFG (16'b0010010111101000), .QPLL0_LOCK_CFG_G3 (16'b0010010111101000), - .QPLL0_LPF (10'b1101111111), + .QPLL0_LPF (QPLL_LPF), .QPLL0_LPF_G3 (10'b0111010101), .QPLL0_PCI_EN (1'b0), .QPLL0_RATE_SW_USE_DRP (1'b1),