diff --git a/projects/fmcomms2/common/fmcomms2_bd.qsys b/projects/fmcomms2/common/fmcomms2_bd.qsys
deleted file mode 100755
index d7daaf622..000000000
--- a/projects/fmcomms2/common/fmcomms2_bd.qsys
+++ /dev/null
@@ -1,613 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<system name="$${FILENAME}">
- <component
-   name="$${FILENAME}"
-   displayName="$${FILENAME}"
-   version="1.0"
-   description=""
-   tags=""
-   categories="System" />
- <parameter name="bonusData"><![CDATA[bonusData 
-{
-   element adc_pack
-   {
-      datum _sortIndex
-      {
-         value = "3";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element arradio_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Cyclone V";
-         type = "String";
-      }
-   }
-   element arradio_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Cyclone V";
-         type = "String";
-      }
-   }
-   element arradio_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Cyclone V";
-         type = "String";
-      }
-   }
-   element arradio_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Cyclone V";
-         type = "String";
-      }
-   }
-   element arradio_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Cyclone V";
-         type = "String";
-      }
-   }
-   element arradio_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Cyclone V";
-         type = "String";
-      }
-   }
-   element arradio_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Cyclone V";
-         type = "String";
-      }
-   }
-   element axi_ad9361
-   {
-      datum _sortIndex
-      {
-         value = "2";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element axi_ad9361.s_axi
-   {
-      datum baseAddress
-      {
-         value = "131072";
-         type = "String";
-      }
-   }
-   element axi_dmac_adc
-   {
-      datum _sortIndex
-      {
-         value = "4";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element axi_dmac_adc.s_axi
-   {
-      datum baseAddress
-      {
-         value = "0";
-         type = "String";
-      }
-   }
-   element axi_dmac_dac
-   {
-      datum _sortIndex
-      {
-         value = "6";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element axi_dmac_dac.s_axi
-   {
-      datum baseAddress
-      {
-         value = "16384";
-         type = "String";
-      }
-   }
-   element dac_upack
-   {
-      datum _sortIndex
-      {
-         value = "5";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element sys_clk
-   {
-      datum _sortIndex
-      {
-         value = "0";
-         type = "int";
-      }
-   }
-   element sys_rst
-   {
-      datum _sortIndex
-      {
-         value = "1";
-         type = "int";
-      }
-   }
-}
-]]></parameter>
- <parameter name="clockCrossingAdapter" value="FIFO" />
- <parameter name="device" value="10AS066N3F40E2SGE2" />
- <parameter name="deviceFamily" value="Arria 10" />
- <parameter name="deviceSpeedGrade" value="2" />
- <parameter name="fabricMode" value="QSYS" />
- <parameter name="generateLegacySim" value="false" />
- <parameter name="generationId" value="0" />
- <parameter name="globalResetBus" value="false" />
- <parameter name="hdlLanguage" value="VERILOG" />
- <parameter name="hideFromIPCatalog" value="false" />
- <parameter name="lockedInterfaceDefinition" value="" />
- <parameter name="maxAdditionalLatency" value="2" />
- <parameter name="projectName" value="" />
- <parameter name="sopcBorderPoints" value="false" />
- <parameter name="systemHash" value="0" />
- <parameter name="testBenchDutName" value="" />
- <parameter name="timeStamp" value="0" />
- <parameter name="useTestBenchNamingPattern" value="false" />
- <instanceScript></instanceScript>
- <interface
-   name="axi_ad9361_delay_clk"
-   internal="axi_ad9361.if_delay_clk"
-   type="clock"
-   dir="end" />
- <interface name="axi_ad9361_device_clock" internal="axi_ad9361.device_clock" />
- <interface
-   name="axi_ad9361_device_if"
-   internal="axi_ad9361.device_if"
-   type="conduit"
-   dir="end" />
- <interface
-   name="axi_ad9361_s_axi"
-   internal="axi_ad9361.s_axi"
-   type="axi4lite"
-   dir="end" />
- <interface
-   name="axi_ad9361_up_enable"
-   internal="axi_ad9361.if_up_enable"
-   type="conduit"
-   dir="end" />
- <interface
-   name="axi_ad9361_up_txnrx"
-   internal="axi_ad9361.if_up_txnrx"
-   type="conduit"
-   dir="end" />
- <interface
-   name="axi_dmac_adc_fifo_wr_clock"
-   internal="axi_dmac_adc.fifo_wr_clock" />
- <interface name="axi_dmac_adc_fifo_wr_if" internal="axi_dmac_adc.fifo_wr_if" />
- <interface
-   name="axi_dmac_adc_intr"
-   internal="axi_dmac_adc.interrupt_sender"
-   type="interrupt"
-   dir="end" />
- <interface
-   name="axi_dmac_adc_m_dest_axi"
-   internal="axi_dmac_adc.m_dest_axi"
-   type="axi4"
-   dir="start" />
- <interface
-   name="axi_dmac_adc_s_axi"
-   internal="axi_dmac_adc.s_axi"
-   type="axi4lite"
-   dir="end" />
- <interface
-   name="axi_dmac_dac_fifo_rd_clock"
-   internal="axi_dmac_dac.fifo_rd_clock" />
- <interface name="axi_dmac_dac_fifo_rd_if" internal="axi_dmac_dac.fifo_rd_if" />
- <interface
-   name="axi_dmac_dac_intr"
-   internal="axi_dmac_dac.interrupt_sender"
-   type="interrupt"
-   dir="end" />
- <interface
-   name="axi_dmac_dac_m_src_axi"
-   internal="axi_dmac_dac.m_src_axi"
-   type="axi4"
-   dir="start" />
- <interface
-   name="axi_dmac_dac_s_axi"
-   internal="axi_dmac_dac.s_axi"
-   type="axi4lite"
-   dir="end" />
- <interface name="sys_clk" internal="sys_clk.in_clk" type="clock" dir="end" />
- <interface name="sys_rst" internal="sys_rst.in_reset" type="reset" dir="end" />
- <module name="adc_pack" kind="util_cpack" version="1.0" enabled="1">
-  <parameter name="CHANNEL_DATA_WIDTH" value="16" />
-  <parameter name="NUM_OF_CHANNELS" value="4" />
- </module>
- <module name="axi_ad9361" kind="axi_ad9361" version="1.0" enabled="1">
-  <parameter name="ADC_DATAPATH_DISABLE" value="0" />
-  <parameter name="CMOS_OR_LVDS_N" value="0" />
-  <parameter name="DAC_DATAPATH_DISABLE" value="0" />
-  <parameter name="DEVICE_FAMILY" value="Arria 10" />
-  <parameter name="DEVICE_TYPE" value="0" />
-  <parameter name="ID" value="0" />
- </module>
- <module name="axi_dmac_adc" kind="axi_dmac" version="1.0" enabled="1">
-  <parameter name="ASYNC_CLK_DEST_REQ" value="1" />
-  <parameter name="ASYNC_CLK_REQ_SRC" value="1" />
-  <parameter name="ASYNC_CLK_SRC_DEST" value="1" />
-  <parameter name="AXI_SLICE_DEST" value="0" />
-  <parameter name="AXI_SLICE_SRC" value="0" />
-  <parameter name="CYCLIC" value="0" />
-  <parameter name="DMA_2D_TRANSFER" value="0" />
-  <parameter name="DMA_DATA_WIDTH_DEST" value="64" />
-  <parameter name="DMA_DATA_WIDTH_SRC" value="64" />
-  <parameter name="DMA_LENGTH_WIDTH" value="24" />
-  <parameter name="DMA_TYPE_DEST" value="0" />
-  <parameter name="DMA_TYPE_SRC" value="2" />
-  <parameter name="FIFO_SIZE" value="4" />
-  <parameter name="ID" value="0" />
-  <parameter name="SYNC_TRANSFER_START" value="1" />
- </module>
- <module name="axi_dmac_dac" kind="axi_dmac" version="1.0" enabled="1">
-  <parameter name="ASYNC_CLK_DEST_REQ" value="1" />
-  <parameter name="ASYNC_CLK_REQ_SRC" value="1" />
-  <parameter name="ASYNC_CLK_SRC_DEST" value="1" />
-  <parameter name="AXI_SLICE_DEST" value="0" />
-  <parameter name="AXI_SLICE_SRC" value="0" />
-  <parameter name="CYCLIC" value="1" />
-  <parameter name="DMA_2D_TRANSFER" value="0" />
-  <parameter name="DMA_DATA_WIDTH_DEST" value="64" />
-  <parameter name="DMA_DATA_WIDTH_SRC" value="64" />
-  <parameter name="DMA_LENGTH_WIDTH" value="24" />
-  <parameter name="DMA_TYPE_DEST" value="2" />
-  <parameter name="DMA_TYPE_SRC" value="0" />
-  <parameter name="FIFO_SIZE" value="4" />
-  <parameter name="ID" value="0" />
-  <parameter name="SYNC_TRANSFER_START" value="0" />
- </module>
- <module name="dac_upack" kind="util_upack" version="1.0" enabled="1">
-  <parameter name="CHANNEL_DATA_WIDTH" value="16" />
-  <parameter name="NUM_OF_CHANNELS" value="4" />
- </module>
- <module name="sys_clk" kind="altera_clock_bridge" version="15.1" enabled="1">
-  <parameter name="DERIVED_CLOCK_RATE" value="0" />
-  <parameter name="EXPLICIT_CLOCK_RATE" value="50000000" />
-  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
- </module>
- <module name="sys_rst" kind="altera_reset_bridge" version="15.1" enabled="1">
-  <parameter name="ACTIVE_LOW_RESET" value="0" />
-  <parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
-  <parameter name="NUM_RESET_OUTPUTS" value="1" />
-  <parameter name="SYNCHRONOUS_EDGES" value="none" />
-  <parameter name="USE_RESET_REQUEST" value="0" />
- </module>
- <connection
-   kind="clock"
-   version="15.1"
-   start="axi_ad9361.if_l_clk"
-   end="adc_pack.if_adc_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="axi_ad9361.if_l_clk"
-   end="axi_ad9361.if_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="axi_ad9361.if_l_clk"
-   end="dac_upack.if_dac_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="axi_ad9361.if_l_clk"
-   end="axi_dmac_dac.if_fifo_rd_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="axi_ad9361.if_l_clk"
-   end="axi_dmac_adc.if_fifo_wr_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="axi_dmac_adc.m_dest_axi_clock" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="axi_dmac_dac.m_src_axi_clock" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="axi_ad9361.s_axi_clock" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="axi_dmac_adc.s_axi_clock" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="axi_dmac_dac.s_axi_clock" />
- <connection
-   kind="conduit"
-   version="15.1"
-   start="dac_upack.fifo_ch_0"
-   end="axi_ad9361.fifo_ch_0_out">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_ad9361.fifo_ch_0_in"
-   end="adc_pack.fifo_ch_0">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_ad9361.fifo_ch_1_in"
-   end="adc_pack.fifo_ch_1">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_ad9361.fifo_ch_1_out"
-   end="dac_upack.fifo_ch_1">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_ad9361.fifo_ch_2_in"
-   end="adc_pack.fifo_ch_2">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_ad9361.fifo_ch_2_out"
-   end="dac_upack.fifo_ch_2">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_ad9361.fifo_ch_3_in"
-   end="adc_pack.fifo_ch_3">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_ad9361.fifo_ch_3_out"
-   end="dac_upack.fifo_ch_3">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="adc_pack.if_adc_data"
-   end="axi_dmac_adc.if_fifo_wr_din">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="adc_pack.if_adc_sync"
-   end="axi_dmac_adc.if_fifo_wr_sync">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="adc_pack.if_adc_valid"
-   end="axi_dmac_adc.if_fifo_wr_en">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="dac_upack.if_dac_data"
-   end="axi_dmac_dac.if_fifo_rd_dout">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="dac_upack.if_dma_xfer_in"
-   end="axi_dmac_dac.if_fifo_rd_xfer_req">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_dmac_dac.if_fifo_rd_en"
-   end="dac_upack.if_dac_valid">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_dmac_dac.if_fifo_rd_underflow"
-   end="axi_ad9361.if_dac_dunf">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_dmac_adc.if_fifo_wr_overflow"
-   end="axi_ad9361.if_adc_dovf">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="reset"
-   version="15.1"
-   start="axi_ad9361.if_rst"
-   end="adc_pack.if_adc_rst" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="adc_pack.if_adc_rst" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="axi_dmac_adc.m_dest_axi_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="axi_dmac_dac.m_src_axi_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="axi_ad9361.s_axi_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="axi_dmac_adc.s_axi_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="axi_dmac_dac.s_axi_reset" />
- <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />
- <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="2" />
- <interconnectRequirement
-   for="mm_interconnect_0|cmd_mux"
-   name="qsys_mm.postTransform.pipelineCount"
-   value="0" />
- <interconnectRequirement
-   for="mm_interconnect_2|cmd_mux"
-   name="qsys_mm.postTransform.pipelineCount"
-   value="0" />
- <interconnectRequirement
-   for="mm_interconnect_3|cmd_mux"
-   name="qsys_mm.postTransform.pipelineCount"
-   value="0" />
- <interconnectRequirement
-   for="mm_interconnect_3|cmd_mux_001"
-   name="qsys_mm.postTransform.pipelineCount"
-   value="0" />
- <interconnectRequirement
-   for="mm_interconnect_4|axi_dmac_dac_m_src_axi_agent.write_cp/router.sink"
-   name="qsys_mm.postTransform.pipelineCount"
-   value="0" />
- <interconnectRequirement
-   for="mm_interconnect_4|cmd_mux"
-   name="qsys_mm.postTransform.pipelineCount"
-   value="0" />
- <interconnectRequirement
-   for="mm_interconnect_4|cmd_mux_001"
-   name="qsys_mm.postTransform.pipelineCount"
-   value="0" />
-</system>
diff --git a/projects/fmcomms2/common/fmcomms2_qsys.tcl b/projects/fmcomms2/common/fmcomms2_qsys.tcl
new file mode 100644
index 000000000..2196c97b0
--- /dev/null
+++ b/projects/fmcomms2/common/fmcomms2_qsys.tcl
@@ -0,0 +1,135 @@
+
+# fmcomms2
+
+# ad9361 core
+
+add_instance axi_ad9361 axi_ad9361 1.0
+set_instance_parameter_value axi_ad9361 {ID} {0}
+
+add_connection sys_clk.clk_reset axi_ad9361.s_axi_reset
+add_connection sys_clk.clk axi_ad9361.s_axi_clock
+add_connection sys_cpu.data_master axi_ad9361.s_axi
+add_connection  axi_ad9361.if_l_clk axi_ad9361.if_clk
+
+# ad9361-unpack (dac)
+
+add_instance util_ad9361_dac_upack util_upack 1.0
+set_instance_parameter_value util_ad9361_dac_upack {CHANNEL_DATA_WIDTH} {16}
+set_instance_parameter_value util_ad9361_dac_upack {NUM_OF_CHANNELS} {4}
+
+add_connection  axi_ad9361.if_l_clk util_ad9361_dac_upack.if_dac_clk
+
+# ad9361-dma (dac)
+
+add_instance axi_ad9361_dac_dma axi_dmac 1.0
+set_instance_parameter_value axi_ad9361_dac_dma {DMA_DATA_WIDTH_DEST} {64}
+set_instance_parameter_value axi_ad9361_dac_dma {DMA_2D_TRANSFER} {0}
+set_instance_parameter_value axi_ad9361_dac_dma {DMA_TYPE_DEST} {2}
+set_instance_parameter_value axi_ad9361_dac_dma {DMA_TYPE_SRC} {0}
+set_instance_parameter_value axi_ad9361_dac_dma {CYCLIC} {1}
+set_instance_parameter_value axi_ad9361_dac_dma {SYNC_TRANSFER_START} {0}
+set_instance_parameter_value axi_ad9361_dac_dma {AXI_SLICE_SRC} {0}
+set_instance_parameter_value axi_ad9361_dac_dma {AXI_SLICE_DEST} {1}
+
+add_connection sys_clk.clk_reset axi_ad9361_dac_dma.s_axi_reset
+add_connection sys_clk.clk axi_ad9361_dac_dma.s_axi_clock
+add_connection sys_ddr3_cntrl.emif_usr_reset_n axi_ad9361_dac_dma.m_src_axi_reset
+add_connection sys_ddr3_cntrl.emif_usr_clk axi_ad9361_dac_dma.m_src_axi_clock
+add_connection axi_ad9361_dac_dma.m_src_axi sys_ddr3_cntrl.ctrl_amm_0
+add_connection sys_cpu.irq axi_ad9361_dac_dma.interrupt_sender
+
+# dac path connections
+
+add_connection  sys_cpu.data_master axi_ad9361_dac_dma.s_axi
+add_connection  util_ad9361_dac_upack.if_dac_valid axi_ad9361_dac_dma.if_fifo_rd_en
+add_connection  util_ad9361_dac_upack.if_dac_data axi_ad9361_dac_dma.if_fifo_rd_dout
+add_connection  axi_ad9361_dac_dma.if_fifo_rd_underflow axi_ad9361.if_dac_dunf
+add_connection  util_ad9361_dac_upack.dac_ch_0 axi_ad9361.dac_ch_0
+add_connection  util_ad9361_dac_upack.dac_ch_1 axi_ad9361.dac_ch_1
+add_connection  util_ad9361_dac_upack.dac_ch_2 axi_ad9361.dac_ch_2
+add_connection  util_ad9361_dac_upack.dac_ch_3 axi_ad9361.dac_ch_3
+add_connection  axi_ad9361.if_l_clk axi_ad9361_dac_dma.if_fifo_rd_clk
+
+# ad9361-adc-fifo
+
+add_instance util_ad9361_adc_fifo util_wfifo 1.0
+set_instance_parameter_value util_ad9361_adc_fifo {NUM_OF_CHANNELS} {4}
+set_instance_parameter_value util_ad9361_adc_fifo {DIN_ADDRESS_WIDTH} {4}
+set_instance_parameter_value util_ad9361_adc_fifo {DIN_DATA_WIDTH} {16}
+set_instance_parameter_value util_ad9361_adc_fifo {DOUT_DATA_WIDTH} {16}
+
+add_connection  axi_ad9361.if_l_clk util_ad9361_adc_fifo.if_din_clk
+add_connection  axi_ad9361.if_rst util_ad9361_adc_fifo.if_din_rst
+add_connection  sys_clk.clk_reset util_ad9361_adc_fifo.if_dout_rstn
+add_connection  sys_clk.clk util_ad9361_adc_fifo.if_dout_clk
+
+# ad9361-pack (adc)
+
+add_instance util_ad9361_adc_cpack util_cpack 1.0
+set_instance_parameter_value util_ad9361_adc_cpack {CHANNEL_DATA_WIDTH} {16}
+set_instance_parameter_value util_ad9361_adc_cpack {NUM_OF_CHANNELS} {4}
+
+add_connection  sys_clk.clk util_ad9361_adc_cpack.if_adc_clk
+add_connection  sys_clk.clk_reset util_ad9361_adc_cpack.if_adc_rst
+
+# ad9361-dma (adc)
+
+add_instance axi_ad9361_adc_dma axi_dmac 1.0
+set_instance_parameter_value axi_ad9361_adc_dma {DMA_DATA_WIDTH_SRC} {64}
+set_instance_parameter_value axi_ad9361_adc_dma {DMA_2D_TRANSFER} {0}
+set_instance_parameter_value axi_ad9361_adc_dma {AXI_SLICE_SRC} {0}
+set_instance_parameter_value axi_ad9361_adc_dma {SYNC_TRANSFER_START} {1}
+set_instance_parameter_value axi_ad9361_adc_dma {CYCLIC} {0}
+set_instance_parameter_value axi_ad9361_adc_dma {DMA_TYPE_DEST} {0}
+set_instance_parameter_value axi_ad9361_adc_dma {DMA_TYPE_SRC} {2}
+
+add_connection sys_clk.clk_reset axi_ad9361_adc_dma.s_axi_reset
+add_connection sys_clk.clk axi_ad9361_adc_dma.s_axi_clock
+add_connection sys_ddr3_cntrl.emif_usr_reset_n axi_ad9361_adc_dma.m_dest_axi_reset
+add_connection sys_ddr3_cntrl.emif_usr_clk axi_ad9361_adc_dma.m_dest_axi_clock
+add_connection sys_clk.clk axi_ad9361_adc_dma.if_fifo_wr_clk
+add_connection sys_cpu.irq axi_ad9361_adc_dma.interrupt_sender
+add_connection axi_ad9361_adc_dma.if_fifo_wr_overflow util_ad9361_adc_fifo.if_dout_ovf
+add_connection axi_ad9361_adc_dma.m_dest_axi sys_ddr3_cntrl.ctrl_amm_0
+
+# adc path connections
+
+add_connection  axi_ad9361.adc_ch_0 util_ad9361_adc_fifo.din_0
+add_connection  axi_ad9361.adc_ch_1 util_ad9361_adc_fifo.din_1
+add_connection  axi_ad9361.adc_ch_2 util_ad9361_adc_fifo.din_2
+add_connection  axi_ad9361.adc_ch_3 util_ad9361_adc_fifo.din_3
+add_connection  util_ad9361_adc_fifo.if_din_ovf axi_ad9361.if_adc_dovf
+add_connection  util_ad9361_adc_fifo.dout_0 util_ad9361_adc_cpack.adc_ch_0
+add_connection  util_ad9361_adc_fifo.dout_1 util_ad9361_adc_cpack.adc_ch_1
+add_connection  util_ad9361_adc_fifo.dout_2 util_ad9361_adc_cpack.adc_ch_2
+add_connection  util_ad9361_adc_fifo.dout_3 util_ad9361_adc_cpack.adc_ch_3
+add_connection  util_ad9361_adc_cpack.if_adc_valid axi_ad9361_adc_dma.if_fifo_wr_en
+add_connection  util_ad9361_adc_cpack.if_adc_sync axi_ad9361_adc_dma.if_fifo_wr_sync
+add_connection  util_ad9361_adc_cpack.if_adc_data axi_ad9361_adc_dma.if_fifo_wr_din
+add_connection sys_cpu.data_master axi_ad9361_adc_dma.s_axi
+add_interface up_enable conduit end
+add_interface up_txnrx conduit end
+add_interface delay_clk conduit end
+
+# setting interface propriety
+
+set_interface_property  axi_ad9361_device_if EXPORT_OF axi_ad9361.device_if
+set_interface_property  up_enable EXPORT_OF axi_ad9361.if_up_enable
+set_interface_property  up_txnrx EXPORT_OF axi_ad9361.if_up_txnrx
+set_interface_property  delay_clk EXPORT_OF axi_ad9361.if_delay_clk
+
+# addresses
+
+set_connection_parameter_value sys_cpu.data_master/axi_ad9361.s_axi                       baseAddress {0x10000000}
+set_connection_parameter_value sys_cpu.data_master/axi_ad9361_dac_dma.s_axi               baseAddress {0x10034000}
+set_connection_parameter_value sys_cpu.data_master/axi_ad9361_adc_dma.s_axi               baseAddress {0x10010000}
+
+set_connection_parameter_value axi_ad9361_adc_dma.m_dest_axi/sys_ddr3_cntrl.ctrl_amm_0    baseAddress {0x00000000}
+set_connection_parameter_value axi_ad9361_dac_dma.m_src_axi/sys_ddr3_cntrl.ctrl_amm_0     baseAddress {0x00000000}
+
+
+# interrupts
+
+set_connection_parameter_value sys_cpu.irq/axi_ad9361_adc_dma.interrupt_sender irqNumber {10}
+set_connection_parameter_value sys_cpu.irq/axi_ad9361_dac_dma.interrupt_sender irqNumber {11}
+