projects/adrv9009zu11eg: JESD support for fmcomms8
for configurations 4, 8 TX_L and 4 RX/ORX_L Signed-off-by: LIacob106 <liviu.iacob@analog.com>main
LIacob106
AndrDragomir
parent
261c0d1b90
commit
e932e6f4f8
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@ -313,7 +313,6 @@ ad_ip_parameter axi_adrv9009_som_rx_dma CONFIG.DMA_2D_TRANSFER 0
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ad_ip_parameter axi_adrv9009_som_rx_dma CONFIG.FIFO_SIZE 32
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ad_ip_parameter axi_adrv9009_som_rx_dma MAX_BYTES_PER_BURST 256
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ad_ip_parameter axi_adrv9009_som_rx_dma CONFIG.DMA_DATA_WIDTH_SRC $adc_dma_data_width
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### This could be a problem
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ad_ip_parameter axi_adrv9009_som_rx_dma CONFIG.DMA_DATA_WIDTH_DEST 128
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ad_ip_instance axi_adxcvr axi_adrv9009_som_obs_xcvr
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@ -385,14 +384,153 @@ ad_connect sys_cpu_clk util_adrv9009_som_xcvr/up_clk
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if {[info exists FMCOMMS8]} {
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#FMCOMMS8
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# Tx
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if {$TX_NUM_OF_LANES == 16} {
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ad_xcvrcon util_adrv9009_som_xcvr axi_adrv9009_som_tx_xcvr axi_adrv9009_som_tx_jesd {0 1 2 3 4 5 6 7 9 8 10 11 12 13 14 15} core_clk_a
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} else {
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#TX_JESD_L=8 it is recommanded to use RX_OS_JESD_M=TX_JESD_M because they share the same device clock
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ad_xcvrcon util_adrv9009_som_xcvr axi_adrv9009_som_tx_xcvr axi_adrv9009_som_tx_jesd {0 1 2 3 4 5 6 7 9 8 10 11 12 13 14 15} core_clk_a {} $MAX_TX_NUM_OF_LANES {0 1 4 5 9 8 12 13}
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if {$TX_NUM_OF_LANES == 8} {
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# TX_JESD_L=8 it is recommanded to use RX_OS_JESD_M=TX_JESD_M because they share the same device clock
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ad_xcvrcon util_adrv9009_som_xcvr axi_adrv9009_som_tx_xcvr axi_adrv9009_som_tx_jesd {0 1 2 3 4 5 6 7 9 8 10 11 12 13 14 15} core_clk_a {} $MAX_TX_NUM_OF_LANES {0 1 4 5 8 9 12 13}
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} else {
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# TX_JESD_L=4
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ad_xcvrcon util_adrv9009_som_xcvr axi_adrv9009_som_tx_xcvr axi_adrv9009_som_tx_jesd {0 1 2 3 4 5 6 7 9 8 10 11 12 13 14 15} core_clk_a {} $MAX_TX_NUM_OF_LANES {0 4 8 12}
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}
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}
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# Rx
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if {$RX_NUM_OF_LANES == 8} {
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ad_xcvrcon util_adrv9009_som_xcvr axi_adrv9009_som_rx_xcvr axi_adrv9009_som_rx_jesd {0 1 4 5 8 9 12 13} core_clk_b
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} else {
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# for RX_JESD_L=4, RX_OCTETS_PER_FRAME = 8
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# {0 1 4 5 8 9 12 13} are the lanes for rx
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ad_connect adrv9009_som_rx_link_clk util_adrv9009_som_xcvr/rx_out_clk_0
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ad_xcvrcon util_adrv9009_som_xcvr axi_adrv9009_som_rx_xcvr axi_adrv9009_som_rx_jesd {0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15} adrv9009_som_rx_link_clk core_clk_b $MAX_RX_NUM_OF_LANES {0 4 8 12} 0
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ad_connect axi_adrv9009_som_rx_xcvr/up_es_0 util_adrv9009_som_xcvr/up_es_0
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ad_connect axi_adrv9009_som_rx_xcvr/up_es_1 util_adrv9009_som_xcvr/up_es_1
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ad_connect axi_adrv9009_som_rx_xcvr/up_es_2 util_adrv9009_som_xcvr/up_es_4
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ad_connect axi_adrv9009_som_rx_xcvr/up_es_3 util_adrv9009_som_xcvr/up_es_5
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ad_connect axi_adrv9009_som_rx_xcvr/up_es_4 util_adrv9009_som_xcvr/up_es_8
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ad_connect axi_adrv9009_som_rx_xcvr/up_es_5 util_adrv9009_som_xcvr/up_es_9
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ad_connect axi_adrv9009_som_rx_xcvr/up_es_6 util_adrv9009_som_xcvr/up_es_12
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ad_connect axi_adrv9009_som_rx_xcvr/up_es_7 util_adrv9009_som_xcvr/up_es_13
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ad_connect axi_adrv9009_som_rx_xcvr/up_ch_0 util_adrv9009_som_xcvr/up_rx_0
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ad_connect axi_adrv9009_som_rx_xcvr/up_ch_1 util_adrv9009_som_xcvr/up_rx_1
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ad_connect axi_adrv9009_som_rx_xcvr/up_ch_2 util_adrv9009_som_xcvr/up_rx_4
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ad_connect axi_adrv9009_som_rx_xcvr/up_ch_3 util_adrv9009_som_xcvr/up_rx_5
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ad_connect axi_adrv9009_som_rx_xcvr/up_ch_4 util_adrv9009_som_xcvr/up_rx_8
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ad_connect axi_adrv9009_som_rx_xcvr/up_ch_5 util_adrv9009_som_xcvr/up_rx_9
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ad_connect axi_adrv9009_som_rx_xcvr/up_ch_6 util_adrv9009_som_xcvr/up_rx_12
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ad_connect axi_adrv9009_som_rx_xcvr/up_ch_7 util_adrv9009_som_xcvr/up_rx_13
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ad_connect adrv9009_som_rx_link_clk util_adrv9009_som_xcvr/rx_clk_0
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ad_connect adrv9009_som_rx_link_clk util_adrv9009_som_xcvr/rx_clk_1
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ad_connect adrv9009_som_rx_link_clk util_adrv9009_som_xcvr/rx_clk_4
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ad_connect adrv9009_som_rx_link_clk util_adrv9009_som_xcvr/rx_clk_5
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ad_connect adrv9009_som_rx_link_clk util_adrv9009_som_xcvr/rx_clk_8
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ad_connect adrv9009_som_rx_link_clk util_adrv9009_som_xcvr/rx_clk_9
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ad_connect adrv9009_som_rx_link_clk util_adrv9009_som_xcvr/rx_clk_12
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ad_connect adrv9009_som_rx_link_clk util_adrv9009_som_xcvr/rx_clk_13
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create_bd_port -dir I rx_data_0_p
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create_bd_port -dir I rx_data_0_n
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create_bd_port -dir I rx_data_1_p
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create_bd_port -dir I rx_data_1_n
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create_bd_port -dir I rx_data_4_p
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create_bd_port -dir I rx_data_4_n
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create_bd_port -dir I rx_data_5_p
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create_bd_port -dir I rx_data_5_n
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create_bd_port -dir I rx_data_8_p
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create_bd_port -dir I rx_data_8_n
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create_bd_port -dir I rx_data_9_p
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create_bd_port -dir I rx_data_9_n
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create_bd_port -dir I rx_data_12_p
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create_bd_port -dir I rx_data_12_n
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create_bd_port -dir I rx_data_13_p
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create_bd_port -dir I rx_data_13_n
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ad_connect util_adrv9009_som_xcvr/rx_0_p rx_data_0_p
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ad_connect util_adrv9009_som_xcvr/rx_0_n rx_data_0_n
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ad_connect util_adrv9009_som_xcvr/rx_1_p rx_data_1_p
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ad_connect util_adrv9009_som_xcvr/rx_1_n rx_data_1_n
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ad_connect util_adrv9009_som_xcvr/rx_4_p rx_data_4_p
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ad_connect util_adrv9009_som_xcvr/rx_4_n rx_data_4_n
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ad_connect util_adrv9009_som_xcvr/rx_5_p rx_data_5_p
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ad_connect util_adrv9009_som_xcvr/rx_5_n rx_data_5_n
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ad_connect util_adrv9009_som_xcvr/rx_8_p rx_data_8_p
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ad_connect util_adrv9009_som_xcvr/rx_8_n rx_data_8_n
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ad_connect util_adrv9009_som_xcvr/rx_9_p rx_data_9_p
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ad_connect util_adrv9009_som_xcvr/rx_9_n rx_data_9_n
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ad_connect util_adrv9009_som_xcvr/rx_12_p rx_data_12_p
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ad_connect util_adrv9009_som_xcvr/rx_12_n rx_data_12_n
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ad_connect util_adrv9009_som_xcvr/rx_13_p rx_data_13_p
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ad_connect util_adrv9009_som_xcvr/rx_13_n rx_data_13_n
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}
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# Rx - Obs
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if {$RX_OS_NUM_OF_LANES == 8} {
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ad_xcvrcon util_adrv9009_som_xcvr axi_adrv9009_som_obs_xcvr axi_adrv9009_som_obs_jesd {2 3 6 7 10 11 14 15} core_clk_a
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} else {
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# ORX_JESD_L=4
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# {2 3 6 7 10 11 14 15} are the lanes for orx
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ad_xcvrcon util_adrv9009_som_xcvr axi_adrv9009_som_obs_xcvr axi_adrv9009_som_obs_jesd {0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15} core_clk_a {} $MAX_RX_OS_NUM_OF_LANES {2 6 10 14} 0
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ad_connect axi_adrv9009_som_obs_xcvr/up_es_0 util_adrv9009_som_xcvr/up_es_2
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ad_connect axi_adrv9009_som_obs_xcvr/up_es_1 util_adrv9009_som_xcvr/up_es_3
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ad_connect axi_adrv9009_som_obs_xcvr/up_es_2 util_adrv9009_som_xcvr/up_es_6
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ad_connect axi_adrv9009_som_obs_xcvr/up_es_3 util_adrv9009_som_xcvr/up_es_7
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ad_connect axi_adrv9009_som_obs_xcvr/up_es_4 util_adrv9009_som_xcvr/up_es_10
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ad_connect axi_adrv9009_som_obs_xcvr/up_es_5 util_adrv9009_som_xcvr/up_es_11
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ad_connect axi_adrv9009_som_obs_xcvr/up_es_6 util_adrv9009_som_xcvr/up_es_14
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ad_connect axi_adrv9009_som_obs_xcvr/up_es_7 util_adrv9009_som_xcvr/up_es_15
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ad_connect axi_adrv9009_som_obs_xcvr/up_ch_0 util_adrv9009_som_xcvr/up_rx_2
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ad_connect axi_adrv9009_som_obs_xcvr/up_ch_1 util_adrv9009_som_xcvr/up_rx_3
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ad_connect axi_adrv9009_som_obs_xcvr/up_ch_2 util_adrv9009_som_xcvr/up_rx_6
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ad_connect axi_adrv9009_som_obs_xcvr/up_ch_3 util_adrv9009_som_xcvr/up_rx_7
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ad_connect axi_adrv9009_som_obs_xcvr/up_ch_4 util_adrv9009_som_xcvr/up_rx_10
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ad_connect axi_adrv9009_som_obs_xcvr/up_ch_5 util_adrv9009_som_xcvr/up_rx_11
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ad_connect axi_adrv9009_som_obs_xcvr/up_ch_6 util_adrv9009_som_xcvr/up_rx_14
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ad_connect axi_adrv9009_som_obs_xcvr/up_ch_7 util_adrv9009_som_xcvr/up_rx_15
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ad_connect core_clk_a util_adrv9009_som_xcvr/rx_clk_2
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ad_connect core_clk_a util_adrv9009_som_xcvr/rx_clk_3
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ad_connect core_clk_a util_adrv9009_som_xcvr/rx_clk_6
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ad_connect core_clk_a util_adrv9009_som_xcvr/rx_clk_7
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ad_connect core_clk_a util_adrv9009_som_xcvr/rx_clk_10
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ad_connect core_clk_a util_adrv9009_som_xcvr/rx_clk_11
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ad_connect core_clk_a util_adrv9009_som_xcvr/rx_clk_14
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ad_connect core_clk_a util_adrv9009_som_xcvr/rx_clk_15
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create_bd_port -dir I rx_data_2_p
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create_bd_port -dir I rx_data_2_n
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create_bd_port -dir I rx_data_3_p
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create_bd_port -dir I rx_data_3_n
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create_bd_port -dir I rx_data_6_p
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create_bd_port -dir I rx_data_6_n
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create_bd_port -dir I rx_data_7_p
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create_bd_port -dir I rx_data_7_n
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create_bd_port -dir I rx_data_10_p
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create_bd_port -dir I rx_data_10_n
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create_bd_port -dir I rx_data_11_p
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create_bd_port -dir I rx_data_11_n
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create_bd_port -dir I rx_data_14_p
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create_bd_port -dir I rx_data_14_n
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create_bd_port -dir I rx_data_15_p
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create_bd_port -dir I rx_data_15_n
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ad_connect util_adrv9009_som_xcvr/rx_2_p rx_data_2_p
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ad_connect util_adrv9009_som_xcvr/rx_2_n rx_data_2_n
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ad_connect util_adrv9009_som_xcvr/rx_3_p rx_data_3_p
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ad_connect util_adrv9009_som_xcvr/rx_3_n rx_data_3_n
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ad_connect util_adrv9009_som_xcvr/rx_6_p rx_data_6_p
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ad_connect util_adrv9009_som_xcvr/rx_6_n rx_data_6_n
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ad_connect util_adrv9009_som_xcvr/rx_7_p rx_data_7_p
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ad_connect util_adrv9009_som_xcvr/rx_7_n rx_data_7_n
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ad_connect util_adrv9009_som_xcvr/rx_10_p rx_data_10_p
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ad_connect util_adrv9009_som_xcvr/rx_10_n rx_data_10_n
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ad_connect util_adrv9009_som_xcvr/rx_11_p rx_data_11_p
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ad_connect util_adrv9009_som_xcvr/rx_11_n rx_data_11_n
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ad_connect util_adrv9009_som_xcvr/rx_14_p rx_data_14_p
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ad_connect util_adrv9009_som_xcvr/rx_14_n rx_data_14_n
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ad_connect util_adrv9009_som_xcvr/rx_15_p rx_data_15_p
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ad_connect util_adrv9009_som_xcvr/rx_15_n rx_data_15_n
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}
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ad_xcvrcon util_adrv9009_som_xcvr axi_adrv9009_som_rx_xcvr axi_adrv9009_som_rx_jesd {0 1 4 5 8 9 12 13} core_clk_b
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ad_xcvrcon util_adrv9009_som_xcvr axi_adrv9009_som_obs_xcvr axi_adrv9009_som_obs_jesd {2 3 6 7 10 11 14 15} core_clk_a
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} else {
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#ADRV2CRR_FMC
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# Tx
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@ -400,26 +538,21 @@ if {[info exists FMCOMMS8]} {
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ad_xcvrcon util_adrv9009_som_xcvr axi_adrv9009_som_tx_xcvr axi_adrv9009_som_tx_jesd {} core_clk_a
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} else {
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if {$TX_NUM_OF_LANES == 4} {
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#TX_JESD_L=4, it is recommanded to use RX_OS_JESD_M=TX_JESD_M because they share the same device clock
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# TX_JESD_L=4, it is recommanded to use RX_OS_JESD_M=TX_JESD_M because they share the same device clock
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ad_xcvrcon util_adrv9009_som_xcvr axi_adrv9009_som_tx_xcvr axi_adrv9009_som_tx_jesd {0 1 2 3 4 5 6 7} core_clk_a {} $MAX_TX_NUM_OF_LANES {0 1 4 5}
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} else {
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#TX_JESD_L=2
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# TX_JESD_L=2
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ad_xcvrcon util_adrv9009_som_xcvr axi_adrv9009_som_tx_xcvr axi_adrv9009_som_tx_jesd {0 1 2 3 4 5 6 7} core_clk_a {} $MAX_TX_NUM_OF_LANES {0 4}
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}
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}
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}
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# Rx
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if {$RX_NUM_OF_LANES == 4} {
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ad_xcvrcon util_adrv9009_som_xcvr axi_adrv9009_som_rx_xcvr axi_adrv9009_som_rx_jesd {0 1 4 5} core_clk_b
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} else {
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# for RX_JESD_L=2, RX_OCTETS_PER_FRAME = 8
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# 0 1 4 5 are the lanes for rx
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# find replacement for this
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#ad_connect adrv9009_rx_device_clk axi_adrv9009_rx_clkgen/clk_1
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#ad_connect adrv9009_rx_link_clk axi_adrv9009_rx_clkgen/clk_0
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#connect_bd_net [get_bd_pins util_adrv9009_som_xcvr/rx_out_clk_0] [get_bd_pins axi_adrv9009_som_rx_jesd/link_clk]
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# {0 1 4 5} are the lanes for rx
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ad_connect adrv9009_som_rx_link_clk util_adrv9009_som_xcvr/rx_out_clk_0
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# core_clk_b is should be the link clock
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ad_xcvrcon util_adrv9009_som_xcvr axi_adrv9009_som_rx_xcvr axi_adrv9009_som_rx_jesd {0 1 2 3 4 5 6 7} adrv9009_som_rx_link_clk core_clk_b $MAX_RX_NUM_OF_LANES {0 4} 0
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ad_connect axi_adrv9009_som_rx_xcvr/up_es_0 util_adrv9009_som_xcvr/up_es_0
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ad_connect axi_adrv9009_som_rx_xcvr/up_es_1 util_adrv9009_som_xcvr/up_es_1
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@ -453,12 +586,12 @@ if {[info exists FMCOMMS8]} {
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ad_connect util_adrv9009_som_xcvr/rx_5_n rx_data_5_n
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}
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# Rx -OBS
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# Rx - Obs
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if {$RX_OS_NUM_OF_LANES == 4} {
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ad_xcvrcon util_adrv9009_som_xcvr axi_adrv9009_som_obs_xcvr axi_adrv9009_som_obs_jesd {2 3 6 7} core_clk_a
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} else {
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#ORX_JESD_L=2
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# 2 3 6 7 are the lanes for orx
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# ORX_JESD_L=2
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# {2 3 6 7} are the lanes for orx
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ad_xcvrcon util_adrv9009_som_xcvr axi_adrv9009_som_obs_xcvr axi_adrv9009_som_obs_jesd {0 1 2 3 4 5 6 7} core_clk_a {} $MAX_RX_OS_NUM_OF_LANES {2 6} 0
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ad_connect axi_adrv9009_som_obs_xcvr/up_es_0 util_adrv9009_som_xcvr/up_es_2
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ad_connect axi_adrv9009_som_obs_xcvr/up_es_1 util_adrv9009_som_xcvr/up_es_3
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@ -493,10 +626,6 @@ if {[info exists FMCOMMS8]} {
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}
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}
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##rx and orx stuff
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##ad_xcvrcon util_adrv9009_som_xcvr axi_adrv9009_som_rx_xcvr axi_adrv9009_som_rx_jesd {0 1 4 5} core_clk_b
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##ad_xcvrcon util_adrv9009_som_xcvr axi_adrv9009_som_obs_xcvr axi_adrv9009_som_obs_jesd {2 3 6 7} core_clk_a
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ad_connect core_clk_a tx_adrv9009_som_tpl_core/link_clk
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ad_connect axi_adrv9009_som_tx_jesd/tx_data tx_adrv9009_som_tpl_core/link
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@ -514,18 +643,9 @@ ad_connect tx_sysref_0 tx_adrv9009_som_tpl_core/dac_tpl_core/dac_sync_in
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# connections (adc)
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if {$RX_OCTETS_PER_FRAME == 8} {
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# if this does not work, swap with link_clk
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ad_connect core_clk_b rx_adrv9009_som_tpl_core/link_clk
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ad_connect core_clk_b util_som_rx_cpack/clk
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ad_connect axi_adrv9009_som_rx_dma/fifo_wr_clk core_clk_b
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} else {
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ad_connect core_clk_b rx_adrv9009_som_tpl_core/link_clk
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ad_connect core_clk_b util_som_rx_cpack/clk
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ad_connect axi_adrv9009_som_rx_dma/fifo_wr_clk core_clk_b
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}
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ad_connect core_clk_b rx_adrv9009_som_tpl_core/link_clk
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ad_connect core_clk_b util_som_rx_cpack/clk
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ad_connect axi_adrv9009_som_rx_dma/fifo_wr_clk core_clk_b
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ad_connect axi_adrv9009_som_rx_jesd/rx_sof rx_adrv9009_som_tpl_core/link_sof
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ad_connect axi_adrv9009_som_rx_jesd/rx_data_tdata rx_adrv9009_som_tpl_core/link_data
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|
|
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Loading…
Reference in New Issue