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ad9671_fmc: changed for ad9671-fmc

main
Rejeesh Kutty 2014-04-10 16:09:14 -04:00
parent 72e318a247
commit e92e6b2fd5
5 changed files with 302 additions and 298 deletions
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339
projects/ad9671_fmc/common/ad9671_fmc_bd.tcl
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@ -1,8 +1,10 @@
# usdrx1
# ad9671
set spi_csn_i [create_bd_port -dir I -from 10 -to 0 spi_csn_i]
set spi_csn_o [create_bd_port -dir O -from 10 -to 0 spi_csn_o]
set spi_csn_2_o [create_bd_port -dir O spi_csn_2_o]
set spi_csn_1_o [create_bd_port -dir O spi_csn_1_o]
set spi_csn_0_o [create_bd_port -dir O spi_csn_0_o]
set spi_csn_i [create_bd_port -dir I spi_csn_i]
set spi_clk_i [create_bd_port -dir I spi_clk_i]
set spi_clk_o [create_bd_port -dir O spi_clk_o]
set spi_sdo_i [create_bd_port -dir I spi_sdo_i]
@ -12,235 +14,147 @@ set spi_sdi_i [create_bd_port -dir I spi_sdi_i]
set rx_ref_clk [create_bd_port -dir I rx_ref_clk]
set rx_sync [create_bd_port -dir O rx_sync]
set rx_sysref [create_bd_port -dir O rx_sysref]
set rx_data_p [create_bd_port -dir I -from 7 -to 0 rx_data_p]
set rx_data_n [create_bd_port -dir I -from 7 -to 0 rx_data_n]
set mlo_clk [create_bd_port -dir O mlo_clk]
set gt_rx_data [create_bd_port -dir O -from 255 -to 0 gt_rx_data]
set gt_rx_data_0 [create_bd_port -dir I -from 63 -to 0 gt_rx_data_0]
set gt_rx_data_1 [create_bd_port -dir I -from 63 -to 0 gt_rx_data_1]
set gt_rx_data_2 [create_bd_port -dir I -from 63 -to 0 gt_rx_data_2]
set gt_rx_data_3 [create_bd_port -dir I -from 63 -to 0 gt_rx_data_3]
set adc_dwr_0 [create_bd_port -dir O adc_dwr_0]
set adc_dwr_1 [create_bd_port -dir O adc_dwr_1]
set adc_dwr_2 [create_bd_port -dir O adc_dwr_2]
set adc_dwr_3 [create_bd_port -dir O adc_dwr_3]
set adc_dsync_0 [create_bd_port -dir O adc_dsync_0]
set adc_dsync_1 [create_bd_port -dir O adc_dsync_1]
set adc_dsync_2 [create_bd_port -dir O adc_dsync_2]
set adc_dsync_3 [create_bd_port -dir O adc_dsync_3]
set adc_ddata_0 [create_bd_port -dir O -from 127 -to 0 adc_ddata_0]
set adc_ddata_1 [create_bd_port -dir O -from 127 -to 0 adc_ddata_1]
set adc_ddata_2 [create_bd_port -dir O -from 127 -to 0 adc_ddata_2]
set adc_ddata_3 [create_bd_port -dir O -from 127 -to 0 adc_ddata_3]
set adc_dovf_0 [create_bd_port -dir I adc_dovf_0]
set adc_dovf_1 [create_bd_port -dir I adc_dovf_1]
set adc_dovf_2 [create_bd_port -dir I adc_dovf_2]
set adc_dovf_3 [create_bd_port -dir I adc_dovf_3]
set adc_dwr [create_bd_port -dir I adc_dwr]
set adc_dsync [create_bd_port -dir I adc_dsync]
set adc_ddata [create_bd_port -dir I -from 511 -to 0 adc_ddata]
set adc_dovf [create_bd_port -dir O adc_dovf]
set rx_data_p [create_bd_port -dir I -from 3 -to 0 rx_data_p]
set rx_data_n [create_bd_port -dir I -from 3 -to 0 rx_data_n]
# adc peripherals
set axi_ad9671_core_0 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9671:1.0 axi_ad9671_core_0]
set_property -dict [list CONFIG.PCORE_4L_2L_N {0}] [get_bd_cells axi_ad9671_core_0]
set axi_ad9671_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9671:1.0 axi_ad9671_core]
set_property -dict [list CONFIG.PCORE_4L_2L_N {1}] [get_bd_cells axi_ad9671_core]
set axi_ad9671_core_1 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9671:1.0 axi_ad9671_core_1]
set_property -dict [list CONFIG.PCORE_4L_2L_N {0}] [get_bd_cells axi_ad9671_core_1]
set axi_ad9671_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:5.1 axi_ad9671_jesd]
set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9671_jesd
set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9671_jesd
set axi_ad9671_core_2 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9671:1.0 axi_ad9671_core_2]
set_property -dict [list CONFIG.PCORE_4L_2L_N {0}] [get_bd_cells axi_ad9671_core_2]
set axi_ad9671_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_ad9671_gt]
set_property -dict [list CONFIG.PCORE_NUM_OF_LANES {4}] [get_bd_cells axi_ad9671_gt]
set_property -dict [list CONFIG.PCORE_CPLL_FBDIV {4}] $axi_ad9671_gt
set_property -dict [list CONFIG.PCORE_RX_OUT_DIV {2}] $axi_ad9671_gt
set_property -dict [list CONFIG.PCORE_TX_OUT_DIV {2}] $axi_ad9671_gt
set_property -dict [list CONFIG.PCORE_RX_CLK25_DIV {4}] $axi_ad9671_gt
set_property -dict [list CONFIG.PCORE_TX_CLK25_DIV {4}] $axi_ad9671_gt
set_property -dict [list CONFIG.PCORE_PMA_RSV {0x00018480}] $axi_ad9671_gt
set_property -dict [list CONFIG.PCORE_RX_CDR_CFG {0x03000023ff40200020}] $axi_ad9671_gt
set axi_ad9671_core_3 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9671:1.0 axi_ad9671_core_3]
set_property -dict [list CONFIG.PCORE_4L_2L_N {0}] [get_bd_cells axi_ad9671_core_3]
set axi_ad9671_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9671_dma]
set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_ad9671_dma
set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_ad9671_dma
set_property -dict [list CONFIG.PCORE_ID {0}] $axi_ad9671_dma
set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9671_dma
set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9671_dma
set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {1}] $axi_ad9671_dma
set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_ad9671_dma
set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_ad9671_dma
set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9671_dma
set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9671_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {128}] $axi_ad9671_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {128}] $axi_ad9671_dma
set axi_usdrx1_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:5.1 axi_usdrx1_jesd]
set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_usdrx1_jesd
set_property -dict [list CONFIG.C_LANES {8}] $axi_usdrx1_jesd
set axi_ad9671_gt_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9671_gt_interconnect]
set_property -dict [list CONFIG.NUM_MI {1}] $axi_ad9671_gt_interconnect
set axi_usdrx1_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_usdrx1_gt]
set_property -dict [list CONFIG.PCORE_NUM_OF_LANES {8}] [get_bd_cells axi_usdrx1_gt]
set_property -dict [list CONFIG.PCORE_CPLL_FBDIV {4}] $axi_usdrx1_gt
set_property -dict [list CONFIG.PCORE_RX_OUT_DIV {1}] $axi_usdrx1_gt
set_property -dict [list CONFIG.PCORE_TX_OUT_DIV {1}] $axi_usdrx1_gt
set_property -dict [list CONFIG.PCORE_RX_CLK25_DIV {4}] $axi_usdrx1_gt
set_property -dict [list CONFIG.PCORE_TX_CLK25_DIV {4}] $axi_usdrx1_gt
set_property -dict [list CONFIG.PCORE_PMA_RSV {0x00018480}] $axi_usdrx1_gt
set_property -dict [list CONFIG.PCORE_RX_CDR_CFG {0x03000023ff20400020}] $axi_usdrx1_gt
set axi_usdrx1_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_usdrx1_dma]
set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_usdrx1_dma
set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_usdrx1_dma
set_property -dict [list CONFIG.PCORE_ID {0}] $axi_usdrx1_dma
set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_usdrx1_dma
set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_usdrx1_dma
set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {1}] $axi_usdrx1_dma
set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_usdrx1_dma
set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_usdrx1_dma
set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_usdrx1_dma
set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_usdrx1_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {512}] $axi_usdrx1_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {512}] $axi_usdrx1_dma
set axi_usdrx1_gt_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_usdrx1_gt_interconnect]
set_property -dict [list CONFIG.NUM_MI {1}] $axi_usdrx1_gt_interconnect
set axi_usdrx1_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_usdrx1_dma_interconnect]
set_property -dict [list CONFIG.NUM_MI {1}] $axi_usdrx1_dma_interconnect
# gpio and spi
set axi_usdrx1_spi [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.1 axi_usdrx1_spi]
set_property -dict [list CONFIG.C_USE_STARTUP {0}] $axi_usdrx1_spi
set_property -dict [list CONFIG.C_NUM_SS_BITS {11}] $axi_usdrx1_spi
set_property -dict [list CONFIG.C_SCK_RATIO {8}] $axi_usdrx1_spi
set axi_ad9671_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9671_dma_interconnect]
set_property -dict [list CONFIG.NUM_MI {1}] $axi_ad9671_dma_interconnect
# additions to default configuration
set_property -dict [list CONFIG.NUM_MI {15}] $axi_cpu_interconnect
set_property -dict [list CONFIG.NUM_MI {11}] $axi_cpu_interconnect
set_property -dict [list CONFIG.PCW_USE_S_AXI_HP2 {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_USE_S_AXI_HP3 {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_EN_CLK3_PORT {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_EN_RST2_PORT {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7
set_property -dict [list CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {40}] $sys_ps7
set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {44}] $sys_ps7
set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {24}] $sys_ps7
set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7
set_property LEFT 43 [get_bd_ports GPIO_I]
set_property LEFT 43 [get_bd_ports GPIO_O]
set_property LEFT 43 [get_bd_ports GPIO_T]
set_property LEFT 23 [get_bd_ports GPIO_I]
set_property LEFT 23 [get_bd_ports GPIO_O]
set_property LEFT 23 [get_bd_ports GPIO_T]
# connections (spi and gpio)
connect_bd_net -net axi_spi_1_csn_i [get_bd_ports spi_csn_i] [get_bd_pins axi_usdrx1_spi/ss_i]
connect_bd_net -net axi_spi_1_csn_o [get_bd_ports spi_csn_o] [get_bd_pins axi_usdrx1_spi/ss_o]
connect_bd_net -net axi_spi_1_clk_i [get_bd_ports spi_clk_i] [get_bd_pins axi_usdrx1_spi/sck_i]
connect_bd_net -net axi_spi_1_clk_o [get_bd_ports spi_clk_o] [get_bd_pins axi_usdrx1_spi/sck_o]
connect_bd_net -net axi_spi_1_sdo_i [get_bd_ports spi_sdo_i] [get_bd_pins axi_usdrx1_spi/io0_i]
connect_bd_net -net axi_spi_1_sdo_o [get_bd_ports spi_sdo_o] [get_bd_pins axi_usdrx1_spi/io0_o]
connect_bd_net -net axi_spi_1_sdi_i [get_bd_ports spi_sdi_i] [get_bd_pins axi_usdrx1_spi/io1_i]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_spi/ext_spi_clk]
connect_bd_net -net axi_spi_1_irq [get_bd_pins axi_usdrx1_spi/ip2intc_irpt] [get_bd_pins sys_concat_intc/In3]
connect_bd_net -net spi_csn_2_o [get_bd_ports spi_csn_2_o] [get_bd_pins sys_ps7/SPI0_SS2_O]
connect_bd_net -net spi_csn_1_o [get_bd_ports spi_csn_1_o] [get_bd_pins sys_ps7/SPI0_SS1_O]
connect_bd_net -net spi_csn_0_o [get_bd_ports spi_csn_0_o] [get_bd_pins sys_ps7/SPI0_SS_O]
connect_bd_net -net spi_csn_i [get_bd_ports spi_csn_i] [get_bd_pins sys_ps7/SPI0_SS_I]
connect_bd_net -net spi_clk_i [get_bd_ports spi_clk_i] [get_bd_pins sys_ps7/SPI0_SCLK_I]
connect_bd_net -net spi_clk_o [get_bd_ports spi_clk_o] [get_bd_pins sys_ps7/SPI0_SCLK_O]
connect_bd_net -net spi_sdo_i [get_bd_ports spi_sdo_i] [get_bd_pins sys_ps7/SPI0_MOSI_I]
connect_bd_net -net spi_sdo_o [get_bd_ports spi_sdo_o] [get_bd_pins sys_ps7/SPI0_MOSI_O]
connect_bd_net -net spi_sdi_i [get_bd_ports spi_sdi_i] [get_bd_pins sys_ps7/SPI0_MISO_I]
# connections (gt)
connect_bd_net -net axi_usdrx1_gt_ref_clk_c [get_bd_pins axi_usdrx1_gt/ref_clk_c] [get_bd_ports rx_ref_clk]
connect_bd_net -net axi_usdrx1_gt_rx_data_p [get_bd_pins axi_usdrx1_gt/rx_data_p] [get_bd_ports rx_data_p]
connect_bd_net -net axi_usdrx1_gt_rx_data_n [get_bd_pins axi_usdrx1_gt/rx_data_n] [get_bd_ports rx_data_n]
connect_bd_net -net axi_usdrx1_gt_rx_sync [get_bd_pins axi_usdrx1_gt/rx_sync] [get_bd_ports rx_sync]
connect_bd_net -net axi_usdrx1_gt_rx_sysref [get_bd_pins axi_usdrx1_gt/rx_sysref] [get_bd_ports rx_sysref]
connect_bd_net -net axi_ad9671_gt_ref_clk_c [get_bd_pins axi_ad9671_gt/ref_clk_c] [get_bd_ports rx_ref_clk]
connect_bd_net -net axi_ad9671_gt_rx_data_p [get_bd_pins axi_ad9671_gt/rx_data_p] [get_bd_ports rx_data_p]
connect_bd_net -net axi_ad9671_gt_rx_data_n [get_bd_pins axi_ad9671_gt/rx_data_n] [get_bd_ports rx_data_n]
connect_bd_net -net axi_ad9671_gt_rx_sync [get_bd_pins axi_ad9671_gt/rx_sync] [get_bd_ports rx_sync]
connect_bd_net -net axi_ad9671_gt_rx_sysref [get_bd_pins axi_ad9671_gt/rx_sysref] [get_bd_ports rx_sysref]
# connections (adc)
connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_usdrx1_gt/rx_clk]
connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_ad9671_core_0/rx_clk]
connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_ad9671_core_1/rx_clk]
connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_ad9671_core_2/rx_clk]
connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_ad9671_core_3/rx_clk]
connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_usdrx1_jesd/rx_core_clk]
connect_bd_net -net axi_ad9671_gt_rx_clk [get_bd_pins axi_ad9671_gt/rx_clk]
connect_bd_net -net axi_ad9671_gt_rx_clk [get_bd_pins axi_ad9671_core/rx_clk]
connect_bd_net -net axi_ad9671_gt_rx_clk [get_bd_pins axi_ad9671_jesd/rx_core_clk]
connect_bd_net -net axi_usdrx1_gt_rx_rst [get_bd_pins axi_usdrx1_gt/rx_rst] [get_bd_pins axi_usdrx1_jesd/rx_reset]
connect_bd_net -net axi_usdrx1_gt_rx_sysref [get_bd_pins axi_usdrx1_jesd/rx_sysref]
connect_bd_net -net axi_usdrx1_gt_rx_gt_charisk [get_bd_pins axi_usdrx1_gt/rx_gt_charisk] [get_bd_pins axi_usdrx1_jesd/gt_rxcharisk_in]
connect_bd_net -net axi_usdrx1_gt_rx_gt_disperr [get_bd_pins axi_usdrx1_gt/rx_gt_disperr] [get_bd_pins axi_usdrx1_jesd/gt_rxdisperr_in]
connect_bd_net -net axi_usdrx1_gt_rx_gt_notintable [get_bd_pins axi_usdrx1_gt/rx_gt_notintable] [get_bd_pins axi_usdrx1_jesd/gt_rxnotintable_in]
connect_bd_net -net axi_usdrx1_gt_rx_gt_data [get_bd_pins axi_usdrx1_gt/rx_gt_data] [get_bd_pins axi_usdrx1_jesd/gt_rxdata_in]
connect_bd_net -net axi_usdrx1_gt_rx_rst_done [get_bd_pins axi_usdrx1_gt/rx_rst_done] [get_bd_pins axi_usdrx1_jesd/rx_reset_done]
connect_bd_net -net axi_usdrx1_gt_rx_ip_comma_align [get_bd_pins axi_usdrx1_gt/rx_ip_comma_align] [get_bd_pins axi_usdrx1_jesd/rxencommaalign_out]
connect_bd_net -net axi_usdrx1_gt_rx_ip_sync [get_bd_pins axi_usdrx1_gt/rx_ip_sync] [get_bd_pins axi_usdrx1_jesd/rx_sync]
connect_bd_net -net axi_usdrx1_gt_rx_ip_sof [get_bd_pins axi_usdrx1_gt/rx_ip_sof] [get_bd_pins axi_usdrx1_jesd/rx_start_of_frame]
connect_bd_net -net axi_usdrx1_gt_rx_ip_data [get_bd_pins axi_usdrx1_gt/rx_ip_data] [get_bd_pins axi_usdrx1_jesd/rx_tdata]
connect_bd_net -net axi_usdrx1_gt_rx_data [get_bd_pins axi_usdrx1_gt/rx_data] [get_bd_ports gt_rx_data]
connect_bd_net -net axi_usdrx1_gt_rx_data_0 [get_bd_pins axi_ad9671_core_0/rx_data] [get_bd_ports gt_rx_data_0]
connect_bd_net -net axi_usdrx1_gt_rx_data_1 [get_bd_pins axi_ad9671_core_1/rx_data] [get_bd_ports gt_rx_data_1]
connect_bd_net -net axi_usdrx1_gt_rx_data_2 [get_bd_pins axi_ad9671_core_2/rx_data] [get_bd_ports gt_rx_data_2]
connect_bd_net -net axi_usdrx1_gt_rx_data_3 [get_bd_pins axi_ad9671_core_3/rx_data] [get_bd_ports gt_rx_data_3]
connect_bd_net -net axi_ad9671_core_adc_clk [get_bd_pins axi_ad9671_core_0/adc_clk] [get_bd_pins axi_usdrx1_dma/fifo_wr_clk]
connect_bd_net -net axi_ad9671_core_adc_dwr_0 [get_bd_pins axi_ad9671_core_0/adc_dwr] [get_bd_ports adc_dwr_0]
connect_bd_net -net axi_ad9671_core_adc_dwr_1 [get_bd_pins axi_ad9671_core_1/adc_dwr] [get_bd_ports adc_dwr_1]
connect_bd_net -net axi_ad9671_core_adc_dwr_2 [get_bd_pins axi_ad9671_core_2/adc_dwr] [get_bd_ports adc_dwr_2]
connect_bd_net -net axi_ad9671_core_adc_dwr_3 [get_bd_pins axi_ad9671_core_3/adc_dwr] [get_bd_ports adc_dwr_3]
connect_bd_net -net axi_ad9671_core_adc_dsync_0 [get_bd_pins axi_ad9671_core_0/adc_dsync] [get_bd_ports adc_dsync_0]
connect_bd_net -net axi_ad9671_core_adc_dsync_1 [get_bd_pins axi_ad9671_core_1/adc_dsync] [get_bd_ports adc_dsync_1]
connect_bd_net -net axi_ad9671_core_adc_dsync_2 [get_bd_pins axi_ad9671_core_2/adc_dsync] [get_bd_ports adc_dsync_2]
connect_bd_net -net axi_ad9671_core_adc_dsync_3 [get_bd_pins axi_ad9671_core_3/adc_dsync] [get_bd_ports adc_dsync_3]
connect_bd_net -net axi_ad9671_core_adc_ddata_0 [get_bd_pins axi_ad9671_core_0/adc_ddata] [get_bd_ports adc_ddata_0]
connect_bd_net -net axi_ad9671_core_adc_ddata_1 [get_bd_pins axi_ad9671_core_1/adc_ddata] [get_bd_ports adc_ddata_1]
connect_bd_net -net axi_ad9671_core_adc_ddata_2 [get_bd_pins axi_ad9671_core_2/adc_ddata] [get_bd_ports adc_ddata_2]
connect_bd_net -net axi_ad9671_core_adc_ddata_3 [get_bd_pins axi_ad9671_core_3/adc_ddata] [get_bd_ports adc_ddata_3]
connect_bd_net -net axi_ad9671_core_adc_dovf_0 [get_bd_pins axi_ad9671_core_0/adc_dovf] [get_bd_ports adc_dovf_0]
connect_bd_net -net axi_ad9671_core_adc_dovf_1 [get_bd_pins axi_ad9671_core_1/adc_dovf] [get_bd_ports adc_dovf_1]
connect_bd_net -net axi_ad9671_core_adc_dovf_2 [get_bd_pins axi_ad9671_core_2/adc_dovf] [get_bd_ports adc_dovf_2]
connect_bd_net -net axi_ad9671_core_adc_dovf_3 [get_bd_pins axi_ad9671_core_3/adc_dovf] [get_bd_ports adc_dovf_3]
connect_bd_net -net axi_ad9671_dma_adc_dwr [get_bd_pins axi_usdrx1_dma/fifo_wr_en] [get_bd_ports adc_dwr]
connect_bd_net -net axi_ad9671_dma_adc_dsync [get_bd_pins axi_usdrx1_dma/fifo_wr_sync] [get_bd_ports adc_dsync]
connect_bd_net -net axi_ad9671_dma_adc_ddata [get_bd_pins axi_usdrx1_dma/fifo_wr_din] [get_bd_ports adc_ddata]
connect_bd_net -net axi_ad9671_dma_adc_dovf [get_bd_pins axi_usdrx1_dma/fifo_wr_overflow] [get_bd_ports adc_dovf]
connect_bd_net -net axi_usdrx1_dma_irq [get_bd_pins axi_usdrx1_dma/irq] [get_bd_pins sys_concat_intc/In2]
connect_bd_net -net axi_ad9671_gt_rx_rst [get_bd_pins axi_ad9671_gt/rx_rst] [get_bd_pins axi_ad9671_jesd/rx_reset]
connect_bd_net -net axi_ad9671_gt_rx_sysref [get_bd_pins axi_ad9671_jesd/rx_sysref]
connect_bd_net -net axi_ad9671_gt_rx_gt_charisk [get_bd_pins axi_ad9671_gt/rx_gt_charisk] [get_bd_pins axi_ad9671_jesd/gt_rxcharisk_in]
connect_bd_net -net axi_ad9671_gt_rx_gt_disperr [get_bd_pins axi_ad9671_gt/rx_gt_disperr] [get_bd_pins axi_ad9671_jesd/gt_rxdisperr_in]
connect_bd_net -net axi_ad9671_gt_rx_gt_notintable [get_bd_pins axi_ad9671_gt/rx_gt_notintable] [get_bd_pins axi_ad9671_jesd/gt_rxnotintable_in]
connect_bd_net -net axi_ad9671_gt_rx_gt_data [get_bd_pins axi_ad9671_gt/rx_gt_data] [get_bd_pins axi_ad9671_jesd/gt_rxdata_in]
connect_bd_net -net axi_ad9671_gt_rx_rst_done [get_bd_pins axi_ad9671_gt/rx_rst_done] [get_bd_pins axi_ad9671_jesd/rx_reset_done]
connect_bd_net -net axi_ad9671_gt_rx_ip_comma_align [get_bd_pins axi_ad9671_gt/rx_ip_comma_align] [get_bd_pins axi_ad9671_jesd/rxencommaalign_out]
connect_bd_net -net axi_ad9671_gt_rx_ip_sync [get_bd_pins axi_ad9671_gt/rx_ip_sync] [get_bd_pins axi_ad9671_jesd/rx_sync]
connect_bd_net -net axi_ad9671_gt_rx_ip_sof [get_bd_pins axi_ad9671_gt/rx_ip_sof] [get_bd_pins axi_ad9671_jesd/rx_start_of_frame]
connect_bd_net -net axi_ad9671_gt_rx_ip_data [get_bd_pins axi_ad9671_gt/rx_ip_data] [get_bd_pins axi_ad9671_jesd/rx_tdata]
connect_bd_net -net axi_ad9671_gt_rx_data [get_bd_pins axi_ad9671_gt/rx_data] [get_bd_pins axi_ad9671_core/rx_data]
connect_bd_net -net axi_ad9671_core_adc_clk [get_bd_pins axi_ad9671_core/adc_clk] [get_bd_pins axi_ad9671_dma/fifo_wr_clk]
connect_bd_net -net axi_ad9671_core_adc_dwr [get_bd_pins axi_ad9671_core/adc_dwr] [get_bd_pins axi_ad9671_dma/fifo_wr_en]
connect_bd_net -net axi_ad9671_core_adc_dsync [get_bd_pins axi_ad9671_core/adc_dsync] [get_bd_pins axi_ad9671_dma/fifo_wr_sync]
connect_bd_net -net axi_ad9671_core_adc_ddata [get_bd_pins axi_ad9671_core/adc_ddata] [get_bd_pins axi_ad9671_dma/fifo_wr_din]
connect_bd_net -net axi_ad9671_core_adc_dovf [get_bd_pins axi_ad9671_core/adc_dovf] [get_bd_pins axi_ad9671_dma/fifo_wr_overflow]
connect_bd_net -net axi_ad9671_dma_irq [get_bd_pins axi_ad9671_dma/irq] [get_bd_pins sys_concat_intc/In2]
# interconnect (cpu)
connect_bd_intf_net -intf_net axi_cpu_interconnect_m07_axi [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins axi_usdrx1_gt/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m08_axi [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins axi_usdrx1_jesd/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m09_axi [get_bd_intf_pins axi_cpu_interconnect/M09_AXI] [get_bd_intf_pins axi_ad9671_core_0/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m10_axi [get_bd_intf_pins axi_cpu_interconnect/M10_AXI] [get_bd_intf_pins axi_ad9671_core_1/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m11_axi [get_bd_intf_pins axi_cpu_interconnect/M11_AXI] [get_bd_intf_pins axi_ad9671_core_2/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m12_axi [get_bd_intf_pins axi_cpu_interconnect/M12_AXI] [get_bd_intf_pins axi_ad9671_core_3/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m13_axi [get_bd_intf_pins axi_cpu_interconnect/M13_AXI] [get_bd_intf_pins axi_usdrx1_dma/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m14_axi [get_bd_intf_pins axi_cpu_interconnect/M14_AXI] [get_bd_intf_pins axi_usdrx1_spi/axi_lite]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m07_axi [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins axi_ad9671_gt/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m08_axi [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins axi_ad9671_jesd/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m09_axi [get_bd_intf_pins axi_cpu_interconnect/M09_AXI] [get_bd_intf_pins axi_ad9671_core/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m10_axi [get_bd_intf_pins axi_cpu_interconnect/M10_AXI] [get_bd_intf_pins axi_ad9671_dma/s_axi]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M07_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M08_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M09_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M10_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M11_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M12_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M13_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M14_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_gt/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9671_core_0/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9671_core_1/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9671_core_2/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9671_core_3/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_jesd/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_dma/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_spi/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9671_gt/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9671_core/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9671_jesd/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9671_dma/s_axi_aclk]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M07_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M08_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M09_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M10_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M11_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M12_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M13_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M14_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_usdrx1_gt/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9671_core_0/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9671_core_1/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9671_core_2/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9671_core_3/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_usdrx1_jesd/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_usdrx1_dma/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_usdrx1_spi/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9671_gt/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9671_core/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9671_jesd/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9671_dma/s_axi_aresetn]
# interconnect (gt es)
connect_bd_intf_net -intf_net axi_usdrx1_gt_interconnect_s00_axi [get_bd_intf_pins axi_usdrx1_gt_interconnect/S00_AXI] [get_bd_intf_pins axi_usdrx1_gt/m_axi]
connect_bd_intf_net -intf_net axi_usdrx1_gt_interconnect_m00_axi [get_bd_intf_pins axi_usdrx1_gt_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP3]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_gt_interconnect/ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_gt_interconnect/S00_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_gt_interconnect/M00_ACLK] $sys_100m_clk_source
connect_bd_intf_net -intf_net axi_ad9671_gt_interconnect_s00_axi [get_bd_intf_pins axi_ad9671_gt_interconnect/S00_AXI] [get_bd_intf_pins axi_ad9671_gt/m_axi]
connect_bd_intf_net -intf_net axi_ad9671_gt_interconnect_m00_axi [get_bd_intf_pins axi_ad9671_gt_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP3]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9671_gt_interconnect/ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9671_gt_interconnect/S00_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9671_gt_interconnect/M00_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/S_AXI_HP3_ACLK]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_gt/m_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_gt/drp_clk]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_usdrx1_gt_interconnect/ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_usdrx1_gt_interconnect/S00_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_usdrx1_gt_interconnect/M00_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_usdrx1_gt/m_axi_aresetn]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9671_gt/m_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9671_gt/drp_clk]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9671_gt_interconnect/ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9671_gt_interconnect/S00_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9671_gt_interconnect/M00_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9671_gt/m_axi_aresetn]
# interconnect (dma)
@ -250,17 +164,17 @@ set sys_fmc_dma_resetn_source [get_bd_pins sys_ps7/FCLK_RESET2_N]
connect_bd_net -net sys_fmc_dma_clk $sys_fmc_dma_clk_source
connect_bd_net -net sys_fmc_dma_resetn $sys_fmc_dma_resetn_source
connect_bd_intf_net -intf_net axi_usdrx1_dma_interconnect_m00_axi [get_bd_intf_pins axi_usdrx1_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP2]
connect_bd_intf_net -intf_net axi_usdrx1_dma_interconnect_s00_axi [get_bd_intf_pins axi_usdrx1_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_usdrx1_dma/m_dest_axi]
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_usdrx1_dma_interconnect/ACLK] $sys_fmc_dma_clk_source
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_usdrx1_dma_interconnect/S00_ACLK] $sys_fmc_dma_clk_source
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_usdrx1_dma_interconnect/M00_ACLK] $sys_fmc_dma_clk_source
connect_bd_intf_net -intf_net axi_ad9671_dma_interconnect_m00_axi [get_bd_intf_pins axi_ad9671_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP2]
connect_bd_intf_net -intf_net axi_ad9671_dma_interconnect_s00_axi [get_bd_intf_pins axi_ad9671_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_ad9671_dma/m_dest_axi]
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9671_dma_interconnect/ACLK] $sys_fmc_dma_clk_source
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9671_dma_interconnect/S00_ACLK] $sys_fmc_dma_clk_source
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9671_dma_interconnect/M00_ACLK] $sys_fmc_dma_clk_source
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins sys_ps7/S_AXI_HP2_ACLK]
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_usdrx1_dma/m_dest_axi_aclk]
connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_usdrx1_dma_interconnect/ARESETN] $sys_fmc_dma_resetn_source
connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_usdrx1_dma_interconnect/S00_ARESETN] $sys_fmc_dma_resetn_source
connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_usdrx1_dma_interconnect/M00_ARESETN] $sys_fmc_dma_resetn_source
connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_usdrx1_dma/m_dest_axi_aresetn]
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9671_dma/m_dest_axi_aclk]
connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9671_dma_interconnect/ARESETN] $sys_fmc_dma_resetn_source
connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9671_dma_interconnect/S00_ARESETN] $sys_fmc_dma_resetn_source
connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9671_dma_interconnect/M00_ARESETN] $sys_fmc_dma_resetn_source
connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9671_dma/m_dest_axi_aresetn]
# ila
@ -269,24 +183,19 @@ set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_jesd_rx_mon
set_property -dict [list CONFIG.C_PROBE0_WIDTH {662}] $ila_jesd_rx_mon
set_property -dict [list CONFIG.C_PROBE1_WIDTH {10}] $ila_jesd_rx_mon
connect_bd_net -net axi_usdrx1_gt_rx_mon_data [get_bd_pins axi_usdrx1_gt/rx_mon_data]
connect_bd_net -net axi_usdrx1_gt_rx_mon_trigger [get_bd_pins axi_usdrx1_gt/rx_mon_trigger]
connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins ila_jesd_rx_mon/CLK]
connect_bd_net -net axi_usdrx1_gt_rx_mon_data [get_bd_pins ila_jesd_rx_mon/PROBE0]
connect_bd_net -net axi_usdrx1_gt_rx_mon_trigger [get_bd_pins ila_jesd_rx_mon/PROBE1]
connect_bd_net -net axi_ad9671_gt_rx_mon_data [get_bd_pins axi_ad9671_gt/rx_mon_data]
connect_bd_net -net axi_ad9671_gt_rx_mon_trigger [get_bd_pins axi_ad9671_gt/rx_mon_trigger]
connect_bd_net -net axi_ad9671_gt_rx_clk [get_bd_pins ila_jesd_rx_mon/CLK]
connect_bd_net -net axi_ad9671_gt_rx_mon_data [get_bd_pins ila_jesd_rx_mon/PROBE0]
connect_bd_net -net axi_ad9671_gt_rx_mon_trigger [get_bd_pins ila_jesd_rx_mon/PROBE1]
# address map
create_bd_addr_seg -range 0x00010000 -offset 0x44A00000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9671_core_0/s_axi/axi_lite] SEG_data_ad9671_core_0
create_bd_addr_seg -range 0x00010000 -offset 0x44A10000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9671_core_1/s_axi/axi_lite] SEG_data_ad9671_core_1
create_bd_addr_seg -range 0x00010000 -offset 0x44A20000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9671_core_2/s_axi/axi_lite] SEG_data_ad9671_core_2
create_bd_addr_seg -range 0x00010000 -offset 0x44A30000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9671_core_3/s_axi/axi_lite] SEG_data_ad9671_core_3
create_bd_addr_seg -range 0x00010000 -offset 0x44A00000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9671_core/s_axi/axi_lite] SEG_data_ad9671_core
create_bd_addr_seg -range 0x00010000 -offset 0x44A60000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9671_gt/s_axi/axi_lite] SEG_data_ad9671_gt
create_bd_addr_seg -range 0x00001000 -offset 0x44A91000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9671_jesd/s_axi/Reg] SEG_data_ad9671_jesd
create_bd_addr_seg -range 0x00010000 -offset 0x7c400000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9671_dma/s_axi/axi_lite] SEG_data_ad9671_dma
create_bd_addr_seg -range 0x00010000 -offset 0x44A60000 $sys_addr_cntrl_space [get_bd_addr_segs axi_usdrx1_gt/s_axi/axi_lite] SEG_data_usdrx1_gt
create_bd_addr_seg -range 0x00001000 -offset 0x44A91000 $sys_addr_cntrl_space [get_bd_addr_segs axi_usdrx1_jesd/s_axi/Reg] SEG_data_usdrx1_jesd
create_bd_addr_seg -range 0x00010000 -offset 0x7c400000 $sys_addr_cntrl_space [get_bd_addr_segs axi_usdrx1_dma/s_axi/axi_lite] SEG_data_usdrx1_dma
create_bd_addr_seg -range 0x00010000 -offset 0x7c420000 $sys_addr_cntrl_space [get_bd_addr_segs axi_usdrx1_spi/axi_lite/Reg] SEG_data_usdrx1_spi
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_usdrx1_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_sys_ps7_hp2_ddr_lowocm
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_usdrx1_gt/m_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_sys_ps7_hp3_ddr_lowocm
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9671_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_sys_ps7_hp2_ddr_lowocm
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9671_gt/m_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_sys_ps7_hp3_ddr_lowocm

138
projects/ad9671_fmc/common/ad9671_fmc_spi.v Executable file
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@ -0,0 +1,138 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad9671_fmc_spi (
spi_ad9671_csn,
spi_ad9516_csn,
spi_ad9553_csn,
spi_clk,
spi_mosi,
spi_miso,
spi_ad9671_sdio,
spi_ad9516_sdio,
spi_ad9553_sdio);
// 4 wire
input spi_ad9671_csn;
input spi_ad9516_csn;
input spi_ad9553_csn;
input spi_clk;
input spi_mosi;
output spi_miso;
// 3 wire
inout spi_ad9671_sdio;
inout spi_ad9516_sdio;
input spi_ad9553_sdio;
// internal registers
reg [ 5:0] spi_count = 'd0;
reg spi_rd_wr_n = 'd0;
reg spi_enable = 'd0;
// internal signals
wire spi_csn_s;
wire spi_enable_s;
wire spi_ad9516_miso_s;
wire spi_ad9671_miso_s;
wire spi_ad9553_miso_s;
// check on rising edge and change on falling edge
assign spi_csn_s = spi_ad9553_csn & spi_ad9516_csn & spi_ad9671_csn;
assign spi_enable_s = spi_enable & ~spi_csn_s;
always @(posedge spi_clk or posedge spi_csn_s) begin
if (spi_csn_s == 1'b1) begin
spi_count <= 6'd0;
spi_rd_wr_n <= 1'd0;
end else begin
spi_count <= spi_count + 1'b1;
if (spi_count == 6'd0) begin
spi_rd_wr_n <= spi_mosi;
end
end
end
always @(negedge spi_clk or posedge spi_csn_s) begin
if (spi_csn_s == 1'b1) begin
spi_enable <= 1'b0;
end else begin
if (((spi_count == 6'd16) && (spi_ad9671_csn == 1'b0)) ||
((spi_count == 6'd16) && (spi_ad9516_csn == 1'b0)) ||
((spi_count == 6'd16) && (spi_ad9553_csn == 1'b0))) begin
spi_enable <= spi_rd_wr_n;
end
end
end
assign spi_miso = ((spi_ad9671_miso_s & ~spi_ad9671_csn) |
(spi_ad9516_miso_s & ~spi_ad9516_csn) |
(spi_ad9553_miso_s & ~spi_ad9553_csn));
// io buffers
IOBUF i_iobuf_ad9671_sdio (
.T (spi_enable_s),
.I (spi_mosi),
.O (spi_ad9671_miso_s),
.IO (spi_ad9671_sdio));
IOBUF i_iobuf_ad9516_sdio (
.T (spi_enable_s),
.I (spi_mosi),
.O (spi_ad9516_miso_s),
.IO (spi_ad9516_sdio));
IOBUF i_iobuf_clk_sdio (
.T (spi_enable_s),
.I (spi_mosi),
.O (spi_ad9553_miso_s),
.IO (spi_ad9553_sdio));
endmodule
// ***************************************************************************
// ***************************************************************************

2
projects/ad9671_fmc/zc706/system_bd.tcl
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@ -1,4 +1,4 @@
source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
source ../common/usdrx1_bd.tcl
source ../common/ad9671_fmc_bd.tcl

113
projects/ad9671_fmc/zc706/system_constr.xdc
View File

@ -4,94 +4,51 @@
set_property -dict {PACKAGE_PIN AD10} [get_ports rx_ref_clk_p] ; ## D04 FMC_HPC_GBTCLK0_M2C_P
set_property -dict {PACKAGE_PIN AD9} [get_ports rx_ref_clk_n] ; ## D05 FMC_HPC_GBTCLK0_M2C_N
set_property -dict {PACKAGE_PIN AH10} [get_ports rx_data_p[0]] ; ## C06 FMC_HPC_DP0_M2C_P
set_property -dict {PACKAGE_PIN AH9} [get_ports rx_data_n[0]] ; ## C07 FMC_HPC_DP0_M2C_N
set_property -dict {PACKAGE_PIN AJ8} [get_ports rx_data_p[1]] ; ## A02 FMC_HPC_DP1_M2C_P
set_property -dict {PACKAGE_PIN AJ7} [get_ports rx_data_n[1]] ; ## A03 FMC_HPC_DP1_M2C_N
set_property -dict {PACKAGE_PIN AE8} [get_ports rx_data_p[0]] ; ## A10 FMC_HPC_DP3_M2C_P
set_property -dict {PACKAGE_PIN AE7} [get_ports rx_data_n[0]] ; ## A11 FMC_HPC_DP3_M2C_N
set_property -dict {PACKAGE_PIN AH10} [get_ports rx_data_p[1]] ; ## C06 FMC_HPC_DP0_M2C_P
set_property -dict {PACKAGE_PIN AH9} [get_ports rx_data_n[1]] ; ## C07 FMC_HPC_DP0_M2C_N
set_property -dict {PACKAGE_PIN AG8} [get_ports rx_data_p[2]] ; ## A06 FMC_HPC_DP2_M2C_P
set_property -dict {PACKAGE_PIN AG7} [get_ports rx_data_n[2]] ; ## A07 FMC_HPC_DP2_M2C_N
set_property -dict {PACKAGE_PIN AE8} [get_ports rx_data_p[3]] ; ## A10 FMC_HPC_DP3_M2C_P
set_property -dict {PACKAGE_PIN AE7} [get_ports rx_data_n[3]] ; ## A11 FMC_HPC_DP3_M2C_N
set_property -dict {PACKAGE_PIN AH6} [get_ports rx_data_p[4]] ; ## A14 FMC_HPC_DP4_M2C_P
set_property -dict {PACKAGE_PIN AH5} [get_ports rx_data_n[4]] ; ## A15 FMC_HPC_DP4_M2C_N
set_property -dict {PACKAGE_PIN AG4} [get_ports rx_data_p[5]] ; ## A18 FMC_HPC_DP5_M2C_P
set_property -dict {PACKAGE_PIN AG3} [get_ports rx_data_n[5]] ; ## A19 FMC_HPC_DP5_M2C_N
set_property -dict {PACKAGE_PIN AF6} [get_ports rx_data_p[6]] ; ## B16 FMC_HPC_DP6_M2C_P
set_property -dict {PACKAGE_PIN AF5} [get_ports rx_data_n[6]] ; ## B17 FMC_HPC_DP6_M2C_N
set_property -dict {PACKAGE_PIN AD6} [get_ports rx_data_p[7]] ; ## B12 FMC_HPC_DP7_M2C_P
set_property -dict {PACKAGE_PIN AD5} [get_ports rx_data_n[7]] ; ## B13 FMC_HPC_DP7_M2C_N
set_property -dict {PACKAGE_PIN P25 IOSTANDARD LVDS_25} [get_ports rx_sysref_p] ; ## D23 FMC_HPC_LA23_P
set_property -dict {PACKAGE_PIN P26 IOSTANDARD LVDS_25} [get_ports rx_sysref_n] ; ## D24 FMC_HPC_LA23_N
set_property -dict {PACKAGE_PIN R28 IOSTANDARD LVDS_25} [get_ports rx_sync_p] ; ## D26 FMC_HPC_LA26_P
set_property -dict {PACKAGE_PIN T28 IOSTANDARD LVDS_25} [get_ports rx_sync_n] ; ## D27 FMC_HPC_LA26_N
set_property -dict {PACKAGE_PIN V23 IOSTANDARD LVDS_25} [get_ports afe_mlo_p] ; ## D20 FMC_HPC_LA17_CC_P
set_property -dict {PACKAGE_PIN W24 IOSTANDARD LVDS_25} [get_ports afe_mlo_n] ; ## D21 FMC_HPC_LA17_CC_N
set_property -dict {PACKAGE_PIN T29 IOSTANDARD LVDS_25} [get_ports afe_rst_p] ; ## G27 FMC_HPC_LA25_P
set_property -dict {PACKAGE_PIN U29 IOSTANDARD LVDS_25} [get_ports afe_rst_n] ; ## G28 FMC_HPC_LA25_N
set_property -dict {PACKAGE_PIN T30 IOSTANDARD LVDS_25} [get_ports afe_trig_p] ; ## H28 FMC_HPC_LA24_P
set_property -dict {PACKAGE_PIN U30 IOSTANDARD LVDS_25} [get_ports afe_trig_n] ; ## H29 FMC_HPC_LA24_N
set_property -dict {PACKAGE_PIN AJ8} [get_ports rx_data_p[3]] ; ## A02 FMC_HPC_DP1_M2C_P
set_property -dict {PACKAGE_PIN AJ7} [get_ports rx_data_n[3]] ; ## A03 FMC_HPC_DP1_M2C_N
set_property -dict {PACKAGE_PIN AH23 IOSTANDARD LVDS_25} [get_ports rx_sysref_p] ; ## D11 FMC_HPC_LA05_P
set_property -dict {PACKAGE_PIN AH24 IOSTANDARD LVDS_25} [get_ports rx_sysref_n] ; ## D12 FMC_HPC_LA05_N
set_property -dict {PACKAGE_PIN AJ20 IOSTANDARD LVDS_25} [get_ports rx_sync_p] ; ## H10 FMC_HPC_LA04_P
set_property -dict {PACKAGE_PIN AK20 IOSTANDARD LVDS_25} [get_ports rx_sync_n] ; ## H11 FMC_HPC_LA04_N
set_property -dict {PACKAGE_PIN AG24 IOSTANDARD LVCMOS25} [get_ports spi_fout_enb_clk] ; ## C14 FMC_HPC_LA10_P
set_property -dict {PACKAGE_PIN AG25 IOSTANDARD LVCMOS25} [get_ports spi_fout_enb_mlo] ; ## C15 FMC_HPC_LA10_N
set_property -dict {PACKAGE_PIN AC24 IOSTANDARD LVCMOS25} [get_ports spi_fout_enb_rst] ; ## C18 FMC_HPC_LA14_P
set_property -dict {PACKAGE_PIN AD24 IOSTANDARD LVCMOS25} [get_ports spi_fout_enb_sync] ; ## C19 FMC_HPC_LA14_N
set_property -dict {PACKAGE_PIN W25 IOSTANDARD LVCMOS25} [get_ports spi_fout_enb_sysref] ; ## C22 FMC_HPC_LA18_CC_P
set_property -dict {PACKAGE_PIN W26 IOSTANDARD LVCMOS25} [get_ports spi_fout_enb_trig] ; ## C23 FMC_HPC_LA18_CC_N
set_property -dict {PACKAGE_PIN AG22 IOSTANDARD LVCMOS25} [get_ports spi_fout_clk] ; ## C10 FMC_HPC_LA06_P
set_property -dict {PACKAGE_PIN AH22 IOSTANDARD LVCMOS25} [get_ports spi_fout_sdio] ; ## C11 FMC_HPC_LA06_N
set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVCMOS25} [get_ports reset_ad9516] ; ## G15 FMC_HPC_LA12_P
set_property -dict {PACKAGE_PIN V29 IOSTANDARD LVCMOS25} [get_ports reset_ad9671] ; ## C27 FMC_HPC_LA27_N
set_property -dict {PACKAGE_PIN AE23 IOSTANDARD LVCMOS25} [get_ports trig] ; ## H17 FMC_HPC_LA11_N
set_property -dict {PACKAGE_PIN AC24 IOSTANDARD LVCMOS25} [get_ports prci_sck] ; ## C18 FMC_HPC_LA14_P
set_property -dict {PACKAGE_PIN AG24 IOSTANDARD LVCMOS25} [get_ports prci_cnv] ; ## C14 FMC_HPC_LA10_P
set_property -dict {PACKAGE_PIN W25 IOSTANDARD LVCMOS25} [get_ports prci_sdo] ; ## C22 FMC_HPC_LA18_CC_P
set_property -dict {PACKAGE_PIN AD24 IOSTANDARD LVCMOS25} [get_ports prcq_sck] ; ## C19 FMC_HPC_LA14_N
set_property -dict {PACKAGE_PIN AG25 IOSTANDARD LVCMOS25} [get_ports prcq_cnv] ; ## C15 FMC_HPC_LA10_N
set_property -dict {PACKAGE_PIN W26 IOSTANDARD LVCMOS25} [get_ports prcq_sdo] ; ## C23 FMC_HPC_LA18_CC_N
set_property -dict {PACKAGE_PIN AH23 IOSTANDARD LVCMOS25} [get_ports spi_afe_csn[0]] ; ## D11 FMC_HPC_LA05_P
set_property -dict {PACKAGE_PIN AH24 IOSTANDARD LVCMOS25} [get_ports spi_afe_csn[1]] ; ## D12 FMC_HPC_LA05_N
set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVCMOS25} [get_ports spi_afe_csn[2]] ; ## D14 FMC_HPC_LA09_P
set_property -dict {PACKAGE_PIN AE21 IOSTANDARD LVCMOS25} [get_ports spi_afe_csn[3]] ; ## D15 FMC_HPC_LA09_N
set_property -dict {PACKAGE_PIN AG21 IOSTANDARD LVCMOS25} [get_ports spi_afe_clk] ; ## D08 FMC_HPC_LA01_CC_P
set_property -dict {PACKAGE_PIN AH21 IOSTANDARD LVCMOS25} [get_ports spi_afe_sdio] ; ## D09 FMC_HPC_LA01_CC_N
set_property -dict {PACKAGE_PIN AJ19 IOSTANDARD LVCMOS25} [get_ports spi_clk_csn] ; ## G10 FMC_HPC_LA03_N
set_property -dict {PACKAGE_PIN AG19 IOSTANDARD LVCMOS25} [get_ports spi_clk_clk] ; ## G13 FMC_HPC_LA08_N
set_property -dict {PACKAGE_PIN AF19 IOSTANDARD LVCMOS25} [get_ports spi_clk_sdio] ; ## G12 FMC_HPC_LA08_P
set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVCMOS25} [get_ports afe_pdn] ; ## D17 FMC_HPC_LA13_P
set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVCMOS25} [get_ports afe_stby] ; ## D18 FMC_HPC_LA13_N
set_property -dict {PACKAGE_PIN AF24 IOSTANDARD LVCMOS25} [get_ports clk_resetn] ; ## G16 FMC_HPC_LA12_N
set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVCMOS25} [get_ports clk_syncn] ; ## G15 FMC_HPC_LA12_P
set_property -dict {PACKAGE_PIN AA24 IOSTANDARD LVCMOS25} [get_ports clk_status] ; ## G18 FMC_HPC_LA16_P
set_property -dict {PACKAGE_PIN AB24 IOSTANDARD LVCMOS25} [get_ports amp_disbn] ; ## G19 FMC_HPC_LA16_N
set_property -dict {PACKAGE_PIN U25 IOSTANDARD LVCMOS25} [get_ports prc_sck] ; ## G21 FMC_HPC_LA20_P
set_property -dict {PACKAGE_PIN V26 IOSTANDARD LVCMOS25} [get_ports prc_cnv] ; ## G22 FMC_HPC_LA20_N
set_property -dict {PACKAGE_PIN V27 IOSTANDARD LVCMOS25} [get_ports prc_sdo_i] ; ## G24 FMC_HPC_LA22_P
set_property -dict {PACKAGE_PIN W28 IOSTANDARD LVCMOS25} [get_ports prc_sdo_q] ; ## G25 FMC_HPC_LA22_N
set_property -dict {PACKAGE_PIN AH19 IOSTANDARD LVCMOS25} [get_ports dac_sleep] ; ## G09 FMC_HPC_LA03_P
set_property -dict {PACKAGE_PIN W30 IOSTANDARD LVCMOS25} [get_ports dac_data[0]] ; ## H26 FMC_HPC_LA21_N
set_property -dict {PACKAGE_PIN W29 IOSTANDARD LVCMOS25} [get_ports dac_data[1]] ; ## H25 FMC_HPC_LA21_P
set_property -dict {PACKAGE_PIN T25 IOSTANDARD LVCMOS25} [get_ports dac_data[2]] ; ## H23 FMC_HPC_LA19_N
set_property -dict {PACKAGE_PIN T24 IOSTANDARD LVCMOS25} [get_ports dac_data[3]] ; ## H22 FMC_HPC_LA19_P
set_property -dict {PACKAGE_PIN Y23 IOSTANDARD LVCMOS25} [get_ports dac_data[4]] ; ## H20 FMC_HPC_LA15_N
set_property -dict {PACKAGE_PIN Y22 IOSTANDARD LVCMOS25} [get_ports dac_data[5]] ; ## H19 FMC_HPC_LA15_P
set_property -dict {PACKAGE_PIN AE23 IOSTANDARD LVCMOS25} [get_ports dac_data[6]] ; ## H17 FMC_HPC_LA11_N
set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVCMOS25} [get_ports dac_data[7]] ; ## H16 FMC_HPC_LA11_P
set_property -dict {PACKAGE_PIN AJ24 IOSTANDARD LVCMOS25} [get_ports dac_data[8]] ; ## H14 FMC_HPC_LA07_N
set_property -dict {PACKAGE_PIN AJ23 IOSTANDARD LVCMOS25} [get_ports dac_data[9]] ; ## H13 FMC_HPC_LA07_P
set_property -dict {PACKAGE_PIN AK20 IOSTANDARD LVCMOS25} [get_ports dac_data[10]] ; ## H11 FMC_HPC_LA04_N
set_property -dict {PACKAGE_PIN AJ20 IOSTANDARD LVCMOS25} [get_ports dac_data[11]] ; ## H10 FMC_HPC_LA04_P
set_property -dict {PACKAGE_PIN AK18 IOSTANDARD LVCMOS25} [get_ports dac_data[12]] ; ## H08 FMC_HPC_LA02_N
set_property -dict {PACKAGE_PIN AK17 IOSTANDARD LVCMOS25} [get_ports dac_data[13]] ; ## H07 FMC_HPC_LA02_P
set_property -dict {PACKAGE_PIN AK18 IOSTANDARD LVCMOS25} [get_ports spi_ad9671_csn] ; ## H08 FMC_HPC_LA02_N
set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVCMOS25} [get_ports spi_ad9671_clk] ; ## D14 FMC_HPC_LA09_P
set_property -dict {PACKAGE_PIN AE21 IOSTANDARD LVCMOS25} [get_ports spi_ad9671_sdio] ; ## D15 FMC_HPC_LA09_N
set_property -dict {PACKAGE_PIN AH19 IOSTANDARD LVCMOS25} [get_ports spi_ad9516_csn] ; ## G09 FMC_HPC_LA03_P
set_property -dict {PACKAGE_PIN AF19 IOSTANDARD LVCMOS25} [get_ports spi_ad9516_clk] ; ## G12 FMC_HPC_LA08_P
set_property -dict {PACKAGE_PIN AG19 IOSTANDARD LVCMOS25} [get_ports spi_ad9516_sdio] ; ## G13 FMC_HPC_LA08_N
set_property -dict {PACKAGE_PIN AJ19 IOSTANDARD LVCMOS25} [get_ports spi_ad9553_csn] ; ## G10 FMC_HPC_LA03_N
set_property -dict {PACKAGE_PIN AK17 IOSTANDARD LVCMOS25} [get_ports spi_ad9553_clk] ; ## H07 FMC_HPC_LA02_P
set_property -dict {PACKAGE_PIN AJ23 IOSTANDARD LVCMOS25} [get_ports spi_ad9553_sdio] ; ## H13 FMC_HPC_LA07_P
# clocks
create_clock -name rx_ref_clk -period 12.50 [get_ports rx_ref_clk_p]
create_clock -name rx_div_clk -period 12.50 [get_nets i_system_wrapper/system_i/axi_usdrx1_gt_rx_clk]
create_clock -name rx_div_clk -period 12.50 [get_nets i_system_wrapper/system_i/axi_ad9671_gt_rx_clk]
create_clock -name fmc_dma_clk -period 5.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK2]
create_clock -name mlo_clk -period 25.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK3]
set_clock_groups -asynchronous -group {rx_div_clk}
set_clock_groups -asynchronous -group {fmc_dma_clk}
set_false_path -through [get_pins i_system_wrapper/system_i/axi_usdrx1_gt/inst/i_up_gt/i_drp_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_usdrx1_gt/inst/i_up_gt/i_gt_pll_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_usdrx1_gt/inst/i_up_gt/i_gt_rx_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_usdrx1_gt/inst/i_up_gt/i_gt_tx_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_usdrx1_gt/inst/i_up_gt/i_rx_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_usdrx1_gt/inst/i_up_gt/i_tx_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9671_gt/inst/i_up_gt/i_drp_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9671_gt/inst/i_up_gt/i_gt_pll_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9671_gt/inst/i_up_gt/i_gt_rx_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9671_gt/inst/i_up_gt/i_gt_tx_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9671_gt/inst/i_up_gt/i_rx_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9671_gt/inst/i_up_gt/i_tx_rst_reg/i_rst_reg/PRE]

8
projects/ad9671_fmc/zc706/system_project.tcl
View File

@ -4,13 +4,13 @@
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project.tcl
adi_project_create usdrx1_zc706
adi_project_files usdrx1_zc706 [list \
adi_project_create ad9671_fmc_zc706
adi_project_files ad9671_fmc_zc706 [list \
"system_top.v" \
"system_constr.xdc" \
"../common/usdrx1_spi.v" \
"../common/ad9671_fmc_spi.v" \
"$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
adi_project_run usdrx1_zc706
adi_project_run ad9671_fmc_zc706