zcu102: zynq ultrascale
Rejeesh Kutty
parent
0041bf69be
commit
e8fbdd0f5d
|
|
@ -0,0 +1,214 @@
|
|||
|
||||
# create board design
|
||||
# default ports
|
||||
|
||||
create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr
|
||||
create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_main
|
||||
create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 fixed_io
|
||||
|
||||
create_bd_port -dir O spi0_csn_2_o
|
||||
create_bd_port -dir O spi0_csn_1_o
|
||||
create_bd_port -dir O spi0_csn_0_o
|
||||
create_bd_port -dir I spi0_csn_i
|
||||
create_bd_port -dir I spi0_clk_i
|
||||
create_bd_port -dir O spi0_clk_o
|
||||
create_bd_port -dir I spi0_sdo_i
|
||||
create_bd_port -dir O spi0_sdo_o
|
||||
create_bd_port -dir I spi0_sdi_i
|
||||
|
||||
create_bd_port -dir O spi1_csn_2_o
|
||||
create_bd_port -dir O spi1_csn_1_o
|
||||
create_bd_port -dir O spi1_csn_0_o
|
||||
create_bd_port -dir I spi1_csn_i
|
||||
create_bd_port -dir I spi1_clk_i
|
||||
create_bd_port -dir O spi1_clk_o
|
||||
create_bd_port -dir I spi1_sdo_i
|
||||
create_bd_port -dir O spi1_sdo_o
|
||||
create_bd_port -dir I spi1_sdi_i
|
||||
|
||||
create_bd_port -dir I -from 63 -to 0 gpio_i
|
||||
create_bd_port -dir O -from 63 -to 0 gpio_o
|
||||
create_bd_port -dir O -from 63 -to 0 gpio_t
|
||||
|
||||
# hdmi interface
|
||||
|
||||
create_bd_port -dir O hdmi_out_clk
|
||||
create_bd_port -dir O hdmi_hsync
|
||||
create_bd_port -dir O hdmi_vsync
|
||||
create_bd_port -dir O hdmi_data_e
|
||||
create_bd_port -dir O -from 23 -to 0 hdmi_data
|
||||
|
||||
# spdif audio
|
||||
|
||||
create_bd_port -dir O spdif
|
||||
|
||||
# interrupts
|
||||
|
||||
create_bd_port -dir I -type intr ps_intr_00
|
||||
create_bd_port -dir I -type intr ps_intr_01
|
||||
create_bd_port -dir I -type intr ps_intr_02
|
||||
create_bd_port -dir I -type intr ps_intr_03
|
||||
create_bd_port -dir I -type intr ps_intr_04
|
||||
create_bd_port -dir I -type intr ps_intr_05
|
||||
create_bd_port -dir I -type intr ps_intr_06
|
||||
create_bd_port -dir I -type intr ps_intr_07
|
||||
create_bd_port -dir I -type intr ps_intr_08
|
||||
create_bd_port -dir I -type intr ps_intr_09
|
||||
create_bd_port -dir I -type intr ps_intr_10
|
||||
create_bd_port -dir I -type intr ps_intr_11
|
||||
create_bd_port -dir I -type intr ps_intr_12
|
||||
create_bd_port -dir I -type intr ps_intr_13
|
||||
|
||||
# instance: sys_ps7
|
||||
|
||||
set sys_ps7 [create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 sys_ps7]
|
||||
set_property -dict [list CONFIG.preset {ZC706}] $sys_ps7
|
||||
set_property -dict [list CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {0}] $sys_ps7
|
||||
set_property -dict [list CONFIG.PCW_EN_CLK1_PORT {1}] $sys_ps7
|
||||
set_property -dict [list CONFIG.PCW_EN_RST1_PORT {1}] $sys_ps7
|
||||
set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $sys_ps7
|
||||
set_property -dict [list CONFIG.PCW_EN_RST2_PORT {1}] $sys_ps7
|
||||
set_property -dict [list CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100.0}] $sys_ps7
|
||||
set_property -dict [list CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7
|
||||
set_property -dict [list CONFIG.PCW_USE_FABRIC_INTERRUPT {1}] $sys_ps7
|
||||
set_property -dict [list CONFIG.PCW_IRQ_F2P_INTR {1}] $sys_ps7
|
||||
set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1}] $sys_ps7
|
||||
set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {64}] $sys_ps7
|
||||
set_property -dict [list CONFIG.PCW_USE_DMA0 {1}] $sys_ps7
|
||||
set_property -dict [list CONFIG.PCW_IRQ_F2P_MODE {REVERSE}] $sys_ps7
|
||||
set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7
|
||||
set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7
|
||||
set_property -dict [list CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {1}] $sys_ps7
|
||||
set_property -dict [list CONFIG.PCW_SPI1_SPI1_IO {EMIO}] $sys_ps7
|
||||
|
||||
set axi_iic_main [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_main]
|
||||
set_property -dict [list CONFIG.USE_BOARD_FLOW {true}] $axi_iic_main
|
||||
set_property -dict [list CONFIG.IIC_BOARD_INTERFACE {Custom}] $axi_iic_main
|
||||
|
||||
set sys_concat_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc]
|
||||
set_property -dict [list CONFIG.NUM_PORTS {16}] $sys_concat_intc
|
||||
|
||||
set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_rstgen]
|
||||
set_property -dict [list CONFIG.C_EXT_RST_WIDTH {1}] $sys_rstgen
|
||||
|
||||
# hdmi peripherals
|
||||
|
||||
set axi_hdmi_clkgen [create_bd_cell -type ip -vlnv analog.com:user:axi_clkgen:1.0 axi_hdmi_clkgen]
|
||||
set axi_hdmi_core [create_bd_cell -type ip -vlnv analog.com:user:axi_hdmi_tx:1.0 axi_hdmi_core]
|
||||
|
||||
set axi_hdmi_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_vdma:6.2 axi_hdmi_dma]
|
||||
set_property -dict [list CONFIG.C_M_AXIS_MM2S_TDATA_WIDTH {64}] $axi_hdmi_dma
|
||||
set_property -dict [list CONFIG.C_USE_MM2S_FSYNC {1}] $axi_hdmi_dma
|
||||
set_property -dict [list CONFIG.C_INCLUDE_S2MM {0}] $axi_hdmi_dma
|
||||
|
||||
# audio peripherals
|
||||
|
||||
set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.2 sys_audio_clkgen]
|
||||
set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen
|
||||
set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen
|
||||
set_property -dict [list CONFIG.USE_LOCKED {false}] $sys_audio_clkgen
|
||||
set_property -dict [list CONFIG.USE_RESET {true} CONFIG.RESET_TYPE {ACTIVE_LOW}] $sys_audio_clkgen
|
||||
|
||||
set axi_spdif_tx_core [create_bd_cell -type ip -vlnv analog.com:user:axi_spdif_tx:1.0 axi_spdif_tx_core]
|
||||
set_property -dict [list CONFIG.DMA_TYPE {1}] $axi_spdif_tx_core
|
||||
set_property -dict [list CONFIG.S_AXI_ADDRESS_WIDTH {16}] $axi_spdif_tx_core
|
||||
|
||||
# system reset/clock definitions
|
||||
|
||||
ad_connect sys_cpu_clk sys_ps7/FCLK_CLK0
|
||||
ad_connect sys_200m_clk sys_ps7/FCLK_CLK1
|
||||
ad_connect sys_cpu_reset sys_rstgen/peripheral_reset
|
||||
ad_connect sys_cpu_resetn sys_rstgen/peripheral_aresetn
|
||||
ad_connect sys_cpu_clk sys_rstgen/slowest_sync_clk
|
||||
ad_connect sys_rstgen/ext_reset_in sys_ps7/FCLK_RESET0_N
|
||||
|
||||
# interface connections
|
||||
|
||||
ad_connect ddr sys_ps7/DDR
|
||||
ad_connect gpio_i sys_ps7/GPIO_I
|
||||
ad_connect gpio_o sys_ps7/GPIO_O
|
||||
ad_connect gpio_t sys_ps7/GPIO_T
|
||||
ad_connect fixed_io sys_ps7/FIXED_IO
|
||||
ad_connect iic_main axi_iic_main/iic
|
||||
ad_connect sys_200m_clk axi_hdmi_clkgen/clk
|
||||
|
||||
# spi connections
|
||||
|
||||
ad_connect spi0_csn_2_o sys_ps7/SPI0_SS2_O
|
||||
ad_connect spi0_csn_1_o sys_ps7/SPI0_SS1_O
|
||||
ad_connect spi0_csn_0_o sys_ps7/SPI0_SS_O
|
||||
ad_connect spi0_csn_i sys_ps7/SPI0_SS_I
|
||||
ad_connect spi0_clk_i sys_ps7/SPI0_SCLK_I
|
||||
ad_connect spi0_clk_o sys_ps7/SPI0_SCLK_O
|
||||
ad_connect spi0_sdo_i sys_ps7/SPI0_MOSI_I
|
||||
ad_connect spi0_sdo_o sys_ps7/SPI0_MOSI_O
|
||||
ad_connect spi0_sdi_i sys_ps7/SPI0_MISO_I
|
||||
|
||||
ad_connect spi1_csn_2_o sys_ps7/SPI1_SS2_O
|
||||
ad_connect spi1_csn_1_o sys_ps7/SPI1_SS1_O
|
||||
ad_connect spi1_csn_0_o sys_ps7/SPI1_SS_O
|
||||
ad_connect spi1_csn_i sys_ps7/SPI1_SS_I
|
||||
ad_connect spi1_clk_i sys_ps7/SPI1_SCLK_I
|
||||
ad_connect spi1_clk_o sys_ps7/SPI1_SCLK_O
|
||||
ad_connect spi1_sdo_i sys_ps7/SPI1_MOSI_I
|
||||
ad_connect spi1_sdo_o sys_ps7/SPI1_MOSI_O
|
||||
ad_connect spi1_sdi_i sys_ps7/SPI1_MISO_I
|
||||
|
||||
# hdmi
|
||||
|
||||
ad_connect sys_cpu_clk axi_hdmi_core/vdma_clk
|
||||
ad_connect sys_cpu_clk axi_hdmi_dma/m_axis_mm2s_aclk
|
||||
ad_connect axi_hdmi_core/hdmi_clk axi_hdmi_clkgen/clk_0
|
||||
ad_connect axi_hdmi_core/hdmi_out_clk hdmi_out_clk
|
||||
ad_connect axi_hdmi_core/hdmi_24_hsync hdmi_hsync
|
||||
ad_connect axi_hdmi_core/hdmi_24_vsync hdmi_vsync
|
||||
ad_connect axi_hdmi_core/hdmi_24_data_e hdmi_data_e
|
||||
ad_connect axi_hdmi_core/hdmi_24_data hdmi_data
|
||||
ad_connect axi_hdmi_core/vdma_valid axi_hdmi_dma/m_axis_mm2s_tvalid
|
||||
ad_connect axi_hdmi_core/vdma_data axi_hdmi_dma/m_axis_mm2s_tdata
|
||||
ad_connect axi_hdmi_core/vdma_ready axi_hdmi_dma/m_axis_mm2s_tready
|
||||
ad_connect axi_hdmi_core/vdma_fs axi_hdmi_dma/mm2s_fsync
|
||||
ad_connect axi_hdmi_core/vdma_fs axi_hdmi_core/vdma_fs_ret
|
||||
|
||||
# spdif audio
|
||||
|
||||
ad_connect sys_cpu_clk axi_spdif_tx_core/DMA_REQ_ACLK
|
||||
ad_connect sys_cpu_clk sys_ps7/DMA0_ACLK
|
||||
ad_connect sys_cpu_resetn axi_spdif_tx_core/DMA_REQ_RSTN
|
||||
ad_connect sys_ps7/DMA0_REQ axi_spdif_tx_core/DMA_REQ
|
||||
ad_connect sys_ps7/DMA0_ACK axi_spdif_tx_core/DMA_ACK
|
||||
ad_connect sys_200m_clk sys_audio_clkgen/clk_in1
|
||||
ad_connect sys_cpu_resetn sys_audio_clkgen/resetn
|
||||
ad_connect sys_audio_clkgen/clk_out1 axi_spdif_tx_core/spdif_data_clk
|
||||
ad_connect spdif axi_spdif_tx_core/spdif_tx_o
|
||||
|
||||
# interrupts
|
||||
|
||||
ad_connect sys_concat_intc/dout sys_ps7/IRQ_F2P
|
||||
ad_connect sys_concat_intc/In15 axi_hdmi_dma/mm2s_introut
|
||||
ad_connect sys_concat_intc/In14 axi_iic_main/iic2intc_irpt
|
||||
ad_connect sys_concat_intc/In13 ps_intr_13
|
||||
ad_connect sys_concat_intc/In12 ps_intr_12
|
||||
ad_connect sys_concat_intc/In11 ps_intr_11
|
||||
ad_connect sys_concat_intc/In10 ps_intr_10
|
||||
ad_connect sys_concat_intc/In9 ps_intr_09
|
||||
ad_connect sys_concat_intc/In8 ps_intr_08
|
||||
ad_connect sys_concat_intc/In7 ps_intr_07
|
||||
ad_connect sys_concat_intc/In6 ps_intr_06
|
||||
ad_connect sys_concat_intc/In5 ps_intr_05
|
||||
ad_connect sys_concat_intc/In4 ps_intr_04
|
||||
ad_connect sys_concat_intc/In3 ps_intr_03
|
||||
ad_connect sys_concat_intc/In2 ps_intr_02
|
||||
ad_connect sys_concat_intc/In1 ps_intr_01
|
||||
ad_connect sys_concat_intc/In0 ps_intr_00
|
||||
|
||||
# interconnects
|
||||
|
||||
ad_cpu_interconnect 0x41600000 axi_iic_main
|
||||
ad_cpu_interconnect 0x79000000 axi_hdmi_clkgen
|
||||
ad_cpu_interconnect 0x43000000 axi_hdmi_dma
|
||||
ad_cpu_interconnect 0x70e00000 axi_hdmi_core
|
||||
ad_cpu_interconnect 0x75c00000 axi_spdif_tx_core
|
||||
ad_mem_hp0_interconnect sys_cpu_clk sys_ps7/S_AXI_HP0
|
||||
ad_mem_hp0_interconnect sys_cpu_clk axi_hdmi_dma/M_AXI_MM2S
|
||||
|
||||
|
|
@ -0,0 +1,63 @@
|
|||
|
||||
# constraints
|
||||
|
||||
# hdmi
|
||||
|
||||
set_property -dict {PACKAGE_PIN P28 IOSTANDARD LVCMOS25} [get_ports hdmi_out_clk]
|
||||
set_property -dict {PACKAGE_PIN U21 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_vsync]
|
||||
set_property -dict {PACKAGE_PIN R22 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_hsync]
|
||||
set_property -dict {PACKAGE_PIN V24 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_data_e]
|
||||
set_property -dict {PACKAGE_PIN U24 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_data[0]]
|
||||
set_property -dict {PACKAGE_PIN T22 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_data[1]]
|
||||
set_property -dict {PACKAGE_PIN R23 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_data[2]]
|
||||
set_property -dict {PACKAGE_PIN AA25 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_data[3]]
|
||||
set_property -dict {PACKAGE_PIN AE28 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_data[4]]
|
||||
set_property -dict {PACKAGE_PIN T23 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_data[5]]
|
||||
set_property -dict {PACKAGE_PIN AB25 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_data[6]]
|
||||
set_property -dict {PACKAGE_PIN T27 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_data[7]]
|
||||
set_property -dict {PACKAGE_PIN AD26 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_data[8]]
|
||||
set_property -dict {PACKAGE_PIN AB26 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_data[9]]
|
||||
set_property -dict {PACKAGE_PIN AA28 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_data[10]]
|
||||
set_property -dict {PACKAGE_PIN AC26 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_data[11]]
|
||||
set_property -dict {PACKAGE_PIN AE30 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_data[12]]
|
||||
set_property -dict {PACKAGE_PIN Y25 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_data[13]]
|
||||
set_property -dict {PACKAGE_PIN AA29 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_data[14]]
|
||||
set_property -dict {PACKAGE_PIN AD30 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_data[15]]
|
||||
set_property -dict {PACKAGE_PIN Y28 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_data[16]]
|
||||
set_property -dict {PACKAGE_PIN AF28 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_data[17]]
|
||||
set_property -dict {PACKAGE_PIN V22 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_data[18]]
|
||||
set_property -dict {PACKAGE_PIN AA27 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_data[19]]
|
||||
set_property -dict {PACKAGE_PIN U22 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_data[20]]
|
||||
set_property -dict {PACKAGE_PIN N28 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_data[21]]
|
||||
set_property -dict {PACKAGE_PIN V21 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_data[22]]
|
||||
set_property -dict {PACKAGE_PIN AC22 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_data[23]]
|
||||
|
||||
# spdif
|
||||
|
||||
set_property -dict {PACKAGE_PIN AC21 IOSTANDARD LVCMOS25} [get_ports spdif]
|
||||
|
||||
# iic
|
||||
|
||||
set_property -dict {PACKAGE_PIN AJ14 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports iic_scl]
|
||||
set_property -dict {PACKAGE_PIN AJ18 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports iic_sda]
|
||||
|
||||
# gpio (switches, leds and such)
|
||||
|
||||
set_property -dict {PACKAGE_PIN AB17 IOSTANDARD LVCMOS25} [get_ports gpio_bd[0]] ; ## GPIO_DIP_SW0
|
||||
set_property -dict {PACKAGE_PIN AC16 IOSTANDARD LVCMOS25} [get_ports gpio_bd[1]] ; ## GPIO_DIP_SW1
|
||||
set_property -dict {PACKAGE_PIN AC17 IOSTANDARD LVCMOS25} [get_ports gpio_bd[2]] ; ## GPIO_DIP_SW2
|
||||
set_property -dict {PACKAGE_PIN AJ13 IOSTANDARD LVCMOS25} [get_ports gpio_bd[3]] ; ## GPIO_DIP_SW3
|
||||
set_property -dict {PACKAGE_PIN AK25 IOSTANDARD LVCMOS25} [get_ports gpio_bd[4]] ; ## GPIO_SW_LEFT
|
||||
set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS15} [get_ports gpio_bd[5]] ; ## GPIO_SW_CENTER
|
||||
set_property -dict {PACKAGE_PIN R27 IOSTANDARD LVCMOS25} [get_ports gpio_bd[6]] ; ## GPIO_SW_RIGHT
|
||||
|
||||
set_property -dict {PACKAGE_PIN Y21 IOSTANDARD LVCMOS25} [get_ports gpio_bd[7]] ; ## GPIO_LED_LEFT
|
||||
set_property -dict {PACKAGE_PIN G2 IOSTANDARD LVCMOS15} [get_ports gpio_bd[8]] ; ## GPIO_LED_CENTER
|
||||
set_property -dict {PACKAGE_PIN W21 IOSTANDARD LVCMOS25} [get_ports gpio_bd[9]] ; ## GPIO_LED_RIGHT
|
||||
set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVCMOS15} [get_ports gpio_bd[10]] ; ## GPIO_LED_0
|
||||
|
||||
set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS15} [get_ports gpio_bd[11]] ; ## XADC_GPIO_0
|
||||
set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS15} [get_ports gpio_bd[12]] ; ## XADC_GPIO_1
|
||||
set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVCMOS15} [get_ports gpio_bd[13]] ; ## XADC_GPIO_2
|
||||
set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS15} [get_ports gpio_bd[14]] ; ## XADC_GPIO_3
|
||||
|
||||
Loading…
Reference in New Issue