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altera hal version

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Rejeesh Kutty 2014-04-01 21:11:32 -04:00
parent 80e5051894
commit e85153b5dd
4 changed files with 23 additions and 13 deletions
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2
library/axi_ad9250/axi_ad9250_pnmon.v
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@ -177,7 +177,7 @@ module axi_ad9250_pnmon (
// if oos is de-asserted, any spurious mismatches sets the error register.
// ideally, processor should make sure both oos == 0x0 and err == 0x0.
assign adc_pn_data_in_s = {~adc_data[27], adc_data[26:14], ~adc_data[13], adc_data[12:0]};
assign adc_pn_data_in_s = {~adc_data[13], adc_data[12:0], ~adc_data[27], adc_data[26:14]};
assign adc_pn_match_d_1_s = (adc_pn_data_in_s[27:14] == adc_pn_data[27:14]) ? 1'b1 : 1'b0;
assign adc_pn_match_d_0_s = (adc_pn_data_in_s[13: 0] == adc_pn_data[13: 0]) ? 1'b1 : 1'b0;
assign adc_pn_match_z_s = (adc_pn_data_in_s == 28'd0) ? 1'b0 : 1'b1;

12
projects/fmcjesdadc1/a5gt/system_constr.sdc
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@ -7,12 +7,12 @@ create_clock -period "8.000 ns" -name n_eth_tx_clk_125m [get_nets {eth_tx_clk}]
derive_pll_clocks
derive_clock_uncertainty
set clk_100m [get_clocks {i_system|sys_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}]
set clk_166m [get_clocks {i_system|sys_pll|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}]
set clk_125m [get_clocks {i_system|sys_pll|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}]
set clk_25m [get_clocks {i_system|sys_pll|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}]
set clk_2m5 [get_clocks {i_system|sys_pll|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk}]
set clk_rxlink [get_clocks {i_system|sys_jesd204b_s1_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}]
set clk_100m [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}]
set clk_166m [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}]
set clk_125m [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}]
set clk_25m [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}]
set clk_2m5 [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk}]
set clk_rxlink [get_clocks {i_system_bd|sys_jesd204b_s1_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}]
set_false_path -from {sys_resetn} -to *
set_false_path -from $clk_100m -to $clk_166m

8
projects/fmcjesdadc1/a5gt/system_project.tcl
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@ -1,4 +1,6 @@
load_package flow
source ../../scripts/adi_env.tcl
project_new fmcjesdadc1_a5gt -overwrite
@ -7,6 +9,7 @@ set_global_assignment -name DEVICE 5AGTFD7K3F40I5
set_global_assignment -name TOP_LEVEL_ENTITY system_top
set_global_assignment -name SDC_FILE system_constr.sdc
set_global_assignment -name QSYS_FILE system_bd.qsys
set_global_assignment -name QIP_FILE system_adc_mon.qip
set_global_assignment -name VERILOG_FILE $ad_hdl_dir/library/common/altera/ad_jesd_align.v
set_global_assignment -name VERILOG_FILE $ad_hdl_dir/library/common/altera/ad_xcvr_rx_rst.v
set_global_assignment -name VERILOG_FILE ../common/fmcjesdadc1_spi.v
@ -64,8 +67,9 @@ set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_sdio
set_global_assignment -name SYNCHRONIZER_IDENTIFICATION AUTO
set_global_assignment -name ENABLE_ADVANCED_IO_TIMING ON
set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER ON
set_global_assignment -name TIMEQUEST_REPORT_SCRIPT fmcjesdadc1_sta.tcl
set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF
execute_flow --compile
execute_flow -compile

14
projects/fmcjesdadc1/a5gt/system_top.v
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@ -185,13 +185,13 @@ module system_top (
wire adc0_dovf_s;
wire adc0_dwr_s;
wire adc0_mon_valid_s;
wire [119:0] adc0_mon_data_s;
wire [ 55:0] adc0_mon_data_s;
wire [ 63:0] adc1_ddata_s;
wire adc1_dsync_s;
wire adc1_dovf_s;
wire adc1_dwr_s;
wire adc1_mon_valid_s;
wire [119:0] adc1_mon_data_s;
wire [ 55:0] adc1_mon_data_s;
wire [ 3:0] rx_ip_sof_s;
wire [127:0] rx_ip_data_s;
wire [127:0] rx_data_s;
@ -246,13 +246,19 @@ module system_top (
end
endgenerate
assign rx_xcvr_status_s[15:14] = 2'd0;
assign rx_xcvr_status_s[15:15] = 1'd0;
assign rx_xcvr_status_s[14:14] = rx_sync;
assign rx_xcvr_status_s[13:13] = rx_ready_s;
assign rx_xcvr_status_s[12:12] = rx_pll_locked_s;
assign rx_xcvr_status_s[11: 8] = rx_rst_state_s;
assign rx_xcvr_status_s[ 7: 4] = rx_cdr_locked_s;
assign rx_xcvr_status_s[ 3: 0] = rx_cal_busy_s;
system_adc_mon i_adc_mon (
.acq_clk (rx_clk),
.acq_data_in ({adc1_mon_data_s, adc0_mon_data_s}),
.acq_trigger_in ({adc1_mon_valid_s, adc0_mon_valid_s}));
ad_xcvr_rx_rst #(.NUM_OF_LANES (4)) i_xcvr_rx_rst (
.rx_clk (rx_clk),
.rx_rstn (sys_resetn),
@ -275,7 +281,7 @@ module system_top (
.spi3_clk (spi_clk),
.spi3_sdio (spi_sdio));
system i_system (
system_bd i_system_bd (
.sys_clk_clk (sys_clk),
.sys_reset_reset_n (sys_resetn),
.sys_125m_clk_clk (sys_125m_clk),