From e7ce2b200df4457132f5a176679908b07202ddc2 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Thu, 23 Apr 2015 10:17:53 +0300
Subject: [PATCH] axi_ad9122: Added CDC and reset constraints

---
 library/axi_ad9122/axi_ad9122_constr.xdc | 46 ++++++++++++++++++++++--
 library/axi_ad9122/axi_ad9122_ip.tcl     |  1 +
 2 files changed, 45 insertions(+), 2 deletions(-)
 mode change 100755 => 100644 library/axi_ad9122/axi_ad9122_constr.xdc
 mode change 100755 => 100644 library/axi_ad9122/axi_ad9122_ip.tcl

diff --git a/library/axi_ad9122/axi_ad9122_constr.xdc b/library/axi_ad9122/axi_ad9122_constr.xdc
old mode 100755
new mode 100644
index 9a5e6a877..a2aab380d
--- a/library/axi_ad9122/axi_ad9122_constr.xdc
+++ b/library/axi_ad9122/axi_ad9122_constr.xdc
@@ -1,2 +1,44 @@
-set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports dac_clk_in_p]]
-set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports s_axi_aclk]]
+set up_clk [get_clocks -of_objects [get_ports s_axi_aclk]]
+set ad9122_clk [get_clocks -of_objects [get_ports dac_div_clk]]
+
+set_property ASYNC_REG TRUE \
+  [get_cells -hier *toggle_m1_reg*] \
+  [get_cells -hier *toggle_m2_reg*] \
+  [get_cells -hier *state_m1_reg*] \
+  [get_cells -hier *state_m2_reg*]
+
+set_false_path \
+  -from [get_cells -hier up_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
+  -to [get_cells -hier d_xfer_toggle_m1_reg* -filter {primitive_subgroup == flop}]
+set_false_path \
+  -from [get_cells -hier d_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
+  -to [get_cells -hier up_xfer_state_m1_reg* -filter {primitive_subgroup == flop}]
+set_max_delay -datapath_only \
+  -from [get_cells -hier up_xfer_data_reg* -filter {primitive_subgroup == flop}] \
+  -to [get_cells -hier d_data_cntrl_reg* -filter {primitive_subgroup == flop}] \
+  [get_property PERIOD $ad9122_clk]
+
+set_false_path \
+  -from [get_cells -hier d_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
+  -to [get_cells -hier up_xfer_toggle_m1_reg* -filter {primitive_subgroup == flop}]
+set_false_path \
+  -from [get_cells -hier up_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
+  -to [get_cells -hier d_xfer_state_m1_reg* -filter {primitive_subgroup == flop}]
+set_max_delay -datapath_only \
+  -from [get_cells -hier d_xfer_data_reg* -filter {primitive_subgroup == flop}] \
+  -to [get_cells -hier up_data_status_reg* -filter {primitive_subgroup == flop}] \
+  [get_property PERIOD $up_clk]
+
+set_false_path \
+  -from [get_cells -hier up_count_toggle_reg* -filter {primitive_subgroup == flop}] \
+  -to [get_cells -hier d_count_toggle_m1_reg* -filter {primitive_subgroup == flop}]
+set_false_path \
+  -from [get_cells -hier d_count_toggle_reg* -filter {primitive_subgroup == flop}] \
+  -to [get_cells -hier up_count_toggle_m1_reg* -filter {primitive_subgroup == flop}]
+set_max_delay -datapath_only \
+  -from [get_cells -hier d_count_hold_reg* -filter {primitive_subgroup == flop}] \
+  -to [get_cells -hier up_d_count_reg* -filter {primitive_subgroup == flop}] \
+  [get_property PERIOD $up_clk]
+
+set_false_path \
+  -to [get_pins -hier */PRE -filter {NAME =~ *i_*rst_reg*}]
diff --git a/library/axi_ad9122/axi_ad9122_ip.tcl b/library/axi_ad9122/axi_ad9122_ip.tcl
old mode 100755
new mode 100644
index 098eeecfd..512f125e2
--- a/library/axi_ad9122/axi_ad9122_ip.tcl
+++ b/library/axi_ad9122/axi_ad9122_ip.tcl
@@ -27,6 +27,7 @@ adi_ip_files axi_ad9122 [list \
   "axi_ad9122.v" ]
 
 adi_ip_properties axi_ad9122
+
 adi_ip_constraints axi_ad9122 [list \
   "axi_ad9122_constr.xdc" ]