fmcomms2: Added FIFOs for DAC and ADC paths so that the path works at l_clk / 2 or l_clk /4
- removed ILAmain
Adrian Costina
parent
9b29941c77
commit
e77428c50e
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@ -66,6 +66,15 @@ set_property -dict [list CONFIG.DOUT_DATA_WIDTH {16}] $util_ad9361_adc_fifo
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set util_ad9361_tdd_sync [create_bd_cell -type ip -vlnv analog.com:user:util_tdd_sync:1.0 util_ad9361_tdd_sync]
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set util_ad9361_tdd_sync [create_bd_cell -type ip -vlnv analog.com:user:util_tdd_sync:1.0 util_ad9361_tdd_sync]
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set_property -dict [list CONFIG.TDD_SYNC_PERIOD {10000000}] $util_ad9361_tdd_sync
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set_property -dict [list CONFIG.TDD_SYNC_PERIOD {10000000}] $util_ad9361_tdd_sync
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set clkdiv [ create_bd_cell -type ip -vlnv analog.com:user:util_clkdiv:1.0 clkdiv ]
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set clkdiv_reset [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 clkdiv_reset]
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set dac_fifo [create_bd_cell -type ip -vlnv analog.com:user:util_rfifo:1.0 dac_fifo]
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set_property -dict [list CONFIG.DIN_DATA_WIDTH {16}] $dac_fifo
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set_property -dict [list CONFIG.DOUT_DATA_WIDTH {16}] $dac_fifo
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set_property -dict [list CONFIG.DIN_ADDRESS_WIDTH {4}] $dac_fifo
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# connections
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# connections
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ad_connect sys_200m_clk axi_ad9361/delay_clk
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ad_connect sys_200m_clk axi_ad9361/delay_clk
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@ -89,11 +98,6 @@ ad_connect up_enable axi_ad9361/up_enable
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ad_connect up_txnrx axi_ad9361/up_txnrx
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ad_connect up_txnrx axi_ad9361/up_txnrx
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ad_connect axi_ad9361_clk util_ad9361_adc_fifo/din_clk
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ad_connect axi_ad9361_clk util_ad9361_adc_fifo/din_clk
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ad_connect axi_ad9361/rst util_ad9361_adc_fifo/din_rst
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ad_connect axi_ad9361/rst util_ad9361_adc_fifo/din_rst
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ad_connect sys_cpu_clk util_ad9361_adc_fifo/dout_clk
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ad_connect sys_cpu_resetn util_ad9361_adc_fifo/dout_rstn
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ad_connect sys_cpu_clk util_ad9361_adc_pack/adc_clk
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ad_connect sys_cpu_reset util_ad9361_adc_pack/adc_rst
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ad_connect sys_cpu_clk axi_ad9361_adc_dma/fifo_wr_clk
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ad_connect axi_ad9361/adc_enable_i0 util_ad9361_adc_fifo/din_enable_0
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ad_connect axi_ad9361/adc_enable_i0 util_ad9361_adc_fifo/din_enable_0
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ad_connect axi_ad9361/adc_valid_i0 util_ad9361_adc_fifo/din_valid_0
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ad_connect axi_ad9361/adc_valid_i0 util_ad9361_adc_fifo/din_valid_0
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ad_connect axi_ad9361/adc_data_i0 util_ad9361_adc_fifo/din_data_0
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ad_connect axi_ad9361/adc_data_i0 util_ad9361_adc_fifo/din_data_0
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@ -123,24 +127,48 @@ ad_connect util_ad9361_adc_pack/adc_sync axi_ad9361_adc_dma/fifo_wr_sync
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ad_connect util_ad9361_adc_pack/adc_data axi_ad9361_adc_dma/fifo_wr_din
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ad_connect util_ad9361_adc_pack/adc_data axi_ad9361_adc_dma/fifo_wr_din
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ad_connect axi_ad9361_adc_dma/fifo_wr_overflow util_ad9361_adc_fifo/dout_ovf
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ad_connect axi_ad9361_adc_dma/fifo_wr_overflow util_ad9361_adc_fifo/dout_ovf
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ad_connect util_ad9361_adc_fifo/din_ovf axi_ad9361/adc_dovf
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ad_connect util_ad9361_adc_fifo/din_ovf axi_ad9361/adc_dovf
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ad_connect axi_ad9361_clk util_ad9361_dac_upack/dac_clk
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ad_connect axi_ad9361_clk clkdiv/clk
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ad_connect axi_ad9361_clk axi_ad9361_dac_dma/fifo_rd_clk
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ad_connect axi_ad9361/adc_r1_mode clkdiv/clk_sel
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ad_connect util_ad9361_dac_upack/dac_enable_0 axi_ad9361/dac_enable_i0
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ad_connect clkdiv/clk_out axi_ad9361_adc_dma/fifo_wr_clk
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ad_connect util_ad9361_dac_upack/dac_valid_0 axi_ad9361/dac_valid_i0
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ad_connect clkdiv/clk_out util_ad9361_adc_fifo/dout_clk
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ad_connect util_ad9361_dac_upack/dac_data_0 axi_ad9361/dac_data_i0
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ad_connect clkdiv/clk_out util_ad9361_adc_pack/adc_clk
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ad_connect util_ad9361_dac_upack/dac_enable_1 axi_ad9361/dac_enable_q0
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ad_connect clkdiv_reset/ext_reset_in sys_rstgen/peripheral_aresetn
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ad_connect util_ad9361_dac_upack/dac_valid_1 axi_ad9361/dac_valid_q0
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ad_connect clkdiv_reset/slowest_sync_clk clkdiv/clk_out
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ad_connect util_ad9361_dac_upack/dac_data_1 axi_ad9361/dac_data_q0
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ad_connect util_ad9361_adc_pack/adc_rst clkdiv_reset/peripheral_reset
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ad_connect util_ad9361_dac_upack/dac_enable_2 axi_ad9361/dac_enable_i1
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ad_connect util_ad9361_adc_fifo/dout_rstn clkdiv_reset/peripheral_aresetn
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ad_connect util_ad9361_dac_upack/dac_valid_2 axi_ad9361/dac_valid_i1
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ad_connect util_ad9361_dac_upack/dac_data_2 axi_ad9361/dac_data_i1
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ad_connect util_ad9361_dac_upack/dac_enable_3 axi_ad9361/dac_enable_q1
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ad_connect util_ad9361_dac_upack/dac_valid_3 axi_ad9361/dac_valid_q1
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ad_connect util_ad9361_dac_upack/dac_data_3 axi_ad9361/dac_data_q1
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ad_connect util_ad9361_dac_upack/dac_valid axi_ad9361_dac_dma/fifo_rd_en
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ad_connect util_ad9361_dac_upack/dac_valid axi_ad9361_dac_dma/fifo_rd_en
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ad_connect util_ad9361_dac_upack/dac_data axi_ad9361_dac_dma/fifo_rd_dout
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ad_connect util_ad9361_dac_upack/dac_data axi_ad9361_dac_dma/fifo_rd_dout
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ad_connect axi_ad9361_dac_dma/fifo_rd_underflow axi_ad9361/dac_dunf
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ad_connect clkdiv/clk_out axi_ad9361_dac_dma/fifo_rd_clk
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ad_connect axi_ad9361/dac_dunf dac_fifo/dout_unf
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ad_connect dac_fifo/din_clk clkdiv/clk_out
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ad_connect dac_fifo/din_rstn clkdiv_reset/peripheral_aresetn
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ad_connect axi_ad9361_clk dac_fifo/dout_clk
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ad_connect dac_fifo/dout_rst axi_ad9361/rst
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ad_connect util_ad9361_dac_upack/dac_clk clkdiv/clk_out
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ad_connect dac_fifo/din_enable_0 util_ad9361_dac_upack/dac_enable_0
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ad_connect dac_fifo/din_valid_0 util_ad9361_dac_upack/dac_valid_0
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ad_connect dac_fifo/din_enable_1 util_ad9361_dac_upack/dac_enable_1
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ad_connect dac_fifo/din_valid_1 util_ad9361_dac_upack/dac_valid_1
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ad_connect dac_fifo/din_enable_2 util_ad9361_dac_upack/dac_enable_2
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ad_connect dac_fifo/din_valid_2 util_ad9361_dac_upack/dac_valid_2
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ad_connect dac_fifo/din_enable_3 util_ad9361_dac_upack/dac_enable_3
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ad_connect dac_fifo/din_valid_3 util_ad9361_dac_upack/dac_valid_3
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ad_connect util_ad9361_dac_upack/dac_data_0 dac_fifo/din_data_0
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ad_connect util_ad9361_dac_upack/dac_data_1 dac_fifo/din_data_1
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ad_connect util_ad9361_dac_upack/dac_data_2 dac_fifo/din_data_2
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ad_connect util_ad9361_dac_upack/dac_data_3 dac_fifo/din_data_3
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ad_connect axi_ad9361/dac_enable_i0 dac_fifo/dout_enable_0
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ad_connect axi_ad9361/dac_valid_i0 dac_fifo/dout_valid_0
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ad_connect axi_ad9361/dac_enable_q0 dac_fifo/dout_enable_1
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ad_connect axi_ad9361/dac_valid_q0 dac_fifo/dout_valid_1
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ad_connect axi_ad9361/dac_enable_i1 dac_fifo/dout_enable_2
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ad_connect axi_ad9361/dac_valid_i1 dac_fifo/dout_valid_2
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ad_connect axi_ad9361/dac_enable_q1 dac_fifo/dout_enable_3
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ad_connect axi_ad9361/dac_valid_q1 dac_fifo/dout_valid_3
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ad_connect dac_fifo/dout_data_0 axi_ad9361/dac_data_i0
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ad_connect dac_fifo/dout_data_1 axi_ad9361/dac_data_q0
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ad_connect dac_fifo/dout_data_2 axi_ad9361/dac_data_i1
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ad_connect dac_fifo/dout_data_3 axi_ad9361/dac_data_q1
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ad_connect sys_cpu_clk util_ad9361_tdd_sync/clk
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ad_connect sys_cpu_clk util_ad9361_tdd_sync/clk
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ad_connect sys_cpu_resetn util_ad9361_tdd_sync/rstn
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ad_connect sys_cpu_resetn util_ad9361_tdd_sync/rstn
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ad_connect util_ad9361_tdd_sync/sync_out axi_ad9361/tdd_sync
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ad_connect util_ad9361_tdd_sync/sync_out axi_ad9361/tdd_sync
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@ -166,23 +194,3 @@ ad_connect sys_cpu_resetn axi_ad9361_dac_dma/m_src_axi_aresetn
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ad_cpu_interrupt ps-13 mb-12 axi_ad9361_adc_dma/irq
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ad_cpu_interrupt ps-13 mb-12 axi_ad9361_adc_dma/irq
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ad_cpu_interrupt ps-12 mb-13 axi_ad9361_dac_dma/irq
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ad_cpu_interrupt ps-12 mb-13 axi_ad9361_dac_dma/irq
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# ila (adc)
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set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.1 ila_adc]
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set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_adc
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set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_adc
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set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_adc
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set_property -dict [list CONFIG.C_NUM_OF_PROBES {5}] $ila_adc
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set_property -dict [list CONFIG.C_PROBE0_WIDTH {16}] $ila_adc
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set_property -dict [list CONFIG.C_PROBE1_WIDTH {16}] $ila_adc
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set_property -dict [list CONFIG.C_PROBE2_WIDTH {16}] $ila_adc
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set_property -dict [list CONFIG.C_PROBE3_WIDTH {16}] $ila_adc
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set_property -dict [list CONFIG.C_PROBE4_WIDTH {1}] $ila_adc
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ad_connect util_ad9361_adc_fifo/dout_data_0 ila_adc/probe0
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ad_connect util_ad9361_adc_fifo/dout_data_1 ila_adc/probe1
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ad_connect util_ad9361_adc_fifo/dout_data_2 ila_adc/probe2
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ad_connect util_ad9361_adc_fifo/dout_data_3 ila_adc/probe3
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ad_connect util_ad9361_adc_fifo/dout_valid_0 ila_adc/probe4
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ad_connect sys_cpu_clk ila_adc/clk
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