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ad9081_fmca_ebz:vcu128: Initial version 

* 4Txs / 4Rxs per MxFE
 * Tx I/Q Rate: 250 MSPS
 * Rx I/Q Rate: 250 MSPS
 * DAC JESD204B: Mode 9, L=4, M=8, N=N'=16
 * ADC JESD204B: Mode 10, L=4, M=8, N=N'=16
 * DAC-Side JESD204B Lane Rate: 10Gbps
 * ADC-Side JESD204B Lane Rate: 10Gbps
main
Laszlo Nagy 2020-07-07 15:15:28 +01:00 committed by Laszlo Nagy
parent 88b5c2d6db
commit e76f287e73
6 changed files with 736 additions and 0 deletions
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projects/ad9081_fmca_ebz/vcu128/Makefile Normal file
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####################################################################################
## Copyright (c) 2018 - 2021 Analog Devices, Inc.
### SPDX short identifier: BSD-1-Clause
## Auto-generated, do not modify!
####################################################################################
PROJECT_NAME := ad9081_fmca_ebz_vcu128
M_DEPS += timing_constr.xdc
M_DEPS += ../../scripts/adi_pd.tcl
M_DEPS += ../../common/xilinx/data_offload_bd.tcl
M_DEPS += ../../common/xilinx/dacfifo_bd.tcl
M_DEPS += ../../common/xilinx/adcfifo_bd.tcl
M_DEPS += ../../common/vcu128/vcu128_system_constr.xdc
M_DEPS += ../../common/vcu128/vcu128_system_bd.tcl
M_DEPS += ../../ad9081_fmca_ebz/common/versal_transceiver.tcl
M_DEPS += ../../ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl
M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl
M_DEPS += ../../../library/common/ad_iobuf.v
M_DEPS += ../../../library/common/ad_edge_detect.v
M_DEPS += ../../../library/common/ad_3w_spi.v
LIB_DEPS += axi_dmac
LIB_DEPS += axi_sysid
LIB_DEPS += axi_tdd
LIB_DEPS += data_offload
LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc
LIB_DEPS += jesd204/ad_ip_jesd204_tpl_dac
LIB_DEPS += jesd204/axi_jesd204_rx
LIB_DEPS += jesd204/axi_jesd204_tx
LIB_DEPS += jesd204/jesd204_rx
LIB_DEPS += jesd204/jesd204_tx
LIB_DEPS += jesd204/jesd204_versal_gt_adapter_rx
LIB_DEPS += jesd204/jesd204_versal_gt_adapter_tx
LIB_DEPS += sysid_rom
LIB_DEPS += util_adcfifo
LIB_DEPS += util_dacfifo
LIB_DEPS += util_fifo2axi_bridge
LIB_DEPS += util_pack/util_cpack2
LIB_DEPS += util_pack/util_upack2
LIB_DEPS += util_tdd_sync
LIB_DEPS += xilinx/axi_adxcvr
LIB_DEPS += xilinx/util_adxcvr
include ../../scripts/project-xilinx.mk

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projects/ad9081_fmca_ebz/vcu128/system_bd.tcl Normal file
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## ADC FIFO depth in samples per converter
set adc_fifo_samples_per_converter [expr $ad_project_params(RX_KS_PER_CHANNEL)*1024]
## DAC FIFO depth in samples per converter
set dac_fifo_samples_per_converter [expr $ad_project_params(TX_KS_PER_CHANNEL)*1024]
source $ad_hdl_dir/projects/common/vcu128/vcu128_system_bd.tcl
source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl
source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl
source $ad_hdl_dir/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl
source $ad_hdl_dir/projects/scripts/adi_pd.tcl
ad_ip_parameter axi_mxfe_rx_jesd/rx CONFIG.NUM_INPUT_PIPELINE 2
ad_ip_parameter axi_mxfe_tx_jesd/tx CONFIG.NUM_OUTPUT_PIPELINE 1
#system ID
ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt"
ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
sysid_gen_sys_init_file
# Parameters for 15.5Gpbs lane rate
ad_ip_parameter util_mxfe_xcvr CONFIG.RX_CLK25_DIV 31
ad_ip_parameter util_mxfe_xcvr CONFIG.TX_CLK25_DIV 31
ad_ip_parameter util_mxfe_xcvr CONFIG.CPLL_CFG0 0x1fa
ad_ip_parameter util_mxfe_xcvr CONFIG.CPLL_CFG1 0x2b
ad_ip_parameter util_mxfe_xcvr CONFIG.CPLL_CFG2 0x2
ad_ip_parameter util_mxfe_xcvr CONFIG.CPLL_FBDIV 2
ad_ip_parameter util_mxfe_xcvr CONFIG.CH_HSPMUX 0x4040
ad_ip_parameter util_mxfe_xcvr CONFIG.PREIQ_FREQ_BST 1
ad_ip_parameter util_mxfe_xcvr CONFIG.RTX_BUF_CML_CTRL 0x5
ad_ip_parameter util_mxfe_xcvr CONFIG.RXPI_CFG0 0x3002
ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG2 0x1E9
ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3 0x23
ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3_GEN2 0x23
ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3_GEN3 0x23
ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3_GEN4 0x23
ad_ip_parameter util_mxfe_xcvr CONFIG.RX_WIDEMODE_CDR 0x1
ad_ip_parameter util_mxfe_xcvr CONFIG.RX_XMODE_SEL 0x0
ad_ip_parameter util_mxfe_xcvr CONFIG.TXDRV_FREQBAND 1
ad_ip_parameter util_mxfe_xcvr CONFIG.TXFE_CFG1 0xAA00
ad_ip_parameter util_mxfe_xcvr CONFIG.TXFE_CFG2 0xAA00
ad_ip_parameter util_mxfe_xcvr CONFIG.TXFE_CFG3 0xAA00
ad_ip_parameter util_mxfe_xcvr CONFIG.TXPI_CFG0 0x3100
ad_ip_parameter util_mxfe_xcvr CONFIG.TXPI_CFG1 0x0
ad_ip_parameter util_mxfe_xcvr CONFIG.TX_PI_BIASSET 1
ad_ip_parameter util_mxfe_xcvr CONFIG.RXPI_CFG1 0x54
ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_REFCLK_DIV 1
ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_CFG0 0x333c
ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_CFG4 0x2
ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_FBDIV 20
ad_ip_parameter util_mxfe_xcvr CONFIG.PPF0_CFG 0xB00
ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_LPF 0x2ff
# 204C params 16.5Gbps..24.75Gpbs
if {$ad_project_params(JESD_MODE) == "64B66B"} {
# Set higher swing for the diff driver, other case 16.5Gbps won't work
ad_ip_parameter axi_mxfe_tx_xcvr CONFIG.TX_DIFFCTRL 0xC
# Lane rate indepentent parameters
ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3_GEN2 0x12
ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3_GEN3 0x12
ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3_GEN4 0x12
ad_ip_parameter util_mxfe_xcvr CONFIG.RXPI_CFG1 0x0
ad_ip_parameter util_mxfe_xcvr CONFIG.RX_WIDEMODE_CDR 0x2
ad_ip_parameter util_mxfe_xcvr CONFIG.CH_HSPMUX 0x6060
ad_ip_parameter util_mxfe_xcvr CONFIG.PREIQ_FREQ_BST 2
ad_ip_parameter util_mxfe_xcvr CONFIG.TX_PI_BIASSET 2
ad_ip_parameter util_mxfe_xcvr CONFIG.RXDFE_KH_CFG2 0x281C
ad_ip_parameter util_mxfe_xcvr CONFIG.RXDFE_KH_CFG3 0x4120
# Lane rate indepentent QPLL parameters
ad_ip_parameter util_mxfe_xcvr CONFIG.PPF0_CFG 0x600
ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_CFG0 0x331c
# Lane rate dependent QPLL params (these match for 16.5 Gbps and 24.75 Gpbs)
ad_ip_parameter util_mxfe_xcvr CONFIG.PPF1_CFG 0x400
ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_LPF 0x33f
ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_CFG2 0x0FC1
ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_CFG2_G3 0x0FC1
ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_CFG4 0x03
# set dividers for 24.75Gbps, are overwritten by software
ad_ip_parameter util_mxfe_xcvr CONFIG.RX_CLK25_DIV 10
ad_ip_parameter util_mxfe_xcvr CONFIG.TX_CLK25_DIV 10
ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_FBDIV 66
ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_REFCLK_DIV 2
if {$ad_project_params(RX_LANE_RATE) < 20} {
ad_ip_parameter util_mxfe_xcvr CONFIG.RTX_BUF_CML_CTRL 0x5
ad_ip_parameter util_mxfe_xcvr CONFIG.RXPI_CFG0 0x0104
} else {
ad_ip_parameter util_mxfe_xcvr CONFIG.RTX_BUF_CML_CTRL 0x6
ad_ip_parameter util_mxfe_xcvr CONFIG.RXPI_CFG0 0x3004
}
if {$ad_project_params(TX_LANE_RATE) < 20} {
ad_ip_parameter util_mxfe_xcvr CONFIG.TXDRV_FREQBAND 1
ad_ip_parameter util_mxfe_xcvr CONFIG.TXFE_CFG0 0x3C2
ad_ip_parameter util_mxfe_xcvr CONFIG.TXFE_CFG1 0xAA00
ad_ip_parameter util_mxfe_xcvr CONFIG.TXFE_CFG2 0xAA00
ad_ip_parameter util_mxfe_xcvr CONFIG.TXFE_CFG3 0xAA00
ad_ip_parameter util_mxfe_xcvr CONFIG.TXPI_CFG0 0x0100
ad_ip_parameter util_mxfe_xcvr CONFIG.TXPI_CFG1 0x1000
ad_ip_parameter util_mxfe_xcvr CONFIG.TXSWBST_EN 0
} else {
ad_ip_parameter util_mxfe_xcvr CONFIG.TXDRV_FREQBAND 3
ad_ip_parameter util_mxfe_xcvr CONFIG.TXFE_CFG0 0x3C6
ad_ip_parameter util_mxfe_xcvr CONFIG.TXFE_CFG1 0xF800
ad_ip_parameter util_mxfe_xcvr CONFIG.TXFE_CFG2 0xF800
ad_ip_parameter util_mxfe_xcvr CONFIG.TXFE_CFG3 0xF800
ad_ip_parameter util_mxfe_xcvr CONFIG.TXPI_CFG0 0x3000
ad_ip_parameter util_mxfe_xcvr CONFIG.TXPI_CFG1 0x0
ad_ip_parameter util_mxfe_xcvr CONFIG.TXSWBST_EN 1
}
}

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#
## mxfe
#
set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS18 } [get_ports agc0[0] ] ; ## IO_L13P_T2L_N0_GC_QBC_71
set_property -dict {PACKAGE_PIN E17 IOSTANDARD LVCMOS18 } [get_ports agc0[1] ] ; ## IO_L13N_T2L_N1_GC_QBC_71
set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS18 } [get_ports agc1[0] ] ; ## IO_L14P_T2L_N2_GC_71
set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS18 } [get_ports agc1[1] ] ; ## IO_L14N_T2L_N3_GC_71
set_property -dict {PACKAGE_PIN A21 IOSTANDARD LVCMOS18 } [get_ports agc2[0] ] ; ## IO_L22P_T3U_N6_DBC_AD0P_71
set_property -dict {PACKAGE_PIN A20 IOSTANDARD LVCMOS18 } [get_ports agc2[1] ] ; ## IO_L22N_T3U_N7_DBC_AD0N_71
set_property -dict {PACKAGE_PIN A19 IOSTANDARD LVCMOS18 } [get_ports agc3[0] ] ; ## IO_L23P_T3U_N8_71
set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVCMOS18 } [get_ports agc3[1] ] ; ## IO_L23N_T3U_N9_71
set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVDS } [get_ports clkin6_n ] ; ## IO_L11N_T1U_N9_GC_71
set_property -dict {PACKAGE_PIN G18 IOSTANDARD LVDS } [get_ports clkin6_p ] ; ## IO_L11P_T1U_N8_GC_71
set_property -dict {PACKAGE_PIN AR41 } [get_ports clkin8_n ] ; ## MGTREFCLK0N_125
set_property -dict {PACKAGE_PIN AR40 } [get_ports clkin8_p ] ; ## MGTREFCLK0P_125
set_property -dict {PACKAGE_PIN AV43 } [get_ports fpga_refclk_in_n ] ; ## MGTREFCLK0N_124
set_property -dict {PACKAGE_PIN AV42 } [get_ports fpga_refclk_in_p ] ; ## MGTREFCLK0P_124
set_property -quiet -dict {PACKAGE_PIN BA54 } [get_ports rx_data_n[2] ] ; ## MGTYRXN2_124 FPGA_SERDIN_0_N
set_property -quiet -dict {PACKAGE_PIN BA53 } [get_ports rx_data_p[2] ] ; ## MGTYRXP2_124 FPGA_SERDIN_0_P
set_property -quiet -dict {PACKAGE_PIN BC54 } [get_ports rx_data_n[0] ] ; ## MGTYRXN0_124 FPGA_SERDIN_1_N
set_property -quiet -dict {PACKAGE_PIN BC53 } [get_ports rx_data_p[0] ] ; ## MGTYRXP0_124 FPGA_SERDIN_1_P
set_property -quiet -dict {PACKAGE_PIN AV52 } [get_ports rx_data_n[7] ] ; ## MGTYRXN3_125 FPGA_SERDIN_2_N
set_property -quiet -dict {PACKAGE_PIN AV51 } [get_ports rx_data_p[7] ] ; ## MGTYRXP3_125 FPGA_SERDIN_2_P
set_property -quiet -dict {PACKAGE_PIN AW50 } [get_ports rx_data_n[6] ] ; ## MGTYRXN2_125 FPGA_SERDIN_3_N
set_property -quiet -dict {PACKAGE_PIN AW49 } [get_ports rx_data_p[6] ] ; ## MGTYRXP2_125 FPGA_SERDIN_3_P
set_property -quiet -dict {PACKAGE_PIN AW54 } [get_ports rx_data_n[5] ] ; ## MGTYRXN1_125 FPGA_SERDIN_4_N
set_property -quiet -dict {PACKAGE_PIN AW53 } [get_ports rx_data_p[5] ] ; ## MGTYRXP1_125 FPGA_SERDIN_4_P
set_property -quiet -dict {PACKAGE_PIN AY52 } [get_ports rx_data_n[4] ] ; ## MGTYRXN0_125 FPGA_SERDIN_5_N
set_property -quiet -dict {PACKAGE_PIN AY51 } [get_ports rx_data_p[4] ] ; ## MGTYRXP0_125 FPGA_SERDIN_5_P
set_property -quiet -dict {PACKAGE_PIN BA50 } [get_ports rx_data_n[3] ] ; ## MGTYRXN3_124 FPGA_SERDIN_6_N
set_property -quiet -dict {PACKAGE_PIN BA49 } [get_ports rx_data_p[3] ] ; ## MGTYRXP3_124 FPGA_SERDIN_6_P
set_property -quiet -dict {PACKAGE_PIN BB52 } [get_ports rx_data_n[1] ] ; ## MGTYRXN1_124 FPGA_SERDIN_7_N
set_property -quiet -dict {PACKAGE_PIN BB51 } [get_ports rx_data_p[1] ] ; ## MGTYRXP1_124 FPGA_SERDIN_7_P
set_property -quiet -dict {PACKAGE_PIN BC49 } [get_ports tx_data_n[0] ] ; ## MGTYTXN0_124 FPGA_SERDOUT_0_N
set_property -quiet -dict {PACKAGE_PIN BC48 } [get_ports tx_data_p[0] ] ; ## MGTYTXP0_124 FPGA_SERDOUT_0_P
set_property -quiet -dict {PACKAGE_PIN BB47 } [get_ports tx_data_n[2] ] ; ## MGTYTXN2_124 FPGA_SERDOUT_1_N
set_property -quiet -dict {PACKAGE_PIN BB46 } [get_ports tx_data_p[2] ] ; ## MGTYTXP2_124 FPGA_SERDOUT_1_P
set_property -quiet -dict {PACKAGE_PIN AU45 } [get_ports tx_data_n[7] ] ; ## MGTYTXN3_125 FPGA_SERDOUT_2_N
set_property -quiet -dict {PACKAGE_PIN AU44 } [get_ports tx_data_p[7] ] ; ## MGTYTXP3_125 FPGA_SERDOUT_2_P
set_property -quiet -dict {PACKAGE_PIN AV47 } [get_ports tx_data_n[6] ] ; ## MGTYTXN2_125 FPGA_SERDOUT_3_N
set_property -quiet -dict {PACKAGE_PIN AV46 } [get_ports tx_data_p[6] ] ; ## MGTYTXP2_125 FPGA_SERDOUT_3_P
set_property -quiet -dict {PACKAGE_PIN BC45 } [get_ports tx_data_n[1] ] ; ## MGTYTXN1_124 FPGA_SERDOUT_4_N
set_property -quiet -dict {PACKAGE_PIN BC44 } [get_ports tx_data_p[1] ] ; ## MGTYTXP1_124 FPGA_SERDOUT_4_P
set_property -quiet -dict {PACKAGE_PIN AW45 } [get_ports tx_data_n[5] ] ; ## MGTYTXN1_125 FPGA_SERDOUT_5_N
set_property -quiet -dict {PACKAGE_PIN AW44 } [get_ports tx_data_p[5] ] ; ## MGTYTXP1_125 FPGA_SERDOUT_5_P
set_property -quiet -dict {PACKAGE_PIN AY47 } [get_ports tx_data_n[4] ] ; ## MGTYTXN0_125 FPGA_SERDOUT_6_N
set_property -quiet -dict {PACKAGE_PIN AY46 } [get_ports tx_data_p[4] ] ; ## MGTYTXP0_125 FPGA_SERDOUT_6_P
set_property -quiet -dict {PACKAGE_PIN BA45 } [get_ports tx_data_n[3] ] ; ## MGTYTXN3_124 FPGA_SERDOUT_7_N
set_property -quiet -dict {PACKAGE_PIN BA44 } [get_ports tx_data_p[3] ] ; ## MGTYTXP3_124 FPGA_SERDOUT_7_P
set_property -quiet -dict {PACKAGE_PIN K22 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports fpga_syncin_n[0] ] ; ## IO_L4N_T0U_N7_DBC_AD7N_72
set_property -quiet -dict {PACKAGE_PIN L23 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports fpga_syncin_p[0] ] ; ## IO_L4P_T0U_N6_DBC_AD7P_72
set_property -quiet -dict {PACKAGE_PIN A26 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports fpga_syncin_n[1] ] ; ## IO_L23N_T3U_N9_72
set_property -quiet -dict {PACKAGE_PIN B27 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports fpga_syncin_p[1] ] ; ## IO_L23P_T3U_N8_72
set_property -quiet -dict {PACKAGE_PIN F25 IOSTANDARD LVDS } [get_ports fpga_syncout_n[0] ] ; ## IO_L14N_T2L_N3_GC_72
set_property -quiet -dict {PACKAGE_PIN F26 IOSTANDARD LVDS } [get_ports fpga_syncout_p[0] ] ; ## IO_L14P_T2L_N2_GC_72
set_property -quiet -dict {PACKAGE_PIN D22 IOSTANDARD LVDS } [get_ports fpga_syncout_n[1] ] ; ## IO_L15N_T2L_N5_AD11N_72
set_property -quiet -dict {PACKAGE_PIN E22 IOSTANDARD LVDS } [get_ports fpga_syncout_p[1] ] ; ## IO_L15P_T2L_N4_AD11P_72
set_property -dict {PACKAGE_PIN J26 IOSTANDARD LVCMOS18 } [get_ports gpio[0] ] ; ## IO_L6P_T0U_N10_AD6P_72
set_property -dict {PACKAGE_PIN J25 IOSTANDARD LVCMOS18 } [get_ports gpio[1] ] ; ## IO_L6N_T0U_N11_AD6N_72
set_property -dict {PACKAGE_PIN B18 IOSTANDARD LVCMOS18 } [get_ports gpio[2] ] ; ## IO_L21P_T3L_N4_AD8P_71
set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVCMOS18 } [get_ports gpio[3] ] ; ## IO_L21N_T3L_N5_AD8N_71
set_property -dict {PACKAGE_PIN A25 IOSTANDARD LVCMOS18 } [get_ports gpio[4] ] ; ## IO_L24P_T3U_N10_72
set_property -dict {PACKAGE_PIN A24 IOSTANDARD LVCMOS18 } [get_ports gpio[5] ] ; ## IO_L24N_T3U_N11_72
set_property -dict {PACKAGE_PIN C23 IOSTANDARD LVCMOS18 } [get_ports gpio[6] ] ; ## IO_L19P_T3L_N0_DBC_AD9P_72
set_property -dict {PACKAGE_PIN B22 IOSTANDARD LVCMOS18 } [get_ports gpio[7] ] ; ## IO_L19N_T3L_N1_DBC_AD9N_72
set_property -dict {PACKAGE_PIN K24 IOSTANDARD LVCMOS18 } [get_ports gpio[8] ] ; ## IO_L3P_T0L_N4_AD15P_72
set_property -dict {PACKAGE_PIN K23 IOSTANDARD LVCMOS18 } [get_ports gpio[9] ] ; ## IO_L3N_T0L_N5_AD15N_72
set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVCMOS18 } [get_ports gpio[10] ] ; ## IO_L24N_T3U_N11_71
set_property -dict {PACKAGE_PIN B25 IOSTANDARD LVCMOS18 } [get_ports hmc_gpio1 ] ; ## IO_L21N_T3L_N5_AD8N_72
set_property -dict {PACKAGE_PIN J27 IOSTANDARD LVCMOS18 } [get_ports hmc_sync ] ; ## IO_L5N_T0U_N9_AD14N_72
set_property -dict {PACKAGE_PIN E27 IOSTANDARD LVCMOS18 } [get_ports irqb[0] ] ; ## IO_L18P_T2U_N10_AD2P_72
set_property -dict {PACKAGE_PIN D27 IOSTANDARD LVCMOS18 } [get_ports irqb[1] ] ; ## IO_L18N_T2U_N11_AD2N_72
set_property -dict {PACKAGE_PIN K27 IOSTANDARD LVCMOS18 } [get_ports rstb ] ; ## IO_L5P_T0U_N8_AD14P_72
set_property -dict {PACKAGE_PIN B23 IOSTANDARD LVCMOS18 } [get_ports rxen[0] ] ; ## IO_L22P_T3U_N6_DBC_AD0P_72
set_property -dict {PACKAGE_PIN A23 IOSTANDARD LVCMOS18 } [get_ports rxen[1] ] ; ## IO_L22N_T3U_N7_DBC_AD0N_72
set_property -dict {PACKAGE_PIN H27 IOSTANDARD LVCMOS18 } [get_ports spi0_csb ] ; ## IO_L9P_T1L_N4_AD12P_72
set_property -dict {PACKAGE_PIN G27 IOSTANDARD LVCMOS18 } [get_ports spi0_miso ] ; ## IO_L9N_T1L_N5_AD12N_72
set_property -dict {PACKAGE_PIN C25 IOSTANDARD LVCMOS18 } [get_ports spi0_mosi ] ; ## IO_L20P_T3L_N2_AD1P_72
set_property -dict {PACKAGE_PIN C24 IOSTANDARD LVCMOS18 } [get_ports spi0_sclk ] ; ## IO_L20N_T3L_N3_AD1N_72
set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVCMOS18 } [get_ports spi1_csb ] ; ## IO_L8P_T1L_N2_AD5P_72
set_property -dict {PACKAGE_PIN B26 IOSTANDARD LVCMOS18 } [get_ports spi1_sclk ] ; ## IO_L21P_T3L_N4_AD8P_72
set_property -dict {PACKAGE_PIN H22 IOSTANDARD LVCMOS18 } [get_ports spi1_sdio ] ; ## IO_L8N_T1L_N3_AD5N_72
set_property -dict {PACKAGE_PIN F23 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports sysref2_n ] ; ## IO_L11N_T1U_N9_GC_72
set_property -dict {PACKAGE_PIN F24 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports sysref2_p ] ; ## IO_L11P_T1U_N8_GC_72
set_property -dict {PACKAGE_PIN E26 IOSTANDARD LVCMOS18 } [get_ports txen[0] ] ; ## IO_L17P_T2U_N8_AD10P_72
set_property -dict {PACKAGE_PIN D26 IOSTANDARD LVCMOS18 } [get_ports txen[1] ] ; ## IO_L17N_T2U_N9_AD10N_72

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source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl
# get_env_param retrieves parameter value from the environment if exists,
# other case use the default value
#
# Use over-writable parameters from the environment.
#
# e.g.
# make JESD_MODE=64B66B RX_RATE=24.75 TX_RATE=12.375 RX_JESD_L=4 TX_JESD_L=4
# make JESD_MODE=64B66B RX_RATE=16.22016 TX_RATE=16.22016 RX_JESD_M=8 RX_JESD_L=2 TX_JESD_M=16 TX_JESD_L=4
# make JESD_MODE=64B66B RX_RATE=16.50 TX_RATE=16.50 RX_JESD_M=4 RX_JESD_L=4 RX_JESD_S=1 RX_JESD_NP=16 TX_JESD_M=4 TX_JESD_L=4 TX_JESD_S=1 TX_JESD_NP=16
# make JESD_MODE=64B66B RX_RATE=24.75 TX_RATE=24.75 RX_JESD_M=4 RX_JESD_L=4 RX_JESD_S=2 RX_JESD_NP=12 TX_JESD_M=4 TX_JESD_L=4 TX_JESD_S=2 TX_JESD_NP=12
# make JESD_MODE=64B66B RX_RATE=16.50 TX_RATE=16.50 RX_JESD_M=4 RX_JESD_L=4 RX_JESD_S=2 RX_JESD_NP=12 TX_JESD_M=4 TX_JESD_L=4 TX_JESD_S=2 TX_JESD_NP=12
# make JESD_MODE=8B10B RX_JESD_L=4 RX_JESD_M=8 TX_JESD_L=4 TX_JESD_M=8
#
# Parameter description:
# JESD_MODE : Used link layer encoder mode
# 64B66B - 64b66b link layer defined in JESD 204C
# 8B10B - 8b10b link layer defined in JESD 204B
#
# RX_RATE : Lane rate of the Rx link ( MxFE to FPGA )
# TX_RATE : Lane rate of the Tx link ( FPGA to MxFE )
# [RX/TX]_JESD_M : Number of converters per link
# [RX/TX]_JESD_L : Number of lanes per link
# [RX/TX]_JESD_NP : Number of bits per sample
# [RX/TX]_NUM_LINKS : Number of links
#
adi_project ad9081_fmca_ebz_vcu128 0 [list \
JESD_MODE [get_env_param JESD_MODE 8B10B ] \
RX_LANE_RATE [get_env_param RX_RATE 10 ] \
TX_LANE_RATE [get_env_param TX_RATE 10 ] \
RX_JESD_M [get_env_param RX_JESD_M 8 ] \
RX_JESD_L [get_env_param RX_JESD_L 4 ] \
RX_JESD_S [get_env_param RX_JESD_S 1 ] \
RX_JESD_NP [get_env_param RX_JESD_NP 16 ] \
RX_NUM_LINKS [get_env_param RX_NUM_LINKS 1 ] \
TX_JESD_M [get_env_param TX_JESD_M 8 ] \
TX_JESD_L [get_env_param TX_JESD_L 4 ] \
TX_JESD_S [get_env_param TX_JESD_S 1 ] \
TX_JESD_NP [get_env_param TX_JESD_NP 16 ] \
TX_NUM_LINKS [get_env_param TX_NUM_LINKS 1 ] \
RX_KS_PER_CHANNEL [get_env_param RX_KS_PER_CHANNEL 64 ] \
TX_KS_PER_CHANNEL [get_env_param TX_KS_PER_CHANNEL 64 ] \
]
adi_project_files ad9081_fmca_ebz_vcu128 [list \
"system_top.v" \
"system_constr.xdc"\
"timing_constr.xdc"\
"../../../library/common/ad_3w_spi.v"\
"$ad_hdl_dir/library/common/ad_iobuf.v" \
"$ad_hdl_dir/projects/common/vcu128/vcu128_system_constr.xdc" ]
# Avoid critical warning in OOC mode from the clock definitions
# since at that stage the submodules are not stiched together yet
if {$ADI_USE_OOC_SYNTHESIS == 1} {
set_property used_in_synthesis false [get_files timing_constr.xdc]
}
adi_project_run ad9081_fmca_ebz_vcu128

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// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top #(
parameter TX_JESD_L = 8,
parameter TX_NUM_LINKS = 1,
parameter RX_JESD_L = 8,
parameter RX_NUM_LINKS = 1
) (
input sys_rst,
input sys_clk_p,
input sys_clk_n,
input uart_sin,
output uart_sout,
output ddr4_act_n,
output [16:0] ddr4_addr,
output [ 1:0] ddr4_ba,
output [ 0:0] ddr4_bg,
output ddr4_ck_p,
output ddr4_ck_n,
output [ 0:0] ddr4_cke,
output [ 1:0] ddr4_cs_n,
inout [ 8:0] ddr4_dm_n,
inout [71:0] ddr4_dq,
inout [ 8:0] ddr4_dqs_p,
inout [ 8:0] ddr4_dqs_n,
output [ 0:0] ddr4_odt,
output ddr4_reset_n,
output mdio_mdc,
inout mdio_mdio,
input phy_clk_p,
input phy_clk_n,
input phy_rx_p,
input phy_rx_n,
output phy_tx_p,
output phy_tx_n,
input phy_dummy_port_in,
inout [7:0] gpio_bd,
inout iic_scl,
inout iic_sda,
input vadj_1v8_pgood,
// FMC HPC IOs
input [1:0] agc0,
input [1:0] agc1,
input [1:0] agc2,
input [1:0] agc3,
input clkin8_n,
input clkin8_p,
input clkin6_n,
input clkin6_p,
input fpga_refclk_in_n,
input fpga_refclk_in_p,
input [RX_JESD_L*RX_NUM_LINKS-1:0] rx_data_n,
input [RX_JESD_L*RX_NUM_LINKS-1:0] rx_data_p,
output [TX_JESD_L*TX_NUM_LINKS-1:0] tx_data_n,
output [TX_JESD_L*TX_NUM_LINKS-1:0] tx_data_p,
input [TX_NUM_LINKS-1:0] fpga_syncin_n,
input [TX_NUM_LINKS-1:0] fpga_syncin_p,
output [RX_NUM_LINKS-1:0] fpga_syncout_n,
output [RX_NUM_LINKS-1:0] fpga_syncout_p,
inout [10:0] gpio,
inout hmc_gpio1,
output hmc_sync,
input [1:0] irqb,
output rstb,
output [1:0] rxen,
output spi0_csb,
input spi0_miso,
output spi0_mosi,
output spi0_sclk,
output spi1_csb,
output spi1_sclk,
inout spi1_sdio,
input sysref2_n,
input sysref2_p,
output [1:0] txen
);
// internal signals
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire [ 7:0] spi_csn;
wire spi_mosi;
wire spi_miso;
wire spi1_miso;
wire ref_clk;
wire sysref;
wire [TX_NUM_LINKS-1:0] tx_syncin;
wire [RX_NUM_LINKS-1:0] rx_syncout;
wire [7:0] tx_data_p_loc;
wire [7:0] tx_data_n_loc;
wire clkin6;
wire clkin8;
wire tx_device_clk;
wire rx_device_clk;
// instantiations
IBUFDS_GTE4 i_ibufds_ref_clk (
.CEB (1'd0),
.I (fpga_refclk_in_p),
.IB (fpga_refclk_in_n),
.O (ref_clk),
.ODIV2 ());
IBUFDS i_ibufds_sysref (
.I (sysref2_p),
.IB (sysref2_n),
.O (sysref));
IBUFDS i_ibufds_device_clk (
.I (clkin6_p),
.IB (clkin6_n),
.O (clkin6));
IBUFDS_GTE4 i_ibufds_rx_device_clk (
.I (clkin8_p),
.IB (clkin8_n),
.CEB(1'b0),
.ODIV2 (clkin8));
genvar i;
generate
for(i=0;i<TX_NUM_LINKS;i=i+1) begin : g_tx_buffers
IBUFDS i_ibufds_syncin (
.I (fpga_syncin_p[i]),
.IB (fpga_syncin_n[i]),
.O (tx_syncin[i]));
end
for(i=0;i<RX_NUM_LINKS;i=i+1) begin : g_rx_buffers
OBUFDS i_obufds_syncout (
.I (rx_syncout[i]),
.O (fpga_syncout_p[i]),
.OB (fpga_syncout_n[i]));
end
endgenerate
BUFG i_tx_device_clk (
.I (clkin6),
.O (tx_device_clk)
);
BUFG_GT i_rx_device_clk (
.I (clkin8),
.O (rx_device_clk)
);
// spi
assign spi0_csb = spi_csn[0];
assign spi0_mosi = spi_mosi;
assign spi0_sclk = spi_clk;
assign spi1_csb = spi_csn[1];
assign spi1_sclk = spi_clk;
assign spi_miso = ~spi_csn[0] ? spi0_miso :
~spi_csn[1] ? spi1_miso : 1'b0;
ad_3w_spi #(.NUM_OF_SLAVES(1)) i_spi (
.spi_csn (spi_csn[1]),
.spi_clk (spi_clk),
.spi_mosi (spi_mosi),
.spi_miso (spi1_miso),
.spi_sdio (spi1_sdio),
.spi_dir ());
// gpios
ad_iobuf #(.DATA_WIDTH(12)) i_iobuf (
.dio_t (gpio_t[43:32]),
.dio_i (gpio_o[43:32]),
.dio_o (gpio_i[43:32]),
.dio_p ({hmc_gpio1, // 43
gpio[10:0]})); // 42-32
assign gpio_i[44] = agc0[0];
assign gpio_i[45] = agc0[1];
assign gpio_i[46] = agc1[0];
assign gpio_i[47] = agc1[1];
assign gpio_i[48] = agc2[0];
assign gpio_i[49] = agc2[1];
assign gpio_i[50] = agc3[0];
assign gpio_i[51] = agc3[1];
assign gpio_i[52] = irqb[0];
assign gpio_i[53] = irqb[1];
assign hmc_sync = gpio_o[54];
assign rstb = gpio_o[55];
assign rxen[0] = gpio_o[56];
assign rxen[1] = gpio_o[57];
assign txen[0] = gpio_o[58];
assign txen[1] = gpio_o[59];
assign dac_fifo_bypass = gpio_o[60];
ad_iobuf #(.DATA_WIDTH(8)) i_iobuf_bd (
.dio_t (gpio_t[7:0]),
.dio_i (gpio_o[7:0]),
.dio_o (gpio_i[7:0]),
.dio_p (gpio_bd));
assign gpio_i[63:54] = gpio_o[63:54];
assign gpio_i[31:8] = gpio_o[31:8];
system_wrapper i_system_wrapper (
.sys_rst (sys_rst),
.sys_clk_clk_n (sys_clk_n),
.sys_clk_clk_p (sys_clk_p),
.ddr4_act_n (ddr4_act_n),
.ddr4_adr (ddr4_addr),
.ddr4_ba (ddr4_ba),
.ddr4_bg (ddr4_bg),
.ddr4_ck_c (ddr4_ck_n),
.ddr4_ck_t (ddr4_ck_p),
.ddr4_cke (ddr4_cke),
.ddr4_cs_n (ddr4_cs_n),
.ddr4_dm_n (ddr4_dm_n),
.ddr4_dq (ddr4_dq),
.ddr4_dqs_c (ddr4_dqs_n),
.ddr4_dqs_t (ddr4_dqs_p),
.ddr4_odt (ddr4_odt),
.ddr4_reset_n (ddr4_reset_n),
.phy_sd (1'b1),
.phy_dummy_port_in (phy_dummy_port_in),
.sgmii_rxn (phy_rx_n),
.sgmii_rxp (phy_rx_p),
.sgmii_txn (phy_tx_n),
.sgmii_txp (phy_tx_p),
.mdio_mdc (mdio_mdc),
.mdio_mdio_io (mdio_mdio),
.sgmii_phyclk_clk_n (phy_clk_n),
.sgmii_phyclk_clk_p (phy_clk_p),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.uart_sin (uart_sin),
.uart_sout (uart_sout),
.spi_clk_i (spi_clk),
.spi_clk_o (spi_clk),
.spi_csn_i (spi_csn),
.spi_csn_o (spi_csn),
.spi_sdi_i (spi_miso),
.spi_sdo_i (spi_mosi),
.spi_sdo_o (spi_mosi),
.gpio0_i (gpio_i[31:0]),
.gpio0_o (gpio_o[31:0]),
.gpio0_t (gpio_t[31:0]),
.gpio1_i (gpio_i[63:32]),
.gpio1_o (gpio_o[63:32]),
.gpio1_t (gpio_t[63:32]),
// FMC HPC
.rx_data_0_n (rx_data_n[0]),
.rx_data_0_p (rx_data_p[0]),
.rx_data_1_n (rx_data_n[1]),
.rx_data_1_p (rx_data_p[1]),
.rx_data_2_n (rx_data_n[2]),
.rx_data_2_p (rx_data_p[2]),
.rx_data_3_n (rx_data_n[3]),
.rx_data_3_p (rx_data_p[3]),
.rx_data_4_n (rx_data_n[4]),
.rx_data_4_p (rx_data_p[4]),
.rx_data_5_n (rx_data_n[5]),
.rx_data_5_p (rx_data_p[5]),
.rx_data_6_n (rx_data_n[6]),
.rx_data_6_p (rx_data_p[6]),
.rx_data_7_n (rx_data_n[7]),
.rx_data_7_p (rx_data_p[7]),
.tx_data_0_n (tx_data_n_loc[0]),
.tx_data_0_p (tx_data_p_loc[0]),
.tx_data_1_n (tx_data_n_loc[1]),
.tx_data_1_p (tx_data_p_loc[1]),
.tx_data_2_n (tx_data_n_loc[2]),
.tx_data_2_p (tx_data_p_loc[2]),
.tx_data_3_n (tx_data_n_loc[3]),
.tx_data_3_p (tx_data_p_loc[3]),
.tx_data_4_n (tx_data_n_loc[4]),
.tx_data_4_p (tx_data_p_loc[4]),
.tx_data_5_n (tx_data_n_loc[5]),
.tx_data_5_p (tx_data_p_loc[5]),
.tx_data_6_n (tx_data_n_loc[6]),
.tx_data_6_p (tx_data_p_loc[6]),
.tx_data_7_n (tx_data_n_loc[7]),
.tx_data_7_p (tx_data_p_loc[7]),
.ref_clk_q0 (ref_clk),
.ref_clk_q1 (ref_clk),
.rx_device_clk (rx_device_clk),
.tx_device_clk (tx_device_clk),
.rx_sync_0 (rx_syncout),
.tx_sync_0 (tx_syncin),
.rx_sysref_0 (sysref),
.tx_sysref_0 (sysref)
);
assign tx_data_p[TX_JESD_L*TX_NUM_LINKS-1:0] = tx_data_p_loc[TX_JESD_L*TX_NUM_LINKS-1:0];
assign tx_data_n[TX_JESD_L*TX_NUM_LINKS-1:0] = tx_data_n_loc[TX_JESD_L*TX_NUM_LINKS-1:0];
endmodule
// ***************************************************************************
// ***************************************************************************

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# Primary clock definitions
# Set clocks depending on the requested LANE_RATE paramter from the util_adxcvr block
# Maximum values for Link clock:
# 204B - 15.5 Gbps /40 = 387.5MHz
# 204C - 24.75 Gbps /66 = 375MHz
set link_mode [get_property LINK_MODE [get_cells i_system_wrapper/system_i/util_mxfe_xcvr/inst]]
set rx_lane_rate [get_property RX_LANE_RATE [get_cells i_system_wrapper/system_i/util_mxfe_xcvr/inst]]
set tx_lane_rate [get_property TX_LANE_RATE [get_cells i_system_wrapper/system_i/util_mxfe_xcvr/inst]]
set rx_link_clk [expr $rx_lane_rate*1000/[expr {$link_mode==2?66:40}]]
set tx_link_clk [expr $tx_lane_rate*1000/[expr {$link_mode==2?66:40}]]
set rx_link_clk_period [expr 1000/$rx_link_clk]
set tx_link_clk_period [expr 1000/$tx_link_clk]
set rx_ll_width [get_property DATA_PATH_WIDTH [get_cells i_system_wrapper/system_i/axi_mxfe_rx_jesd/rx/inst]]
set tx_ll_width [get_property DATA_PATH_WIDTH [get_cells i_system_wrapper/system_i/axi_mxfe_tx_jesd/tx/inst]]
set rx_tpl_width [get_property TPL_DATA_PATH_WIDTH [get_cells i_system_wrapper/system_i/axi_mxfe_rx_jesd/rx/inst]]
set tx_tpl_width [get_property TPL_DATA_PATH_WIDTH [get_cells i_system_wrapper/system_i/axi_mxfe_tx_jesd/tx/inst]]
set rx_device_clk [expr $rx_link_clk*$rx_ll_width/$rx_tpl_width]
set tx_device_clk [expr $tx_link_clk*$tx_ll_width/$tx_tpl_width]
set rx_device_clk_period [expr 1000/$rx_device_clk]
set tx_device_clk_period [expr 1000/$tx_device_clk]
# refclk and refclk_replica are connect to the same source on the PCB
# Set reference clock to same frequency as the link clock,
# this will ease the XCVR out clocks propagation calculation.
# TODO: this restricts RX_LANE_RATE=TX_LANE_RATE
create_clock -name refclk -period $rx_link_clk_period [get_ports fpga_refclk_in_p]
create_clock -name refclk_replica -period $rx_link_clk_period [get_ports fpga_refclk_in_replica_p]
# device clock
create_clock -name rx_device_clk -period $rx_device_clk_period [get_ports clkin8_p]
create_clock -name tx_device_clk -period $tx_device_clk_period [get_ports clkin6_p]
# Constraint SYSREFs
# Assumption is that REFCLK and SYSREF have similar propagation delay,
# and the SYSREF is a source synchronous Edge-Aligned signal to REFCLK
set_input_delay -clock [get_clocks rx_device_clk] \
[get_property PERIOD [get_clocks rx_device_clk]] \
[get_ports {sysref2_*}]
set_input_delay -clock [get_clocks tx_device_clk] -add_delay\
[get_property PERIOD [get_clocks tx_device_clk]] \
[get_ports {sysref2_*}]
set_clock_groups -group rx_device_clk -group tx_device_clk -asynchronous
# For transceiver output clocks use reference clock divided by one
# This will help autoderive the clocks correcly
set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXSYSCLKSEL[0]]
set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXSYSCLKSEL[1]]
set_case_analysis -quiet 1 [get_pins -quiet -hier *_channel/TXOUTCLKSEL[0]]
set_case_analysis -quiet 1 [get_pins -quiet -hier *_channel/TXOUTCLKSEL[1]]
set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXOUTCLKSEL[2]]
set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXSYSCLKSEL[0]]
set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXSYSCLKSEL[1]]
set_case_analysis -quiet 1 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[0]]
set_case_analysis -quiet 1 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[1]]
set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[2]]