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jesd204: Clean-up combinatorial logic 

To correctly model combinatorial logic in always blocks
blocking assignments must be used.
main
Laszlo Nagy 2020-09-25 09:38:45 +01:00 committed by Laszlo Nagy
parent 7c523fbf02
commit e759c1855b
17 changed files with 371 additions and 371 deletions
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50
library/jesd204/axi_jesd204_common/jesd204_up_common.v
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@ -257,66 +257,66 @@ wire [20:0] clk_mon_count;
always @(*) begin
case (up_raddr)
/* Standard registers */
12'h000: up_rdata <= PCORE_VERSION;
12'h001: up_rdata <= ID;
12'h002: up_rdata <= up_scratch;
12'h003: up_rdata <= PCORE_MAGIC;
12'h000: up_rdata = PCORE_VERSION;
12'h001: up_rdata = ID;
12'h002: up_rdata = up_scratch;
12'h003: up_rdata = PCORE_MAGIC;
/* Core configuration */
12'h004: up_rdata <= NUM_LANES;
12'h005: up_rdata <= DATA_PATH_WIDTH;
12'h006: up_rdata <= {22'b0,LINK_MODE[1:0], NUM_LINKS[7:0]};
12'h004: up_rdata = NUM_LANES;
12'h005: up_rdata = DATA_PATH_WIDTH;
12'h006: up_rdata = {22'b0,LINK_MODE[1:0], NUM_LINKS[7:0]};
/* 0x07-0x0f reserved for future use */
/* 0x10-0x1f reserved for core specific HDL configuration information */
/* IRQ block */
12'h020: up_rdata <= up_irq_enable;
12'h021: up_rdata <= up_irq_pending;
12'h022: up_rdata <= up_irq_source;
12'h020: up_rdata = up_irq_enable;
12'h021: up_rdata = up_irq_pending;
12'h022: up_rdata = up_irq_source;
/* 0x23-0x30 reserved for future use */
/* JESD common control */
12'h030: up_rdata <= up_reset_core;
12'h031: up_rdata <= {up_core_reset_ext, up_reset_synchronizer}; /* core ready */
12'h032: up_rdata <= {11'h00, clk_mon_count}; /* Make it 16.16 */
12'h030: up_rdata = up_reset_core;
12'h031: up_rdata = {up_core_reset_ext, up_reset_synchronizer}; /* core ready */
12'h032: up_rdata = {11'h00, clk_mon_count}; /* Make it 16.16 */
/* 0x32-0x34 reserver for future use */
12'h080: up_rdata <= up_cfg_lanes_disable;
12'h080: up_rdata = up_cfg_lanes_disable;
/* 0x82-0x83 reserved for future lane disable bits (max 128 lanes) */
12'h084: up_rdata <= {
12'h084: up_rdata = {
/* 24-31 */ 8'h00, /* Reserved for future extensions of octets_per_frame */
/* 16-23 */ up_cfg_octets_per_frame,
/* 10-15 */ 6'b000000, /* Reserved for future extensions of beats_per_multiframe */
/* 00-09 */ up_cfg_beats_per_multiframe,{DATA_PATH_WIDTH{1'b1}}
};
12'h85: up_rdata <= {
12'h85: up_rdata = {
/* 02-31 */ 30'h00, /* Reserved for future additions */
/* 01 */ up_cfg_disable_char_replacement, /* Disable character replacement */
/* 00 */ up_cfg_disable_scrambler /* Disable scrambler */
};
12'h086: up_rdata <= up_cfg_links_disable;
12'h086: up_rdata = up_cfg_links_disable;
/* 0x87-0x8f reserved for future use */
/* 0x90-0x9f reserved for core specific configuration options */
/* 0xb0 Stat control */
12'h0b1: up_rdata <= up_link_enable_cnt_s;
12'h0b1: up_rdata = up_link_enable_cnt_s;
/* 0xb4-0xb7 IRQ Stat, max 8 interrupt sources */
12'h0b4: up_rdata <= up_irq_event_cnt_bus[0*32 +: 32];
12'h0b5: up_rdata <= up_irq_event_cnt_bus[1*32 +: 32];
12'h0b6: up_rdata <= up_irq_event_cnt_bus[2*32 +: 32];
12'h0b7: up_rdata <= up_irq_event_cnt_bus[3*32 +: 32];
12'h0b4: up_rdata = up_irq_event_cnt_bus[0*32 +: 32];
12'h0b5: up_rdata = up_irq_event_cnt_bus[1*32 +: 32];
12'h0b6: up_rdata = up_irq_event_cnt_bus[2*32 +: 32];
12'h0b7: up_rdata = up_irq_event_cnt_bus[3*32 +: 32];
default: up_rdata <= 'h00;
default: up_rdata = 'h00;
endcase
end
/* IRQ pending register is write-1-to-clear */
always @(*) begin
if (up_wreq == 1'b1 && up_waddr == 12'h21) begin
up_irq_clear <= up_wdata[NUM_IRQS-1:0];
up_irq_clear = up_wdata[NUM_IRQS-1:0];
end else begin
up_irq_clear <= {NUM_IRQS{1'b0}};
up_irq_clear = {NUM_IRQS{1'b0}};
end
end

12
library/jesd204/axi_jesd204_common/jesd204_up_sysref.v
View File

@ -96,21 +96,21 @@ end
always @(*) begin
case (up_raddr)
/* JESD SYSREF configuraton */
12'h040: up_rdata <= {
12'h040: up_rdata = {
/* 02-31 */ 30'h00, /* Reserved for future use */
/* 01 */ up_cfg_sysref_oneshot,
/* 00 */ up_cfg_sysref_disable
};
12'h041: up_rdata <= {
12'h041: up_rdata = {
/* 10-31 */ 22'h00, /* Reserved for future use */
/* 02-09 */ up_cfg_lmfc_offset,
/* 00-01 */ 2'b00 /* data path alignment for cfg_lmfc_offset */
};
12'h042: up_rdata <= {
12'h042: up_rdata = {
/* 02-31 */ 30'h00,
/* 00-01 */ up_sysref_status
};
default: up_rdata <= 32'h00000000;
default: up_rdata = 32'h00000000;
endcase
end
@ -136,9 +136,9 @@ end
always @(*) begin
if (up_wreq == 1'b1 && up_waddr == 12'h042) begin
up_sysref_status_clear <= up_wdata[1:0];
up_sysref_status_clear = up_wdata[1:0];
end else begin
up_sysref_status_clear <= 2'b00;
up_sysref_status_clear = 2'b00;
end
end

14
library/jesd204/axi_jesd204_rx/jesd204_up_rx.v
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@ -137,23 +137,23 @@ localparam LANE_BASE_ADDR = 'h300 / 32;
always @(*) begin
case (up_raddr)
/* Core configuration */
12'h010: up_rdata <= ELASTIC_BUFFER_SIZE; /* Elastic buffer size in octets */
12'h010: up_rdata = ELASTIC_BUFFER_SIZE; /* Elastic buffer size in octets */
/* JESD RX configuraton */
12'h090: up_rdata <= {
12'h090: up_rdata = {
/* 17-31 */ 15'h00, /* Reserved for future additions */
/* 16 */ up_cfg_buffer_early_release, /* Release buffer as soon as all lanes are ready. */
/* 10-15 */ 6'b0000, /* Reserved for future extensions of buffer_delay */
/* 02-09 */ up_cfg_buffer_delay, /* Buffer release delay */
/* 00-01 */ 2'b00 /* Data path width alignment */
};
12'h91: up_rdata <= {
12'h91: up_rdata = {
/* 15-31 */ 17'h00, /* Reserved for future additions */
/* 08-14 */ up_ctrl_err_statistics_mask,
/* 01-07 */ 7'h0,
/* 00 */ up_ctrl_err_statistics_reset
};
12'h92: up_rdata <= {
12'h92: up_rdata = {
/* 08-31 */ 24'h0,
/* 00-07 */ up_cfg_frame_align_err_threshold
};
@ -161,7 +161,7 @@ always @(*) begin
/* 0x93-0x9f reserved for future use */
/* JESD RX status */
12'ha0: up_rdata <= {
12'ha0: up_rdata = {
/* 04-31 */ 28'h00, /* Reserved for future additions */
/* 02-03 */ 2'b00, /* Reserved for future extensions of ctrl_state */
/* 00-01 */ up_status_ctrl_state /* State of the internal state machine */
@ -169,9 +169,9 @@ always @(*) begin
default: begin
if (up_raddr[11:3] >= LANE_BASE_ADDR &&
up_raddr[11:3] < LANE_BASE_ADDR + NUM_LANES) begin
up_rdata <= up_lane_rdata[up_raddr[11:3] - LANE_BASE_ADDR];
up_rdata = up_lane_rdata[up_raddr[11:3] - LANE_BASE_ADDR];
end else begin
up_rdata <= 'h00;
up_rdata = 'h00;
end
end
endcase

14
library/jesd204/axi_jesd204_rx/jesd204_up_rx_lane.v
View File

@ -102,13 +102,13 @@ end
always @(*) begin
if (up_raddr[2] == 1'b1) begin
if (up_ilas_ready == 1'b1) begin
up_rdata <= up_ilas_rdata;
up_rdata = up_ilas_rdata;
end else begin
up_rdata <= 'h00;
up_rdata = 'h00;
end
end else begin
case (up_raddr[1:0])
2'b00: up_rdata <= {
2'b00: up_rdata = {
/* 11-31 */ 21'h0, /* Reserved for future use */
/* 08-10 */ up_status_emb_state,
/* 06-07 */ 2'h00,
@ -117,18 +117,18 @@ always @(*) begin
/* 02-03 */ 2'b00, /* Reserved for future extensions of cgs_state */
/* 00-01 */ up_status_cgs_state
};
2'b01: up_rdata <= {
2'b01: up_rdata = {
/* 14-31 */ 18'h00, /* Reserved for future use */
/* 00-13 */ up_status_latency
};
2'b10: up_rdata <= {
2'b10: up_rdata = {
/* 00-31 */ up_status_err_statistics_cnt
};
2'b11: up_rdata <= {
2'b11: up_rdata = {
/* 08-31 */ 24'h0, /* Reserved for future use */
/* 00-07 */ up_status_lane_frame_align_err_cnt
};
default: up_rdata <= 'h00;
default: up_rdata = 'h00;
endcase
end
end

18
library/jesd204/axi_jesd204_tx/jesd204_up_tx.v
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@ -114,19 +114,19 @@ integer i;
always @(*) begin
case (up_raddr)
/* JESD TX configuration */
12'h090: up_rdata <= {
12'h090: up_rdata = {
/* 03-31 */ 29'h00, /* Reserved for future additions */
/* 02 */ up_cfg_skip_ilas, /* Don't send ILAS, go directly from CGS to DATA */
/* 01 */ up_cfg_continuous_ilas, /* Continuously send ILAS sequence */
/* 00 */ up_cfg_continuous_cgs /* Continuously send CGS characters */
};
12'h091: up_rdata <= {
12'h091: up_rdata = {
/* 08-31 */ 24'h00, /* Reserved for future additions */
/* 00-07 */ up_cfg_mframes_per_ilas /* Number of multiframes send during the ILAS */
};
/* JESD TX status */
12'ha0: up_rdata <= {
12'ha0: up_rdata = {
/* 12-31 */ 20'h00, /* Reserved for future additions */
/* 04-11 */ up_status_sync, /* Raw value of the SYNC pin */
/* 02-03 */ 2'b0, /* Reserved fo future extension of the status_state field */
@ -136,9 +136,9 @@ always @(*) begin
if (up_raddr[10:3] >= ('h300/32) &&
up_raddr[10:3] < (('h300/32) + NUM_LANES) &&
up_raddr[2] == 1'b1) begin
up_rdata <= up_cfg_ilas_data[up_raddr[5:3]][up_raddr[1:0]];
up_rdata = up_cfg_ilas_data[up_raddr[5:3]][up_raddr[1:0]];
end else begin
up_rdata <= 32'h00000000;
up_rdata = 32'h00000000;
end
end
endcase
@ -202,13 +202,13 @@ reg [7:0] up_cfg_ilas_data_fchk[0:NUM_LANES-1];
always @(*) begin
for (i = 0; i < NUM_LANES; i = i + 1) begin
up_cfg_ilas_data[i][0] <= {
up_cfg_ilas_data[i][0] = {
4'b0000,
up_cfg_ilas_data_bid,
up_cfg_ilas_data_did,
16'h00
};
up_cfg_ilas_data[i][1] <= {
up_cfg_ilas_data[i][1] = {
3'b000,
up_cfg_ilas_data_k,
up_cfg_ilas_data_f,
@ -218,7 +218,7 @@ always @(*) begin
3'b000,
up_cfg_ilas_data_lid[i]
};
up_cfg_ilas_data[i][2] <= {
up_cfg_ilas_data[i][2] = {
up_cfg_ilas_data_jesdv,
up_cfg_ilas_data_s,
up_cfg_ilas_data_subclassv,
@ -228,7 +228,7 @@ always @(*) begin
up_cfg_ilas_data_n,
up_cfg_ilas_data_m
};
up_cfg_ilas_data[i][3] <= {
up_cfg_ilas_data[i][3] = {
up_cfg_ilas_data_fchk[i],
16'h0000,
up_cfg_ilas_data_hd,

4
library/jesd204/jesd204_common/jesd204_lmfc.v
View File

@ -126,9 +126,9 @@ end
always @(*) begin
if (lmfc_counter == cfg_beats_per_multiframe) begin
lmfc_counter_next <= 'h00;
lmfc_counter_next = 'h00;
end else begin
lmfc_counter_next <= lmfc_counter + 1'b1;
lmfc_counter_next = lmfc_counter + 1'b1;
end
end

4
library/jesd204/jesd204_common/jesd204_scrambler.v
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@ -76,9 +76,9 @@ assign feedback = full_state[WIDTH-1+15:15] ^ full_state[WIDTH-1+14:14] ^ swizzl
always @(*) begin
if (enable == 1'b0) begin
swizzle_out <= swizzle_in;
swizzle_out = swizzle_in;
end else begin
swizzle_out <= feedback;
swizzle_out = feedback;
end
end

16
library/jesd204/jesd204_rx/align_mux.v
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@ -65,17 +65,17 @@ end
always @(*) begin
case (align)
'h0: out_data <= in_data_d1;
'h1: out_data <= {in_data[7:0],in_data_d1[31:8]};
'h2: out_data <= {in_data[15:0],in_data_d1[31:16]};
'h3: out_data <= {in_data[23:0],in_data_d1[31:24]};
'h0: out_data = in_data_d1;
'h1: out_data = {in_data[7:0],in_data_d1[31:8]};
'h2: out_data = {in_data[15:0],in_data_d1[31:16]};
'h3: out_data = {in_data[23:0],in_data_d1[31:24]};
endcase
case (align)
'h0: out_charisk <= in_charisk_d1;
'h1: out_charisk <= {in_charisk[0:0],in_charisk_d1[3:1]};
'h2: out_charisk <= {in_charisk[1:0],in_charisk_d1[3:2]};
'h3: out_charisk <= {in_charisk[2:0],in_charisk_d1[3:3]};
'h0: out_charisk = in_charisk_d1;
'h1: out_charisk = {in_charisk[0:0],in_charisk_d1[3:1]};
'h2: out_charisk = {in_charisk[1:0],in_charisk_d1[3:2]};
'h3: out_charisk = {in_charisk[2:0],in_charisk_d1[3:3]};
endcase
end

4
library/jesd204/jesd204_rx/jesd204_ilas_monitor.v
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@ -75,10 +75,10 @@ reg frame_length_error = 1'b0;
assign data_ready_n = next_state;
always @(*) begin
next_state <= state;
next_state = state;
if (reset == 1'b0 && prev_was_last == 1'b1) begin
if (charisk28[0] != 1'b1 || data[7:5] != 3'h0) begin
next_state <= STATE_DATA;
next_state = STATE_DATA;
end
end
end

6
library/jesd204/jesd204_rx/jesd204_rx.v
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@ -438,9 +438,9 @@ end
always @(*) begin
case (SCRAMBLER_REGISTERED + ALIGN_MUX_REGISTERED)
1: ifs_ready_mux <= ifs_ready_d1;
2: ifs_ready_mux <= ifs_ready_d2;
default: ifs_ready_mux <= ifs_ready;
1: ifs_ready_mux = ifs_ready_d1;
2: ifs_ready_mux = ifs_ready_d2;
default: ifs_ready_mux = ifs_ready;
endcase
end

18
library/jesd204/jesd204_rx/jesd204_rx_ctrl.v
View File

@ -122,11 +122,11 @@ end
always @(*) begin
case (state)
STATE_RESET: state_good <= 1'b1;
STATE_WAIT_FOR_PHY: state_good <= phy_ready;
STATE_CGS: state_good <= &(cgs_ready | cfg_lanes_disable);
STATE_SYNCHRONIZED: state_good <= 1'b1;
default: state_good <= 1'b0;
STATE_RESET: state_good = 1'b1;
STATE_WAIT_FOR_PHY: state_good = phy_ready;
STATE_CGS: state_good = &(cgs_ready | cfg_lanes_disable);
STATE_SYNCHRONIZED: state_good = 1'b1;
default: state_good = 1'b0;
endcase
end
@ -156,10 +156,10 @@ end
always @(*) begin
case (state)
STATE_RESET: next_state <= STATE_WAIT_FOR_PHY;
STATE_WAIT_FOR_PHY: next_state <= STATE_CGS;
STATE_CGS: next_state <= STATE_SYNCHRONIZED;
default: next_state <= state_good ? state : STATE_RESET;
STATE_RESET: next_state = STATE_WAIT_FOR_PHY;
STATE_WAIT_FOR_PHY: next_state = STATE_CGS;
STATE_CGS: next_state = STATE_SYNCHRONIZED;
default: next_state = state_good ? state : STATE_RESET;
endcase
end

8
library/jesd204/jesd204_rx/jesd204_rx_frame_align_monitor.v
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@ -111,15 +111,15 @@ genvar ii;
generate
for (ii = 0; ii < DATA_PATH_WIDTH; ii = ii + 1) begin: gen_k_char
always @(*) begin
char_is_a[ii] <= 1'b0;
char_is_f[ii] <= 1'b0;
char_is_a[ii] = 1'b0;
char_is_f[ii] = 1'b0;
if(charisk28[ii]) begin
if(data[ii*8+7:ii*8+5] == 3'd3) begin
char_is_a[ii] <= 1'b1;
char_is_a[ii] = 1'b1;
end
if(data[ii*8+7:ii*8+5] == 3'd7) begin
char_is_f[ii] <= 1'b1;
char_is_f[ii] = 1'b1;
end
end
end

14
library/jesd204/jesd204_rx/jesd204_rx_lane.v
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@ -129,20 +129,20 @@ for (i = 0; i < DATA_PATH_WIDTH; i = i + 1) begin: gen_char
assign char_is_valid[i] = ~(phy_notintable[i] | phy_disperr[i]);
always @(*) begin
char_is_error[i] <= ~char_is_valid[i];
char_is_error[i] = ~char_is_valid[i];
char_is_cgs[i] <= 1'b0;
charisk28[i] <= 1'b0;
unexpected_char[i] <= 1'b0;
char_is_cgs[i] = 1'b0;
charisk28[i] = 1'b0;
unexpected_char[i] = 1'b0;
if (phy_charisk[i] == 1'b1 && char_is_valid[i] == 1'b1) begin
if (char[i][4:0] == 'd28) begin
charisk28[i] <= 1'b1;
charisk28[i] = 1'b1;
if (char[i][7:5] == 'd5) begin
char_is_cgs[i] <= 1'b1;
char_is_cgs[i] = 1'b1;
end
end else begin
unexpected_char[i] <= 1'b1;
unexpected_char[i] = 1'b1;
end
end
end

272
library/jesd204/jesd204_soft_pcs_rx/jesd204_8b10b_decoder.v
View File

@ -75,312 +75,312 @@ reg notintable_disparity;
wire charisk = in_char[5:0] == 6'b000011 || in_char[5:0] == 6'b111100;
always @(*) begin
notintable5b <= 1'b0;
disparity5b <= 2'b00;
ignore5b <= 1'b0;
notintable5b = 1'b0;
disparity5b = 2'b00;
ignore5b = 1'b0;
case (in_char[5:0])
6'b000011: begin
data5b <= 5'd28;
disparity5b <= 2'b11;
data5b = 5'd28;
disparity5b = 2'b11;
end
6'b111100: begin
data5b <= 5'd28;
disparity5b <= 2'b01;
data5b = 5'd28;
disparity5b = 2'b01;
end
6'b000110: begin
data5b <= 5'd00;
disparity5b <= 2'b11;
data5b = 5'd00;
disparity5b = 2'b11;
end
6'b111001: begin
data5b <= 5'd00;
disparity5b <= 2'b01;
data5b = 5'd00;
disparity5b = 2'b01;
end
6'b010001: begin
data5b <= 5'd01;
disparity5b <= 2'b11;
data5b = 5'd01;
disparity5b = 2'b11;
end
6'b101110: begin
data5b <= 5'd01;
disparity5b <= 2'b01;
data5b = 5'd01;
disparity5b = 2'b01;
end
6'b010010: begin
data5b <= 5'd02;
disparity5b <= 2'b11;
data5b = 5'd02;
disparity5b = 2'b11;
end
6'b101101: begin
data5b <= 5'd02;
disparity5b <= 2'b01;
data5b = 5'd02;
disparity5b = 2'b01;
end
6'b100011: begin
data5b <= 5'd03;
data5b = 5'd03;
end
6'b010100: begin
data5b <= 5'd04;
disparity5b <= 2'b11;
data5b = 5'd04;
disparity5b = 2'b11;
end
6'b101011: begin
data5b <= 5'd04;
disparity5b <= 2'b01;
data5b = 5'd04;
disparity5b = 2'b01;
end
6'b100101: begin
data5b <= 5'd05;
data5b = 5'd05;
end
6'b100110: begin
data5b <= 5'd06;
data5b = 5'd06;
end
6'b000111: begin
data5b <= 5'd7;
disparity5b <= 2'b11;
ignore5b <= 1'b1;
data5b = 5'd7;
disparity5b = 2'b11;
ignore5b = 1'b1;
end
6'b111000: begin
data5b <= 5'd7;
disparity5b <= 2'b01;
ignore5b <= 1'b1;
data5b = 5'd7;
disparity5b = 2'b01;
ignore5b = 1'b1;
end
6'b011000: begin
data5b <= 5'd8;
disparity5b <= 2'b11;
data5b = 5'd8;
disparity5b = 2'b11;
end
6'b100111: begin
data5b <= 5'd8;
disparity5b <= 2'b01;
data5b = 5'd8;
disparity5b = 2'b01;
end
6'b101001: begin
data5b <= 5'd9;
data5b = 5'd9;
end
6'b101010: begin
data5b <= 5'd10;
data5b = 5'd10;
end
6'b001011: begin
data5b <= 5'd11;
data5b = 5'd11;
end
6'b101100: begin
data5b <= 5'd12;
data5b = 5'd12;
end
6'b001101: begin
data5b <= 5'd13;
data5b = 5'd13;
end
6'b001110: begin
data5b <= 5'd14;
data5b = 5'd14;
end
6'b000101: begin
data5b <= 5'd15;
disparity5b <= 2'b11;
data5b = 5'd15;
disparity5b = 2'b11;
end
6'b111010: begin
data5b <= 5'd15;
disparity5b <= 2'b01;
data5b = 5'd15;
disparity5b = 2'b01;
end
6'b001001: begin
data5b <= 5'd16;
disparity5b <= 2'b11;
data5b = 5'd16;
disparity5b = 2'b11;
end
6'b110110: begin
data5b <= 5'd16;
disparity5b <= 2'b01;
data5b = 5'd16;
disparity5b = 2'b01;
end
6'b110001: begin
data5b <= 5'd17;
data5b = 5'd17;
end
6'b110010: begin
data5b <= 5'd18;
data5b = 5'd18;
end
6'b010011: begin
data5b <= 5'd19;
data5b = 5'd19;
end
6'b110100: begin
data5b <= 5'd20;
data5b = 5'd20;
end
6'b010101: begin
data5b <= 5'd21;
data5b = 5'd21;
end
6'b010110: begin
data5b <= 5'd22;
data5b = 5'd22;
end
6'b101000: begin
data5b <= 5'd23;
disparity5b <= 2'b11;
data5b = 5'd23;
disparity5b = 2'b11;
end
6'b010111: begin
data5b <= 5'd23;
disparity5b <= 2'b01;
data5b = 5'd23;
disparity5b = 2'b01;
end
6'b001100: begin
data5b <= 5'd24;
disparity5b <= 2'b11;
data5b = 5'd24;
disparity5b = 2'b11;
end
6'b110011: begin
data5b <= 5'd24;
disparity5b <= 2'b01;
data5b = 5'd24;
disparity5b = 2'b01;
end
6'b011001: begin
data5b <= 5'd25;
data5b = 5'd25;
end
6'b011010: begin
data5b <= 5'd26;
data5b = 5'd26;
end
6'b100100: begin
data5b <= 5'd27;
disparity5b <= 2'b11;
data5b = 5'd27;
disparity5b = 2'b11;
end
6'b011011: begin
data5b <= 5'd27;
disparity5b <= 2'b01;
data5b = 5'd27;
disparity5b = 2'b01;
end
6'b011100: begin
data5b <= 5'd28;
data5b = 5'd28;
end
6'b100010: begin
data5b <= 5'd29;
disparity5b <= 2'b11;
data5b = 5'd29;
disparity5b = 2'b11;
end
6'b011101: begin
data5b <= 5'd29;
disparity5b <= 2'b01;
data5b = 5'd29;
disparity5b = 2'b01;
end
6'b100001: begin
data5b <= 5'd30;
disparity5b <= 2'b11;
data5b = 5'd30;
disparity5b = 2'b11;
end
6'b011110: begin
data5b <= 5'd30;
disparity5b <= 2'b01;
data5b = 5'd30;
disparity5b = 2'b01;
end
6'b001010: begin
data5b <= 5'd31;
disparity5b <= 2'b11;
data5b = 5'd31;
disparity5b = 2'b11;
end
6'b110101: begin
data5b <= 5'd31;
disparity5b <= 2'b01;
data5b = 5'd31;
disparity5b = 2'b01;
end
default: begin
data5b <= 5'd00;
notintable5b <= 1'b1;
data5b = 5'd00;
notintable5b = 1'b1;
end
endcase
end
always @(*) begin
ignore3b <= 1'b0;
ignore3b = 1'b0;
case (in_char[9:6])
4'b0010: begin
disparity3b <= 2'b11;
disparity3b = 2'b11;
end
4'b1101: begin
disparity3b <= 2'b01;
disparity3b = 2'b01;
end
4'b1100: begin
disparity3b <= 2'b11;
ignore3b <= 1'b1;
disparity3b = 2'b11;
ignore3b = 1'b1;
end
4'b0011: begin
disparity3b <= 2'b01;
ignore3b <= 1'b1;
disparity3b = 2'b01;
ignore3b = 1'b1;
end
4'b0100: begin
disparity3b <= 2'b11;
disparity3b = 2'b11;
end
4'b1011: begin
disparity3b <= 2'b01;
disparity3b = 2'b01;
end
4'b1000: begin
disparity3b <= 2'b11;
disparity3b = 2'b11;
end
4'b0111: begin
disparity3b <= 2'b01;
disparity3b = 2'b01;
end
4'b0001: begin
disparity3b <= 2'b11;
disparity3b = 2'b11;
end
4'b1110: begin
disparity3b <= 2'b01;
disparity3b = 2'b01;
end
default: begin
disparity3b <= 2'b00;
disparity3b = 2'b00;
end
endcase
end
always @(*) begin
notintable3b <= 1'b0;
notintable3b = 1'b0;
if (charisk == 1'b1) begin
case (in_char[9:6] ^ {4{in_char[5]}})
4'b1101: begin
data3b <= 3'd0;
data3b = 3'd0;
end
4'b0011: begin
data3b <= 3'd3;
data3b = 3'd3;
end
4'b1011: begin
data3b <= 3'd4;
data3b = 3'd4;
end
4'b1010: begin
data3b <= 3'd5;
data3b = 3'd5;
end
4'b1110: begin
data3b <= 3'd7;
data3b = 3'd7;
end
default: begin
data3b <= 3'd0;
notintable3b <= 1'b1;
data3b = 3'd0;
notintable3b = 1'b1;
end
endcase
end else begin
case (in_char[9:6])
4'b0010: begin
data3b <= 3'd0;
data3b = 3'd0;
end
4'b1101: begin
data3b <= 3'd0;
data3b = 3'd0;
end
4'b1001: begin
data3b <= 3'd1;
data3b = 3'd1;
end
4'b1010: begin
data3b <= 3'd2;
data3b = 3'd2;
end
4'b1100: begin
data3b <= 3'd3;
data3b = 3'd3;
end
4'b0011: begin
data3b <= 3'd3;
data3b = 3'd3;
end
4'b0100: begin
data3b <= 3'd4;
data3b = 3'd4;
end
4'b1011: begin
data3b <= 3'd4;
data3b = 3'd4;
end
4'b0101: begin
data3b <= 3'd5;
data3b = 3'd5;
end
4'b0110: begin
data3b <= 3'd6;
data3b = 3'd6;
end
4'b1000: begin
data3b <= 3'd7;
notintable3b <= in_char[5:4] == 2'b00;
data3b = 3'd7;
notintable3b = in_char[5:4] == 2'b00;
end
4'b0111: begin
data3b <= 3'd7;
notintable3b <= in_char[5:4] == 2'b11;
data3b = 3'd7;
notintable3b = in_char[5:4] == 2'b11;
end
4'b0001: begin
data3b <= 3'd7;
notintable3b <= in_char[5:4] != 2'b00;
data3b = 3'd7;
notintable3b = in_char[5:4] != 2'b00;
end
4'b1110: begin
data3b <= 3'd7;
notintable3b <= in_char[5:4] != 2'b11;
data3b = 3'd7;
notintable3b = in_char[5:4] != 2'b11;
end
default: begin
data3b <= 3'd0;
notintable3b <= 1'b1;
data3b = 3'd0;
notintable3b = 1'b1;
end
endcase
end
@ -388,24 +388,24 @@ end
always @(*) begin
if (disparity3b == disparity5b && disparity3b != 2'b00) begin
notintable_disparity <= 1'b1;
notintable_disparity = 1'b1;
end else begin
notintable_disparity <= 1'b0;
notintable_disparity = 1'b0;
end
end
always @(*) begin
total_disparity <= (ignore3b ? 2'b00 : disparity3b) ^ (ignore5b ? 2'b00 : disparity5b);
total_disparity = (ignore3b ? 2'b00 : disparity3b) ^ (ignore5b ? 2'b00 : disparity5b);
if (total_disparity[0] == 1'b0 || out_notintable == 1'b1) begin
out_disparity <= in_disparity;
out_disperr <= 1'b0;
out_disparity = in_disparity;
out_disperr = 1'b0;
end else if (total_disparity[1] == 1'b1) begin
out_disparity <= 1'b0;
out_disperr <= ~in_disparity;
out_disparity = 1'b0;
out_disperr = ~in_disparity;
end else begin
out_disparity <= 1'b1;
out_disperr <= in_disparity;
out_disparity = 1'b1;
out_disperr = in_disparity;
end
end

14
library/jesd204/jesd204_soft_pcs_rx/jesd204_pattern_align.v
View File

@ -82,20 +82,20 @@ always @(*) begin
for (i = 0; i < DATA_PATH_WIDTH*10+3; i = i + 1) begin
if (i < DATA_PATH_WIDTH*10+1) begin
case (align[3:2])
2'b00: aligned_data_stage1[i] <= full_data[i];
2'b01: aligned_data_stage1[i] <= full_data[i+4];
2'b10: aligned_data_stage1[i] <= full_data[i+8];
default: aligned_data_stage1[i] <= 1'b0;
2'b00: aligned_data_stage1[i] = full_data[i];
2'b01: aligned_data_stage1[i] = full_data[i+4];
2'b10: aligned_data_stage1[i] = full_data[i+8];
default: aligned_data_stage1[i] = 1'b0;
endcase
end else begin
case (align[2])
1'b0: aligned_data_stage1[i] <= full_data[i];
default: aligned_data_stage1[i] <= full_data[i+4];
1'b0: aligned_data_stage1[i] = full_data[i];
default: aligned_data_stage1[i] = full_data[i+4];
endcase
end
end
aligned_data_stage2 <= aligned_data_stage1[align[1:0]+:DATA_PATH_WIDTH*10];
aligned_data_stage2 = aligned_data_stage1[align[1:0]+:DATA_PATH_WIDTH*10];
end
always @(posedge clk) begin

270
library/jesd204/jesd204_soft_pcs_tx/jesd204_8b10b_encoder.v
View File

@ -72,170 +72,170 @@ reg alt7;
always @(*) begin
if (in_charisk == 1'b1) begin
// Assume K28.x
data6b <= 6'b000011;
may_invert6b <= 1'b1;
disparity6b <= 1'b1;
data6b = 6'b000011;
may_invert6b = 1'b1;
disparity6b = 1'b1;
end else begin
case (in_char[4:0])
5'd00: begin
data6b <= 6'b000110;
may_invert6b <= 1'b1;
disparity6b <= 1'b1;
data6b = 6'b000110;
may_invert6b = 1'b1;
disparity6b = 1'b1;
end
5'd01: begin
data6b <= 6'b010001;
may_invert6b <= 1'b1;
disparity6b <= 1'b1;
data6b = 6'b010001;
may_invert6b = 1'b1;
disparity6b = 1'b1;
end
5'd02: begin
data6b <= 6'b010010;
may_invert6b <= 1'b1;
disparity6b <= 1'b1;
data6b = 6'b010010;
may_invert6b = 1'b1;
disparity6b = 1'b1;
end
5'd03: begin
data6b <= 6'b100011;
may_invert6b <= 1'b0;
disparity6b <= 1'b0;
data6b = 6'b100011;
may_invert6b = 1'b0;
disparity6b = 1'b0;
end
5'd04: begin
data6b <= 6'b010100;
may_invert6b <= 1'b1;
disparity6b <= 1'b1;
data6b = 6'b010100;
may_invert6b = 1'b1;
disparity6b = 1'b1;
end
5'd05: begin
data6b <= 6'b100101;
may_invert6b <= 1'b0;
disparity6b <= 1'b0;
data6b = 6'b100101;
may_invert6b = 1'b0;
disparity6b = 1'b0;
end
5'd06: begin
data6b <= 6'b100110;
may_invert6b <= 1'b0;
disparity6b <= 1'b0;
data6b = 6'b100110;
may_invert6b = 1'b0;
disparity6b = 1'b0;
end
5'd07: begin
data6b <= 6'b111000;
may_invert6b <= 1'b1;
disparity6b <= 1'b0;
data6b = 6'b111000;
may_invert6b = 1'b1;
disparity6b = 1'b0;
end
5'd08: begin
data6b <= 6'b011000;
may_invert6b <= 1'b1;
disparity6b <= 1'b1;
data6b = 6'b011000;
may_invert6b = 1'b1;
disparity6b = 1'b1;
end
5'd09: begin
data6b <= 6'b101001;
may_invert6b <= 1'b0;
disparity6b <= 1'b0;
data6b = 6'b101001;
may_invert6b = 1'b0;
disparity6b = 1'b0;
end
5'd10: begin
data6b <= 6'b101010;
may_invert6b <= 1'b0;
disparity6b <= 1'b0;
data6b = 6'b101010;
may_invert6b = 1'b0;
disparity6b = 1'b0;
end
5'd11: begin
data6b <= 6'b001011;
may_invert6b <= 1'b0;
disparity6b <= 1'b0;
data6b = 6'b001011;
may_invert6b = 1'b0;
disparity6b = 1'b0;
end
5'd12: begin
data6b <= 6'b101100;
may_invert6b <= 1'b0;
disparity6b <= 1'b0;
data6b = 6'b101100;
may_invert6b = 1'b0;
disparity6b = 1'b0;
end
5'd13: begin
data6b <= 6'b001101;
may_invert6b <= 1'b0;
disparity6b <= 1'b0;
data6b = 6'b001101;
may_invert6b = 1'b0;
disparity6b = 1'b0;
end
5'd14: begin
data6b <= 6'b001110;
may_invert6b <= 1'b0;
disparity6b <= 1'b0;
data6b = 6'b001110;
may_invert6b = 1'b0;
disparity6b = 1'b0;
end
5'd15: begin
data6b <= 6'b000101;
may_invert6b <= 1'b1;
disparity6b <= 1'b1;
data6b = 6'b000101;
may_invert6b = 1'b1;
disparity6b = 1'b1;
end
5'd16: begin
data6b <= 6'b001001;
may_invert6b <= 1'b1;
disparity6b <= 1'b1;
data6b = 6'b001001;
may_invert6b = 1'b1;
disparity6b = 1'b1;
end
5'd17: begin
data6b <= 6'b110001;
may_invert6b <= 1'b0;
disparity6b <= 1'b0;
data6b = 6'b110001;
may_invert6b = 1'b0;
disparity6b = 1'b0;
end
5'd18: begin
data6b <= 6'b110010;
may_invert6b <= 1'b0;
disparity6b <= 1'b0;
data6b = 6'b110010;
may_invert6b = 1'b0;
disparity6b = 1'b0;
end
5'd19: begin
data6b <= 6'b010011;
may_invert6b <= 1'b0;
disparity6b <= 1'b0;
data6b = 6'b010011;
may_invert6b = 1'b0;
disparity6b = 1'b0;
end
5'd20: begin
data6b <= 6'b110100;
may_invert6b <= 1'b0;
disparity6b <= 1'b0;
data6b = 6'b110100;
may_invert6b = 1'b0;
disparity6b = 1'b0;
end
5'd21: begin
data6b <= 6'b010101;
may_invert6b <= 1'b0;
disparity6b <= 1'b0;
data6b = 6'b010101;
may_invert6b = 1'b0;
disparity6b = 1'b0;
end
5'd22: begin
data6b <= 6'b010110;
may_invert6b <= 1'b0;
disparity6b <= 1'b0;
data6b = 6'b010110;
may_invert6b = 1'b0;
disparity6b = 1'b0;
end
5'd23: begin
data6b <= 6'b101000;
may_invert6b <= 1'b1;
disparity6b <= 1'b1;
data6b = 6'b101000;
may_invert6b = 1'b1;
disparity6b = 1'b1;
end
5'd24: begin
data6b <= 6'b001100;
may_invert6b <= 1'b1;
disparity6b <= 1'b1;
data6b = 6'b001100;
may_invert6b = 1'b1;
disparity6b = 1'b1;
end
5'd25: begin
data6b <= 6'b011001;
may_invert6b <= 1'b0;
disparity6b <= 1'b0;
data6b = 6'b011001;
may_invert6b = 1'b0;
disparity6b = 1'b0;
end
5'd26: begin
data6b <= 6'b011010;
may_invert6b <= 1'b0;
disparity6b <= 1'b0;
data6b = 6'b011010;
may_invert6b = 1'b0;
disparity6b = 1'b0;
end
5'd27: begin
data6b <= 6'b100100;
may_invert6b <= 1'b1;
disparity6b <= 1'b1;
data6b = 6'b100100;
may_invert6b = 1'b1;
disparity6b = 1'b1;
end
5'd28: begin
data6b <= 6'b011100;
may_invert6b <= 1'b0;
disparity6b <= 1'b0;
data6b = 6'b011100;
may_invert6b = 1'b0;
disparity6b = 1'b0;
end
5'd29: begin
data6b <= 6'b100010;
may_invert6b <= 1'b1;
disparity6b <= 1'b1;
data6b = 6'b100010;
may_invert6b = 1'b1;
disparity6b = 1'b1;
end
5'd30: begin
data6b <= 6'b100001;
may_invert6b <= 1'b1;
disparity6b <= 1'b1;
data6b = 6'b100001;
may_invert6b = 1'b1;
disparity6b = 1'b1;
end
default: begin
data6b <= 6'b001010;
may_invert6b <= 1'b1;
disparity6b <= 1'b1;
data6b = 6'b001010;
may_invert6b = 1'b1;
disparity6b = 1'b1;
end
endcase
end
@ -243,19 +243,19 @@ end
always @(*) begin
if (in_charisk == 1'b1) begin
alt7 <= 1'b1;
alt7 = 1'b1;
end else begin
// case (in_char[4:0])
// 5'd11, 5'd13, 5'd14: alt7 <= in_disparity;
// 5'd17, 5'd18, 5'd20: alt7 <= ~in_disparity;
// default: alt7 <= 1'b0;
// 5'd11, 5'd13, 5'd14: alt7 = in_disparity;
// 5'd17, 5'd18, 5'd20: alt7 = ~in_disparity;
// default: alt7 = 1'b0;
// endcase
// Slightly better packing
case ({may_invert6b,data6b[5:4]})
3'b000: alt7 <= in_disparity;
3'b011: alt7 <= ~in_disparity;
default: alt7 <= 1'b0;
3'b000: alt7 = in_disparity;
3'b011: alt7 = ~in_disparity;
default: alt7 = 1'b0;
endcase
end
end
@ -263,48 +263,48 @@ end
always @(*) begin
case (in_char[7:5])
3'd0: begin
data4b <= 4'b0010;
may_invert4b <= 1'b1;
disparity4b <= 1'b1;
data4b = 4'b0010;
may_invert4b = 1'b1;
disparity4b = 1'b1;
end
3'd1: begin
data4b <= 4'b1001;
may_invert4b <= in_charisk;
disparity4b <= 1'b0;
data4b = 4'b1001;
may_invert4b = in_charisk;
disparity4b = 1'b0;
end
3'd2: begin
data4b <= 4'b1010;
may_invert4b <= in_charisk;
disparity4b <= 1'b0;
data4b = 4'b1010;
may_invert4b = in_charisk;
disparity4b = 1'b0;
end
3'd3: begin
data4b <= 4'b1100;
may_invert4b <= 1'b1;
disparity4b <= 1'b0;
data4b = 4'b1100;
may_invert4b = 1'b1;
disparity4b = 1'b0;
end
3'd4: begin
data4b <= 4'b0100;
may_invert4b <= 1'b1;
disparity4b <= 1'b1;
data4b = 4'b0100;
may_invert4b = 1'b1;
disparity4b = 1'b1;
end
3'd5: begin
data4b <= 4'b0101;
may_invert4b <= in_charisk;
disparity4b <= 1'b0;
data4b = 4'b0101;
may_invert4b = in_charisk;
disparity4b = 1'b0;
end
3'd6: begin
data4b <= 4'b0110;
may_invert4b <= in_charisk;
disparity4b <= 1'b0;
data4b = 4'b0110;
may_invert4b = in_charisk;
disparity4b = 1'b0;
end
default: begin
if (alt7 == 1'b1) begin
data4b <= 4'b0001;
data4b = 4'b0001;
end else begin
data4b <= 4'b1000;
data4b = 4'b1000;
end
may_invert4b <= 1'b1;
disparity4b <= 1'b1;
may_invert4b = 1'b1;
disparity4b = 1'b1;
end
endcase
end
@ -314,14 +314,14 @@ assign out_disparity = disparity4b_in ^ disparity4b;
always @(*) begin
if (in_disparity == 1'b0 && may_invert6b == 1'b1) begin
out6b <= ~data6b;
out6b = ~data6b;
end else begin
out6b <= data6b;
out6b = data6b;
end
if (disparity4b_in == 1'b0 && may_invert4b == 1'b1) begin
out4b <= ~data4b;
out4b = ~data4b;
end else begin
out4b <= data4b;
out4b = data4b;
end
end

4
library/jesd204/jesd204_tx/jesd204_tx_lane.v
View File

@ -89,9 +89,9 @@ for (i = 0; i < DATA_PATH_WIDTH; i = i + 1) begin: gen_char
always @(*) begin
if (i == DATA_PATH_WIDTH-1 && eomf == 1'b1) begin
char_align[i] <= 8'h7c; // /A/
char_align[i] = 8'h7c; // /A/
end else begin
char_align[i] <= 8'hfc; // /F/
char_align[i] = 8'hfc; // /F/
end
end