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library- drp moved to up clock

main
Rejeesh Kutty 2015-06-01 13:38:29 -04:00
parent c6ebab7393
commit e7470036bf
9 changed files with 1160 additions and 1392 deletions
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239
library/common/ad_gt_channel_1.v
View File

@ -67,6 +67,11 @@ module ad_gt_channel_1 (
rx_notintable,
rx_data,
rx_comma_align_enb,
rx_ilas_f,
rx_ilas_q,
rx_ilas_a,
rx_ilas_r,
rx_cgs_k,
// transmit
@ -86,20 +91,15 @@ module ad_gt_channel_1 (
// drp interface
drp_clk,
drp_sel,
drp_addr,
drp_wr,
drp_wdata,
drp_rdata,
drp_ready,
drp_lanesel,
drp_rx_rate,
// monitor signals
rx_mon_trigger,
rx_mon_data);
up_clk,
up_drp_sel,
up_drp_addr,
up_drp_wr,
up_drp_wdata,
up_drp_rdata,
up_drp_ready,
up_drp_lanesel,
up_drp_rxrate);
// parameters
@ -141,6 +141,11 @@ module ad_gt_channel_1 (
output [ 3:0] rx_notintable;
output [31:0] rx_data;
input rx_comma_align_enb;
output [ 3:0] rx_ilas_f;
output [ 3:0] rx_ilas_q;
output [ 3:0] rx_ilas_a;
output [ 3:0] rx_ilas_r;
output [ 3:0] rx_cgs_k;
// transmit
@ -160,107 +165,75 @@ module ad_gt_channel_1 (
// drp interface
input drp_clk;
input drp_sel;
input [11:0] drp_addr;
input drp_wr;
input [15:0] drp_wdata;
output [15:0] drp_rdata;
output drp_ready;
input [ 7:0] drp_lanesel;
output [ 7:0] drp_rx_rate;
// monitor signals
output rx_mon_trigger;
output [49:0] rx_mon_data;
input up_clk;
input up_drp_sel;
input [11:0] up_drp_addr;
input up_drp_wr;
input [15:0] up_drp_wdata;
output [15:0] up_drp_rdata;
output up_drp_ready;
input [ 7:0] up_drp_lanesel;
output [ 7:0] up_drp_rxrate;
// internal registers
reg [ 3:0] rx_user_ready = 'd0;
reg [ 3:0] tx_user_ready = 'd0;
reg drp_sel_int = 'd0;
reg [11:0] drp_addr_int = 'd0;
reg drp_wr_int = 'd0;
reg [15:0] drp_wdata_int = 'd0;
reg [15:0] drp_rdata = 'd0;
reg drp_ready = 'd0;
reg [ 7:0] drp_rx_rate = 'd0;
reg rx_rst_done = 'd0;
reg tx_rst_done = 'd0;
reg up_drp_sel_int = 'd0;
reg [11:0] up_drp_addr_int = 'd0;
reg up_drp_wr_int = 'd0;
reg [15:0] up_drp_wdata_int = 'd0;
reg [15:0] up_drp_rdata = 'd0;
reg up_drp_ready = 'd0;
reg [ 7:0] up_drp_rxrate = 'd0;
// internal signals
wire rx_ilas_f_s;
wire rx_ilas_q_s;
wire rx_ilas_a_s;
wire rx_ilas_r_s;
wire rx_cgs_k_s;
wire [ 3:0] rx_valid_k_s;
wire rx_valid_k_1_s;
wire [ 2:0] rx_rate_p_s;
wire [ 7:0] rx_rate_s;
wire [ 3:0] rx_charisk_open_s;
wire [ 3:0] rx_disperr_open_s;
wire [ 3:0] rx_notintable_open_s;
wire [31:0] rx_data_open_s;
wire cpll_locked_s;
wire [15:0] drp_rdata_s;
wire drp_ready_s;
wire [ 1:0] rx_sys_clk_sel_s;
wire [ 1:0] tx_sys_clk_sel_s;
wire [ 1:0] rx_pll_clk_sel_s;
wire [ 1:0] tx_pll_clk_sel_s;
wire rx_rst_done_s;
wire tx_rst_done_s;
wire cpll_locked_s;
wire [15:0] up_drp_rdata_s;
wire up_drp_ready_s;
// monitor interface
// cgs & ilas frame characters
assign rx_mon_data[31: 0] = rx_data;
assign rx_mon_data[35:32] = rx_notintable;
assign rx_mon_data[39:36] = rx_disperr;
assign rx_mon_data[43:40] = rx_charisk;
assign rx_mon_data[44:44] = rx_valid_k_1_s;
assign rx_mon_data[45:45] = rx_cgs_k_s;
assign rx_mon_data[46:46] = rx_ilas_r_s;
assign rx_mon_data[47:47] = rx_ilas_a_s;
assign rx_mon_data[48:48] = rx_ilas_q_s;
assign rx_mon_data[49:49] = rx_ilas_f_s;
assign rx_mon_trigger = rx_valid_k_1_s;
// ilas frame characters
assign rx_ilas_f_s =
(((rx_data[31:24] == 8'hfc) && (rx_valid_k_s[ 3] == 1'b1)) ||
((rx_data[23:16] == 8'hfc) && (rx_valid_k_s[ 2] == 1'b1)) ||
((rx_data[15: 8] == 8'hfc) && (rx_valid_k_s[ 1] == 1'b1)) ||
((rx_data[ 7: 0] == 8'hfc) && (rx_valid_k_s[ 0] == 1'b1))) ? 1'b1 : 1'b0;
assign rx_ilas_q_s =
(((rx_data[31:24] == 8'h9c) && (rx_valid_k_s[ 3] == 1'b1)) ||
((rx_data[23:16] == 8'h9c) && (rx_valid_k_s[ 2] == 1'b1)) ||
((rx_data[15: 8] == 8'h9c) && (rx_valid_k_s[ 1] == 1'b1)) ||
((rx_data[ 7: 0] == 8'h9c) && (rx_valid_k_s[ 0] == 1'b1))) ? 1'b1 : 1'b0;
assign rx_ilas_a_s =
(((rx_data[31:24] == 8'h7c) && (rx_valid_k_s[ 3] == 1'b1)) ||
((rx_data[23:16] == 8'h7c) && (rx_valid_k_s[ 2] == 1'b1)) ||
((rx_data[15: 8] == 8'h7c) && (rx_valid_k_s[ 1] == 1'b1)) ||
((rx_data[ 7: 0] == 8'h7c) && (rx_valid_k_s[ 0] == 1'b1))) ? 1'b1 : 1'b0;
assign rx_ilas_r_s =
(((rx_data[31:24] == 8'h1c) && (rx_valid_k_s[ 3] == 1'b1)) ||
((rx_data[23:16] == 8'h1c) && (rx_valid_k_s[ 2] == 1'b1)) ||
((rx_data[15: 8] == 8'h1c) && (rx_valid_k_s[ 1] == 1'b1)) ||
((rx_data[ 7: 0] == 8'h1c) && (rx_valid_k_s[ 0] == 1'b1))) ? 1'b1 : 1'b0;
assign rx_cgs_k_s =
(((rx_data[31:24] == 8'hbc) && (rx_valid_k_s[ 3] == 1'b1)) &&
((rx_data[23:16] == 8'hbc) && (rx_valid_k_s[ 2] == 1'b1)) &&
((rx_data[15: 8] == 8'hbc) && (rx_valid_k_s[ 1] == 1'b1)) &&
((rx_data[ 7: 0] == 8'hbc) && (rx_valid_k_s[ 0] == 1'b1))) ? 1'b1 : 1'b0;
assign rx_ilas_f[3] = (rx_data[31:24] == 8'hfc) ? rx_valid_k_s[3] : 1'b0;
assign rx_ilas_f[2] = (rx_data[23:16] == 8'hfc) ? rx_valid_k_s[2] : 1'b0;
assign rx_ilas_f[1] = (rx_data[15: 8] == 8'hfc) ? rx_valid_k_s[1] : 1'b0;
assign rx_ilas_f[0] = (rx_data[ 7: 0] == 8'hfc) ? rx_valid_k_s[0] : 1'b0;
assign rx_ilas_q[3] = (rx_data[31:24] == 8'h9c) ? rx_valid_k_s[3] : 1'b0;
assign rx_ilas_q[2] = (rx_data[23:16] == 8'h9c) ? rx_valid_k_s[2] : 1'b0;
assign rx_ilas_q[1] = (rx_data[15: 8] == 8'h9c) ? rx_valid_k_s[1] : 1'b0;
assign rx_ilas_q[0] = (rx_data[ 7: 0] == 8'h9c) ? rx_valid_k_s[0] : 1'b0;
assign rx_ilas_a[3] = (rx_data[31:24] == 8'h7c) ? rx_valid_k_s[3] : 1'b0;
assign rx_ilas_a[2] = (rx_data[23:16] == 8'h7c) ? rx_valid_k_s[2] : 1'b0;
assign rx_ilas_a[1] = (rx_data[15: 8] == 8'h7c) ? rx_valid_k_s[1] : 1'b0;
assign rx_ilas_a[0] = (rx_data[ 7: 0] == 8'h7c) ? rx_valid_k_s[0] : 1'b0;
assign rx_ilas_r[3] = (rx_data[31:24] == 8'h1c) ? rx_valid_k_s[3] : 1'b0;
assign rx_ilas_r[2] = (rx_data[23:16] == 8'h1c) ? rx_valid_k_s[2] : 1'b0;
assign rx_ilas_r[1] = (rx_data[15: 8] == 8'h1c) ? rx_valid_k_s[1] : 1'b0;
assign rx_ilas_r[0] = (rx_data[ 7: 0] == 8'h1c) ? rx_valid_k_s[0] : 1'b0;
assign rx_cgs_k[3] = (rx_data[31:24] == 8'hbc) ? rx_valid_k_s[3] : 1'b0;
assign rx_cgs_k[2] = (rx_data[23:16] == 8'hbc) ? rx_valid_k_s[2] : 1'b0;
assign rx_cgs_k[1] = (rx_data[15: 8] == 8'hbc) ? rx_valid_k_s[1] : 1'b0;
assign rx_cgs_k[0] = (rx_data[ 7: 0] == 8'hbc) ? rx_valid_k_s[0] : 1'b0;
// validate all characters
assign rx_valid_k_s = rx_charisk & (~rx_disperr) & (~rx_notintable);
assign rx_valid_k_1_s = (rx_valid_k_s == 4'd0) ? 1'b0 : 1'b1;
// rate
@ -294,7 +267,7 @@ module ad_gt_channel_1 (
// user ready
always @(posedge drp_clk) begin
always @(posedge up_clk) begin
if ((rx_rst == 1'b1) || (rx_pll_locked == 1'b0)) begin
rx_user_ready <= 4'd0;
end else begin
@ -302,7 +275,7 @@ module ad_gt_channel_1 (
end
end
always @(posedge drp_clk) begin
always @(posedge up_clk) begin
if ((tx_rst == 1'b1) || (tx_pll_locked == 1'b0)) begin
tx_user_ready <= 4'd0;
end else begin
@ -310,25 +283,35 @@ module ad_gt_channel_1 (
end
end
// reset done
always @(posedge rx_clk) begin
rx_rst_done <= rx_rst_done_s;
end
always @(posedge tx_clk) begin
tx_rst_done <= tx_rst_done_s;
end
// drp control
always @(posedge drp_clk) begin
if (drp_lanesel == DRP_ID) begin
drp_sel_int <= drp_sel;
drp_addr_int <= drp_addr;
drp_wr_int <= drp_wr;
drp_wdata_int <= drp_wdata;
drp_rdata <= drp_rdata_s;
drp_ready <= drp_ready_s;
drp_rx_rate <= rx_rate_s;
always @(posedge up_clk) begin
if (up_drp_lanesel == DRP_ID) begin
up_drp_sel_int <= up_drp_sel;
up_drp_addr_int <= up_drp_addr;
up_drp_wr_int <= up_drp_wr;
up_drp_wdata_int <= up_drp_wdata;
up_drp_rdata <= up_drp_rdata_s;
up_drp_ready <= up_drp_ready_s;
up_drp_rxrate <= rx_rate_s;
end else begin
drp_sel_int <= 1'd0;
drp_addr_int <= 12'd0;
drp_wr_int <= 1'd0;
drp_wdata_int <= 16'd0;
drp_rdata <= 16'd0;
drp_ready <= 1'd0;
drp_rx_rate <= 8'd0;
up_drp_sel_int <= 1'd0;
up_drp_addr_int <= 12'd0;
up_drp_wr_int <= 1'd0;
up_drp_wdata_int <= 16'd0;
up_drp_rdata <= 16'd0;
up_drp_ready <= 1'd0;
up_drp_rxrate <= 8'd0;
end
end
@ -539,7 +522,7 @@ module ad_gt_channel_1 (
i_gtxe2_channel (
.CPLLFBCLKLOST (),
.CPLLLOCK (cpll_locked_s),
.CPLLLOCKDETCLK (drp_clk),
.CPLLLOCKDETCLK (up_clk),
.CPLLLOCKEN (1'd1),
.CPLLPD (cpll_pd),
.CPLLREFCLKLOST (),
@ -560,13 +543,13 @@ module ad_gt_channel_1 (
.GTREFCLK1 (1'd0),
.GTSOUTHREFCLK0 (1'd0),
.GTSOUTHREFCLK1 (1'd0),
.DRPADDR (drp_addr_int[8:0]),
.DRPCLK (drp_clk),
.DRPDI (drp_wdata_int),
.DRPDO (drp_rdata_s),
.DRPEN (drp_sel_int),
.DRPRDY (drp_ready_s),
.DRPWE (drp_wr_int),
.DRPADDR (up_drp_addr_int[8:0]),
.DRPCLK (up_clk),
.DRPDI (up_drp_wdata_int),
.DRPDO (up_drp_rdata_s),
.DRPEN (up_drp_sel_int),
.DRPRDY (up_drp_ready_s),
.DRPWE (up_drp_wr_int),
.GTREFCLKMONITOR (),
.QPLLCLK (qpll_clk),
.QPLLREFCLK (qpll_ref_clk),
@ -690,7 +673,7 @@ module ad_gt_channel_1 (
.RXCHARISCOMMA (),
.RXCHARISK ({rx_charisk_open_s, rx_charisk}),
.RXCHBONDI (5'd0),
.RXRESETDONE (rx_rst_done),
.RXRESETDONE (rx_rst_done_s),
.RXQPIEN (1'd0),
.RXQPISENN (),
.RXQPISENP (),
@ -755,7 +738,7 @@ module ad_gt_channel_1 (
.TXSTARTSEQ (1'd0),
.TXPCSRESET (1'd0),
.TXPMARESET (1'd0),
.TXRESETDONE (tx_rst_done),
.TXRESETDONE (tx_rst_done_s),
.TXCOMFINISH (),
.TXCOMINIT (1'd0),
.TXCOMSAS (1'd0),
@ -1162,18 +1145,18 @@ module ad_gt_channel_1 (
.CFGRESET (1'd0),
.CLKRSVD0 (1'd0),
.CLKRSVD1 (1'd0),
.CPLLLOCKDETCLK (drp_clk),
.CPLLLOCKDETCLK (up_clk),
.CPLLLOCKEN (1'd1),
.CPLLPD (cpll_pd),
.CPLLREFCLKSEL (3'b001),
.CPLLRESET (cpll_rst),
.DMONFIFORESET (1'd0),
.DMONITORCLK (1'd0),
.DRPADDR (drp_addr_int[8:0]),
.DRPCLK (drp_clk),
.DRPDI (drp_wdata_int),
.DRPEN (drp_sel_int),
.DRPWE (drp_wr_int),
.DRPADDR (up_drp_addr_int[8:0]),
.DRPCLK (up_clk),
.DRPDI (up_drp_wdata_int),
.DRPEN (up_drp_sel_int),
.DRPWE (up_drp_wr_int),
.EVODDPHICALDONE (1'd0),
.EVODDPHICALSTART (1'd0),
.EVODDPHIDRDEN (1'd0),
@ -1400,8 +1383,8 @@ module ad_gt_channel_1 (
.CPLLLOCK (cpll_locked_s),
.CPLLREFCLKLOST (),
.DMONITOROUT (),
.DRPDO (drp_rdata_s),
.DRPRDY (drp_ready_s),
.DRPDO (up_drp_rdata_s),
.DRPRDY (up_drp_ready_s),
.EYESCANDATAERROR (),
.GTHTXN (tx_n),
.GTHTXP (tx_p),
@ -1462,7 +1445,7 @@ module ad_gt_channel_1 (
.RXQPISENP (),
.RXRATEDONE (),
.RXRECCLKOUT (),
.RXRESETDONE (rx_rst_done),
.RXRESETDONE (rx_rst_done_s),
.RXSLIDERDY (),
.RXSLIPDONE (),
.RXSLIPOUTCLKRDY (),
@ -1485,7 +1468,7 @@ module ad_gt_channel_1 (
.TXQPISENN (),
.TXQPISENP (),
.TXRATEDONE (),
.TXRESETDONE (tx_rst_done),
.TXRESETDONE (tx_rst_done_s),
.TXSYNCDONE (),
.TXSYNCOUT ());
end

118
library/common/ad_gt_common_1.v
View File

@ -49,15 +49,15 @@ module ad_gt_common_1 (
// drp interface
drp_clk,
drp_sel,
drp_addr,
drp_wr,
drp_wdata,
drp_rdata,
drp_ready,
drp_lanesel,
drp_rx_rate);
up_clk,
up_drp_sel,
up_drp_addr,
up_drp_wr,
up_drp_wdata,
up_drp_rdata,
up_drp_ready,
up_drp_lanesel,
up_drp_rxrate);
// parameters
@ -78,50 +78,50 @@ module ad_gt_common_1 (
// drp interface
input drp_clk;
input drp_sel;
input [11:0] drp_addr;
input drp_wr;
input [15:0] drp_wdata;
output [15:0] drp_rdata;
output drp_ready;
input [ 7:0] drp_lanesel;
output [ 7:0] drp_rx_rate;
input up_clk;
input up_drp_sel;
input [11:0] up_drp_addr;
input up_drp_wr;
input [15:0] up_drp_wdata;
output [15:0] up_drp_rdata;
output up_drp_ready;
input [ 7:0] up_drp_lanesel;
output [ 7:0] up_drp_rxrate;
// internal registers
reg drp_sel_int;
reg [11:0] drp_addr_int;
reg drp_wr_int;
reg [15:0] drp_wdata_int;
reg [15:0] drp_rdata;
reg drp_ready;
reg [ 7:0] drp_rx_rate;
reg up_drp_sel_int;
reg [11:0] up_drp_addr_int;
reg up_drp_wr_int;
reg [15:0] up_drp_wdata_int;
reg [15:0] up_drp_rdata;
reg up_drp_ready;
reg [ 7:0] up_drp_rxrate;
// internal wires
wire [15:0] drp_rdata_s;
wire drp_ready_s;
wire [15:0] up_drp_rdata_s;
wire up_drp_ready_s;
// drp control
always @(posedge drp_clk) begin
if (drp_lanesel == DRP_ID) begin
drp_sel_int <= drp_sel;
drp_addr_int <= drp_addr;
drp_wr_int <= drp_wr;
drp_wdata_int <= drp_wdata;
drp_rdata <= drp_rdata_s;
drp_ready <= drp_ready_s;
drp_rx_rate <= 8'hff;
always @(posedge up_clk) begin
if (up_drp_lanesel == DRP_ID) begin
up_drp_sel_int <= up_drp_sel;
up_drp_addr_int <= up_drp_addr;
up_drp_wr_int <= up_drp_wr;
up_drp_wdata_int <= up_drp_wdata;
up_drp_rdata <= up_drp_rdata_s;
up_drp_ready <= up_drp_ready_s;
up_drp_rxrate <= 8'hff;
end else begin
drp_sel_int <= 1'd0;
drp_addr_int <= 12'd0;
drp_wr_int <= 1'd0;
drp_wdata_int <= 16'd0;
drp_rdata <= 16'd0;
drp_ready <= 1'd0;
drp_rx_rate <= 8'd0;
up_drp_sel_int <= 1'd0;
up_drp_addr_int <= 12'd0;
up_drp_wr_int <= 1'd0;
up_drp_wdata_int <= 16'd0;
up_drp_rdata <= 16'd0;
up_drp_ready <= 1'd0;
up_drp_rxrate <= 8'd0;
end
end
@ -150,13 +150,13 @@ module ad_gt_common_1 (
.QPLL_LPF (4'b1111),
.QPLL_REFCLK_DIV (QPLL_REFCLK_DIV))
i_gtxe2_common (
.DRPCLK (drp_clk),
.DRPEN (drp_sel_int),
.DRPADDR (drp_addr_int[7:0]),
.DRPWE (drp_wr_int),
.DRPDI (drp_wdata_int),
.DRPDO (drp_rdata_s),
.DRPRDY (drp_ready_s),
.DRPCLK (up_clk),
.DRPEN (up_drp_sel_int),
.DRPADDR (up_drp_addr_int[7:0]),
.DRPWE (up_drp_wr_int),
.DRPDI (up_drp_wdata_int),
.DRPDO (up_drp_rdata_s),
.DRPRDY (up_drp_ready_s),
.GTGREFCLK (1'd0),
.GTNORTHREFCLK0 (1'd0),
.GTNORTHREFCLK1 (1'd0),
@ -170,7 +170,7 @@ module ad_gt_common_1 (
.REFCLKOUTMONITOR (),
.QPLLFBCLKLOST (),
.QPLLLOCK (qpll_locked),
.QPLLLOCKDETCLK (drp_clk),
.QPLLLOCKDETCLK (up_clk),
.QPLLLOCKEN (1'd1),
.QPLLOUTRESET (1'd0),
.QPLLPD (1'd0),
@ -268,11 +268,11 @@ module ad_gt_common_1 (
.BGPDB (1'd1),
.BGRCALOVRD (5'b11111),
.BGRCALOVRDENB (1'd1),
.DRPADDR (drp_addr_int[8:0]),
.DRPCLK (drp_clk),
.DRPDI (drp_wdata_int),
.DRPEN (drp_sel_int),
.DRPWE (drp_wr_int),
.DRPADDR (up_drp_addr_int[8:0]),
.DRPCLK (up_clk),
.DRPDI (up_drp_wdata_int),
.DRPEN (up_drp_sel_int),
.DRPWE (up_drp_wr_int),
.GTGREFCLK0 (1'd0),
.GTGREFCLK1 (1'd0),
.GTNORTHREFCLK00 (1'd0),
@ -295,7 +295,7 @@ module ad_gt_common_1 (
.QPLLRSVD4 (8'd0),
.QPLL0CLKRSVD0 (1'd0),
.QPLL0CLKRSVD1 (1'd0),
.QPLL0LOCKDETCLK (drp_clk),
.QPLL0LOCKDETCLK (up_clk),
.QPLL0LOCKEN (1'd1),
.QPLL0PD (1'd0),
.QPLL0REFCLKSEL (3'b001),
@ -308,8 +308,8 @@ module ad_gt_common_1 (
.QPLL1REFCLKSEL (3'b001),
.QPLL1RESET (1'd1),
.RCALENB (1'd1),
.DRPDO (drp_rdata_s),
.DRPRDY (drp_ready_s),
.DRPDO (up_drp_rdata_s),
.DRPRDY (up_drp_ready_s),
.PMARSVDOUT0 (),
.PMARSVDOUT1 (),
.QPLLDMONITOR0 (),

1255
library/common/ad_gt_es.v
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96
library/common/ad_mmcm_drp.v
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@ -34,8 +34,6 @@
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// MMCM with DRP and device specific
`timescale 1ns/100ps
@ -51,15 +49,15 @@ module ad_mmcm_drp (
// drp interface
drp_clk,
drp_rst,
drp_sel,
drp_wr,
drp_addr,
drp_wdata,
drp_rdata,
drp_ready,
drp_locked);
up_clk,
up_rstn,
up_drp_sel,
up_drp_wr,
up_drp_addr,
up_drp_wdata,
up_drp_rdata,
up_drp_ready,
up_drp_locked);
// parameters
@ -82,22 +80,22 @@ module ad_mmcm_drp (
// drp interface
input drp_clk;
input drp_rst;
input drp_sel;
input drp_wr;
input [11:0] drp_addr;
input [15:0] drp_wdata;
output [15:0] drp_rdata;
output drp_ready;
output drp_locked;
input up_clk;
input up_rstn;
input up_drp_sel;
input up_drp_wr;
input [11:0] up_drp_addr;
input [15:0] up_drp_wdata;
output [15:0] up_drp_rdata;
output up_drp_ready;
output up_drp_locked;
// internal registers
reg [15:0] drp_rdata = 'd0;
reg drp_ready = 'd0;
reg drp_locked_m1 = 'd0;
reg drp_locked = 'd0;
reg [15:0] up_drp_rdata = 'd0;
reg up_drp_ready = 'd0;
reg up_drp_locked_m1 = 'd0;
reg up_drp_locked = 'd0;
// internal signals
@ -106,20 +104,22 @@ module ad_mmcm_drp (
wire mmcm_clk_0_s;
wire mmcm_clk_1_s;
wire mmcm_locked_s;
wire [15:0] drp_rdata_s;
wire drp_ready_s;
wire [15:0] up_drp_rdata_s;
wire up_drp_ready_s;
// drp read and locked
always @(posedge drp_clk) begin
drp_rdata <= drp_rdata_s;
drp_ready <= drp_ready_s;
if (drp_rst == 1'b1) begin
drp_locked_m1 <= 1'd0;
drp_locked <= 1'd0;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_drp_rdata <= 'd0;
up_drp_ready <= 'd0;
up_drp_locked_m1 <= 1'd0;
up_drp_locked <= 1'd0;
end else begin
drp_locked_m1 <= mmcm_locked_s;
drp_locked <= drp_locked_m1;
up_drp_rdata <= up_drp_rdata_s;
up_drp_ready <= up_drp_ready_s;
up_drp_locked_m1 <= mmcm_locked_s;
up_drp_locked <= up_drp_locked_m1;
end
end
@ -154,13 +154,13 @@ module ad_mmcm_drp (
.CLKOUT0 (mmcm_clk_0_s),
.CLKOUT1 (mmcm_clk_1_s),
.LOCKED (mmcm_locked_s),
.DCLK (drp_clk),
.DEN (drp_sel),
.DADDR (drp_addr[6:0]),
.DWE (drp_wr),
.DI (drp_wdata),
.DO (drp_rdata_s),
.DRDY (drp_ready_s),
.DCLK (up_clk),
.DEN (up_drp_sel),
.DADDR (up_drp_addr[6:0]),
.DWE (up_drp_wr),
.DI (up_drp_wdata),
.DO (up_drp_rdata_s),
.DRDY (up_drp_ready_s),
.CLKFBOUTB (),
.CLKOUT0B (),
.CLKOUT1B (),
@ -210,13 +210,13 @@ module ad_mmcm_drp (
.CLKOUT0 (mmcm_clk_0_s),
.CLKOUT1 (mmcm_clk_1_s),
.LOCKED (mmcm_locked_s),
.DCLK (drp_clk),
.DEN (drp_sel),
.DADDR (drp_addr[6:0]),
.DWE (drp_wr),
.DI (drp_wdata),
.DO (drp_rdata_s),
.DRDY (drp_ready_s),
.DCLK (up_clk),
.DEN (up_drp_sel),
.DADDR (up_drp_addr[6:0]),
.DWE (up_drp_wr),
.DI (up_drp_wdata),
.DO (up_drp_rdata_s),
.DRDY (up_drp_ready_s),
.CLKFBOUTB (),
.CLKOUT0B (),
.CLKOUT1B (),

56
library/common/ad_serdes_clk.v
View File

@ -34,8 +34,6 @@
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// serial data output interface: serdes(x8) or oddr(x2) output module
`timescale 1ps/1ps
@ -53,15 +51,15 @@ module ad_serdes_clk (
// drp interface
drp_clk,
drp_rst,
drp_sel,
drp_wr,
drp_addr,
drp_wdata,
drp_rdata,
drp_ready,
drp_locked);
up_clk,
up_rstn,
up_drp_sel,
up_drp_wr,
up_drp_addr,
up_drp_wdata,
up_drp_rdata,
up_drp_ready,
up_drp_locked);
// parameters
@ -85,15 +83,15 @@ module ad_serdes_clk (
// drp interface
input drp_clk;
input drp_rst;
input drp_sel;
input drp_wr;
input [11:0] drp_addr;
input [15:0] drp_wdata;
output [15:0] drp_rdata;
output drp_ready;
output drp_locked;
input up_clk;
input up_rstn;
input up_drp_sel;
input up_drp_wr;
input [11:0] up_drp_addr;
input [15:0] up_drp_wdata;
output [15:0] up_drp_rdata;
output up_drp_ready;
output up_drp_locked;
// internal signals
@ -120,15 +118,15 @@ module ad_serdes_clk (
.mmcm_rst (mmcm_rst),
.mmcm_clk_0 (clk),
.mmcm_clk_1 (div_clk),
.drp_clk (drp_clk),
.drp_rst (drp_rst),
.drp_sel (drp_sel),
.drp_wr (drp_wr),
.drp_addr (drp_addr),
.drp_wdata (drp_wdata),
.drp_rdata (drp_rdata),
.drp_ready (drp_ready),
.drp_locked (drp_locked));
.up_clk (up_clk),
.up_rstn (up_rstn),
.up_drp_sel (up_drp_sel),
.up_drp_wr (up_drp_wr),
.up_drp_addr (up_drp_addr),
.up_drp_wdata (up_drp_wdata),
.up_drp_rdata (up_drp_rdata),
.up_drp_ready (up_drp_ready),
.up_drp_locked (up_drp_locked));
end
if ((MMCM == 0) && (SERDES == 0)) begin

103
library/common/up_adc_common.v
View File

@ -34,8 +34,6 @@
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
@ -68,15 +66,13 @@ module up_adc_common (
// drp interface
drp_clk,
drp_rst,
drp_sel,
drp_wr,
drp_addr,
drp_wdata,
drp_rdata,
drp_ready,
drp_locked,
up_drp_sel,
up_drp_wr,
up_drp_addr,
up_drp_wdata,
up_drp_rdata,
up_drp_ready,
up_drp_locked,
// user channel control
@ -130,15 +126,13 @@ module up_adc_common (
// drp interface
input drp_clk;
output drp_rst;
output drp_sel;
output drp_wr;
output [11:0] drp_addr;
output [15:0] drp_wdata;
input [15:0] drp_rdata;
input drp_ready;
input drp_locked;
output up_drp_sel;
output up_drp_wr;
output [11:0] up_drp_addr;
output [15:0] up_drp_wdata;
input [15:0] up_drp_rdata;
input up_drp_ready;
input up_drp_locked;
// user channel control
@ -169,10 +163,13 @@ module up_adc_common (
reg up_adc_r1_mode = 'd0;
reg up_adc_ddr_edgesel = 'd0;
reg up_adc_pin_mode = 'd0;
reg up_drp_sel_t = 'd0;
reg up_drp_sel = 'd0;
reg up_drp_wr = 'd0;
reg up_drp_status = 'd0;
reg up_drp_rwn = 'd0;
reg [11:0] up_drp_addr = 'd0;
reg [15:0] up_drp_wdata = 'd0;
reg [15:0] up_drp_rdata_hold = 'd0;
reg up_status_ovf = 'd0;
reg up_status_unf = 'd0;
reg [ 7:0] up_usr_chanmax = 'd0;
@ -194,9 +191,6 @@ module up_adc_common (
wire up_status_unf_s;
wire up_cntrl_xfer_done;
wire [31:0] up_adc_clk_count_s;
wire [15:0] up_drp_rdata_s;
wire up_drp_status_s;
wire up_drp_locked_s;
// decode block select
@ -216,10 +210,13 @@ module up_adc_common (
up_adc_r1_mode <= 'd0;
up_adc_ddr_edgesel <= 'd0;
up_adc_pin_mode <= 'd0;
up_drp_sel_t <= 'd0;
up_drp_sel <= 'd0;
up_drp_wr <= 'd0;
up_drp_status <= 'd0;
up_drp_rwn <= 'd0;
up_drp_addr <= 'd0;
up_drp_wdata <= 'd0;
up_drp_rdata_hold <= 'd0;
up_status_ovf <= 'd0;
up_status_unf <= 'd0;
up_usr_chanmax <= 'd0;
@ -247,11 +244,25 @@ module up_adc_common (
up_adc_pin_mode <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin
up_drp_sel_t <= ~up_drp_sel_t;
up_drp_sel <= 1'b1;
up_drp_wr <= ~up_wdata[28];
end else begin
up_drp_sel <= 1'b0;
up_drp_wr <= 1'b0;
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin
up_drp_status <= 1'b1;
end else if (up_drp_ready == 1'b1) begin
up_drp_status <= 1'b0;
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin
up_drp_rwn <= up_wdata[28];
up_drp_addr <= up_wdata[27:16];
up_drp_wdata <= up_wdata[15:0];
end
if (up_drp_ready == 1'b1) begin
up_drp_rdata_hold <= up_drp_rdata;
end
if (up_status_ovf_s == 1'b1) begin
up_status_ovf <= 1'b1;
end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h22)) begin
@ -294,7 +305,7 @@ module up_adc_common (
8'h17: up_rdata <= {28'd0, up_status_pn_err, up_status_pn_oos, up_status_or, up_status_s};
8'h1a: up_rdata <= {31'd0, up_sync_status_s};
8'h1c: up_rdata <= {3'd0, up_drp_rwn, up_drp_addr, up_drp_wdata};
8'h1d: up_rdata <= {14'd0, up_drp_locked_s, up_drp_status_s, up_drp_rdata_s};
8'h1d: up_rdata <= {14'd0, up_drp_locked, up_drp_status, up_drp_rdata_hold};
8'h22: up_rdata <= {29'd0, up_status_ovf, up_status_unf, 1'b0};
8'h23: up_rdata <= 32'd8;
8'h28: up_rdata <= {24'd0, adc_usr_chanmax};
@ -311,16 +322,16 @@ module up_adc_common (
// resets
ad_rst i_mmcm_rst_reg (.preset(up_mmcm_preset_s), .clk(drp_clk), .rst(mmcm_rst));
ad_rst i_mmcm_rst_reg (.preset(up_mmcm_preset_s), .clk(up_clk), .rst(mmcm_rst));
ad_rst i_adc_rst_reg (.preset(up_preset_s), .clk(adc_clk), .rst(adc_rst));
ad_rst i_drp_rst_reg (.preset(up_preset_s), .clk(drp_clk), .rst(drp_rst));
// adc control & status
up_xfer_cntrl #(.DATA_WIDTH(4)) i_adc_xfer_cntrl (
up_xfer_cntrl #(.DATA_WIDTH(36)) i_adc_xfer_cntrl (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_data_cntrl ({ up_adc_sync,
up_adc_start_code,
up_adc_r1_mode,
up_adc_ddr_edgesel,
up_adc_pin_mode}),
@ -328,6 +339,7 @@ module up_adc_common (
.d_rst (adc_rst),
.d_clk (adc_clk),
.d_data_cntrl ({ adc_sync,
adc_start_code,
adc_r1_mode,
adc_ddr_edgesel,
adc_pin_mode}));
@ -346,15 +358,6 @@ module up_adc_common (
adc_status_ovf,
adc_status_unf}));
up_xfer_cntrl #(.DATA_WIDTH(32)) i_adc_xfer_start_code (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_data_cntrl (up_adc_start_code),
.up_xfer_done (),
.d_rst (adc_rst),
.d_clk (adc_clk),
.d_data_cntrl (adc_start_code));
// adc clock monitor
up_clock_mon i_adc_clock_mon (
@ -364,28 +367,6 @@ module up_adc_common (
.d_rst (adc_rst),
.d_clk (adc_clk));
// drp control & status
up_drp_cntrl i_drp_cntrl (
.drp_clk (drp_clk),
.drp_rst (drp_rst),
.drp_sel (drp_sel),
.drp_wr (drp_wr),
.drp_addr (drp_addr),
.drp_wdata (drp_wdata),
.drp_rdata (drp_rdata),
.drp_ready (drp_ready),
.drp_locked (drp_locked),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_drp_sel_t (up_drp_sel_t),
.up_drp_rwn (up_drp_rwn),
.up_drp_addr (up_drp_addr),
.up_drp_wdata (up_drp_wdata),
.up_drp_rdata (up_drp_rdata_s),
.up_drp_status (up_drp_status_s),
.up_drp_locked (up_drp_locked_s));
endmodule
// ***************************************************************************

94
library/common/up_clkgen.v
View File

@ -34,8 +34,6 @@
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
@ -47,15 +45,13 @@ module up_clkgen (
// drp interface
drp_clk,
drp_rst,
drp_sel,
drp_wr,
drp_addr,
drp_wdata,
drp_rdata,
drp_ready,
drp_locked,
up_drp_sel,
up_drp_wr,
up_drp_addr,
up_drp_wdata,
up_drp_rdata,
up_drp_ready,
up_drp_locked,
// bus interface
@ -81,15 +77,13 @@ module up_clkgen (
// drp interface
input drp_clk;
output drp_rst;
output drp_sel;
output drp_wr;
output [11:0] drp_addr;
output [15:0] drp_wdata;
input [15:0] drp_rdata;
input drp_ready;
input drp_locked;
output up_drp_sel;
output up_drp_wr;
output [11:0] up_drp_addr;
output [15:0] up_drp_wdata;
input [15:0] up_drp_rdata;
input up_drp_ready;
input up_drp_locked;
// bus interface
@ -111,10 +105,13 @@ module up_clkgen (
reg [31:0] up_scratch = 'd0;
reg up_mmcm_resetn = 'd0;
reg up_resetn = 'd0;
reg up_drp_sel_t = 'd0;
reg up_drp_sel = 'd0;
reg up_drp_wr = 'd0;
reg up_drp_status = 'd0;
reg up_drp_rwn = 'd0;
reg [11:0] up_drp_addr = 'd0;
reg [15:0] up_drp_wdata = 'd0;
reg [15:0] up_drp_rdata_hold = 'd0;
reg up_rack = 'd0;
reg [31:0] up_rdata = 'd0;
@ -122,17 +119,12 @@ module up_clkgen (
wire up_wreq_s;
wire up_rreq_s;
wire up_preset_s;
wire up_mmcm_preset_s;
wire [15:0] up_drp_rdata_s;
wire up_drp_status_s;
wire up_drp_locked_s;
// decode block select
assign up_wreq_s = (up_waddr[13:8] == 6'h00) ? up_wreq : 1'b0;
assign up_rreq_s = (up_raddr[13:8] == 6'h00) ? up_rreq : 1'b0;
assign up_preset_s = ~up_resetn;
assign up_mmcm_preset_s = ~up_mmcm_resetn;
// processor write interface
@ -143,10 +135,13 @@ module up_clkgen (
up_scratch <= 'd0;
up_mmcm_resetn <= 'd0;
up_resetn <= 'd0;
up_drp_sel_t <= 'd0;
up_drp_sel <= 'd0;
up_drp_wr <= 'd0;
up_drp_status <= 'd0;
up_drp_rwn <= 'd0;
up_drp_addr <= 'd0;
up_drp_wdata <= 'd0;
up_drp_rdata_hold <= 'd0;
end else begin
up_wack <= up_wreq_s;
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin
@ -157,11 +152,25 @@ module up_clkgen (
up_resetn <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin
up_drp_sel_t <= ~up_drp_sel_t;
up_drp_sel <= 1'b1;
up_drp_wr <= ~up_wdata[28];
end else begin
up_drp_sel <= 1'b0;
up_drp_wr <= 1'b0;
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin
up_drp_status <= 1'b1;
end else if (up_drp_ready == 1'b1) begin
up_drp_status <= 1'b0;
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin
up_drp_rwn <= up_wdata[28];
up_drp_addr <= up_wdata[27:16];
up_drp_wdata <= up_wdata[15:0];
end
if (up_drp_ready == 1'b1) begin
up_drp_rdata_hold <= up_drp_rdata;
end
end
end
@ -179,9 +188,9 @@ module up_clkgen (
8'h01: up_rdata <= PCORE_ID;
8'h02: up_rdata <= up_scratch;
8'h10: up_rdata <= {30'd0, up_mmcm_resetn, up_resetn};
8'h17: up_rdata <= {31'd0, up_drp_locked_s};
8'h17: up_rdata <= {31'd0, up_drp_locked};
8'h1c: up_rdata <= {3'd0, up_drp_rwn, up_drp_addr, up_drp_wdata};
8'h1d: up_rdata <= {14'd0, up_drp_locked_s, up_drp_status_s, up_drp_rdata_s};
8'h1d: up_rdata <= {14'd0, up_drp_locked, up_drp_status, up_drp_rdata_hold};
default: up_rdata <= 0;
endcase
end else begin
@ -192,30 +201,7 @@ module up_clkgen (
// resets
ad_rst i_mmcm_rst_reg (.preset(up_mmcm_preset_s), .clk(drp_clk), .rst(mmcm_rst));
ad_rst i_drp_rst_reg (.preset(up_preset_s), .clk(drp_clk), .rst(drp_rst));
// drp control & status
up_drp_cntrl i_drp_cntrl (
.drp_clk (drp_clk),
.drp_rst (drp_rst),
.drp_sel (drp_sel),
.drp_wr (drp_wr),
.drp_addr (drp_addr),
.drp_wdata (drp_wdata),
.drp_rdata (drp_rdata),
.drp_ready (drp_ready),
.drp_locked (drp_locked),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_drp_sel_t (up_drp_sel_t),
.up_drp_rwn (up_drp_rwn),
.up_drp_addr (up_drp_addr),
.up_drp_wdata (up_drp_wdata),
.up_drp_rdata (up_drp_rdata_s),
.up_drp_status (up_drp_status_s),
.up_drp_locked (up_drp_locked_s));
ad_rst i_mmcm_rst_reg (.preset(up_mmcm_preset_s), .clk(up_clk), .rst(mmcm_rst));
endmodule

90
library/common/up_dac_common.v
View File

@ -34,8 +34,6 @@
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
@ -63,15 +61,13 @@ module up_dac_common (
// drp interface
drp_clk,
drp_rst,
drp_sel,
drp_wr,
drp_addr,
drp_wdata,
drp_rdata,
drp_ready,
drp_locked,
up_drp_sel,
up_drp_wr,
up_drp_addr,
up_drp_wdata,
up_drp_rdata,
up_drp_ready,
up_drp_locked,
// user channel control
@ -120,15 +116,13 @@ module up_dac_common (
// drp interface
input drp_clk;
output drp_rst;
output drp_sel;
output drp_wr;
output [11:0] drp_addr;
output [15:0] drp_wdata;
input [15:0] drp_rdata;
input drp_ready;
input drp_locked;
output up_drp_sel;
output up_drp_wr;
output [11:0] up_drp_addr;
output [15:0] up_drp_wdata;
input [15:0] up_drp_rdata;
input up_drp_ready;
input up_drp_locked;
// user channel control
@ -163,10 +157,13 @@ module up_dac_common (
reg up_dac_datafmt = 'd0;
reg [ 7:0] up_dac_datarate = 'd0;
reg up_dac_frame = 'd0;
reg up_drp_sel_t = 'd0;
reg up_drp_sel = 'd0;
reg up_drp_wr = 'd0;
reg up_drp_status = 'd0;
reg up_drp_rwn = 'd0;
reg [11:0] up_drp_addr = 'd0;
reg [15:0] up_drp_wdata = 'd0;
reg [15:0] up_drp_rdata_hold = 'd0;
reg up_status_ovf = 'd0;
reg up_status_unf = 'd0;
reg [ 7:0] up_usr_chanmax = 'd0;
@ -194,9 +191,6 @@ module up_dac_common (
wire dac_sync_s;
wire dac_frame_s;
wire [31:0] up_dac_clk_count_s;
wire [15:0] up_drp_rdata_s;
wire up_drp_status_s;
wire up_drp_locked_s;
// decode block select
@ -220,10 +214,13 @@ module up_dac_common (
up_dac_datafmt <= 'd0;
up_dac_datarate <= 'd0;
up_dac_frame <= 'd0;
up_drp_sel_t <= 'd0;
up_drp_sel <= 'd0;
up_drp_wr <= 'd0;
up_drp_status <= 'd0;
up_drp_rwn <= 'd0;
up_drp_addr <= 'd0;
up_drp_wdata <= 'd0;
up_drp_rdata_hold <= 'd0;
up_status_ovf <= 'd0;
up_status_ovf <= 'd0;
up_usr_chanmax <= 'd0;
@ -261,11 +258,25 @@ module up_dac_common (
up_dac_frame <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin
up_drp_sel_t <= ~up_drp_sel_t;
up_drp_sel <= 1'b1;
up_drp_wr <= ~up_wdata[28];
end else begin
up_drp_sel <= 1'b0;
up_drp_wr <= 1'b0;
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin
up_drp_status <= 1'b1;
end else if (up_drp_ready == 1'b1) begin
up_drp_status <= 1'b0;
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin
up_drp_rwn <= up_wdata[28];
up_drp_addr <= up_wdata[27:16];
up_drp_wdata <= up_wdata[15:0];
end
if (up_drp_ready == 1'b1) begin
up_drp_rdata_hold <= up_drp_rdata;
end
if (up_status_ovf_s == 1'b1) begin
up_status_ovf <= 1'b1;
end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h22)) begin
@ -308,7 +319,7 @@ module up_dac_common (
8'h16: up_rdata <= dac_clk_ratio;
8'h17: up_rdata <= {31'd0, up_status_s};
8'h1c: up_rdata <= {3'd0, up_drp_rwn, up_drp_addr, up_drp_wdata};
8'h1d: up_rdata <= {14'd0, up_drp_locked_s, up_drp_status_s, up_drp_rdata_s};
8'h1d: up_rdata <= {14'd0, up_drp_locked, up_drp_status, up_drp_rdata_hold};
8'h22: up_rdata <= {30'd0, up_status_ovf, up_status_unf};
8'h28: up_rdata <= {24'd0, dac_usr_chanmax};
8'h2e: up_rdata <= up_dac_gpio_in;
@ -323,9 +334,8 @@ module up_dac_common (
// resets
ad_rst i_mmcm_rst_reg (.preset(up_mmcm_preset_s), .clk(drp_clk), .rst(mmcm_rst));
ad_rst i_mmcm_rst_reg (.preset(up_mmcm_preset_s), .clk(up_clk), .rst(mmcm_rst));
ad_rst i_dac_rst_reg (.preset(up_preset_s), .clk(dac_clk), .rst(dac_rst));
ad_rst i_drp_rst_reg (.preset(up_preset_s), .clk(drp_clk), .rst(drp_rst));
// dac control & status
@ -387,28 +397,6 @@ module up_dac_common (
.d_rst (dac_rst),
.d_clk (dac_clk));
// drp control & status
up_drp_cntrl i_drp_cntrl (
.drp_clk (drp_clk),
.drp_rst (drp_rst),
.drp_sel (drp_sel),
.drp_wr (drp_wr),
.drp_addr (drp_addr),
.drp_wdata (drp_wdata),
.drp_rdata (drp_rdata),
.drp_ready (drp_ready),
.drp_locked (drp_locked),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_drp_sel_t (up_drp_sel_t),
.up_drp_rwn (up_drp_rwn),
.up_drp_addr (up_drp_addr),
.up_drp_wdata (up_drp_wdata),
.up_drp_rdata (up_drp_rdata_s),
.up_drp_status (up_drp_status_s),
.up_drp_locked (up_drp_locked_s));
endmodule
// ***************************************************************************

501
library/common/up_gt.v
View File

@ -34,8 +34,6 @@
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
@ -83,50 +81,47 @@ module up_gt (
// drp interface
drp_clk,
drp_rst,
drp_sel,
drp_wr,
drp_addr,
drp_wdata,
drp_rdata,
drp_ready,
drp_lanesel,
drp_rx_rate,
up_drp_sel,
up_drp_wr,
up_drp_addr,
up_drp_wdata,
up_drp_rdata,
up_drp_ready,
up_drp_lanesel,
up_drp_rxrate,
// es interface
es_sel,
es_wr,
es_addr,
es_wdata,
es_rdata,
es_ready,
es_start,
es_stop,
es_init,
es_lpm_dfe_n,
es_prescale,
es_voffset_range,
es_voffset_step,
es_voffset_max,
es_voffset_min,
es_hoffset_max,
es_hoffset_min,
es_hoffset_step,
es_start_addr,
es_sdata0,
es_sdata1,
es_sdata2,
es_sdata3,
es_sdata4,
es_qdata0,
es_qdata1,
es_qdata2,
es_qdata3,
es_qdata4,
es_dmaerr,
es_status,
up_es_drp_sel,
up_es_drp_wr,
up_es_drp_addr,
up_es_drp_wdata,
up_es_drp_rdata,
up_es_drp_ready,
up_es_start,
up_es_stop,
up_es_init,
up_es_prescale,
up_es_voffset_range,
up_es_voffset_step,
up_es_voffset_max,
up_es_voffset_min,
up_es_hoffset_max,
up_es_hoffset_min,
up_es_hoffset_step,
up_es_start_addr,
up_es_sdata0,
up_es_sdata1,
up_es_sdata2,
up_es_sdata3,
up_es_sdata4,
up_es_qdata0,
up_es_qdata1,
up_es_qdata2,
up_es_qdata3,
up_es_qdata4,
up_es_dmaerr,
up_es_status,
// bus interface
@ -189,50 +184,47 @@ module up_gt (
// drp interface
input drp_clk;
output drp_rst;
output drp_sel;
output drp_wr;
output [11:0] drp_addr;
output [15:0] drp_wdata;
input [15:0] drp_rdata;
input drp_ready;
output [ 7:0] drp_lanesel;
input [ 7:0] drp_rx_rate;
output up_drp_sel;
output up_drp_wr;
output [11:0] up_drp_addr;
output [15:0] up_drp_wdata;
input [15:0] up_drp_rdata;
input up_drp_ready;
output [ 7:0] up_drp_lanesel;
input [ 7:0] up_drp_rxrate;
// es interface
input es_sel;
input es_wr;
input [11:0] es_addr;
input [15:0] es_wdata;
output [15:0] es_rdata;
output es_ready;
output es_start;
output es_stop;
output es_init;
output es_lpm_dfe_n;
output [ 4:0] es_prescale;
output [ 1:0] es_voffset_range;
output [ 7:0] es_voffset_step;
output [ 7:0] es_voffset_max;
output [ 7:0] es_voffset_min;
output [11:0] es_hoffset_max;
output [11:0] es_hoffset_min;
output [11:0] es_hoffset_step;
output [31:0] es_start_addr;
output [15:0] es_sdata0;
output [15:0] es_sdata1;
output [15:0] es_sdata2;
output [15:0] es_sdata3;
output [15:0] es_sdata4;
output [15:0] es_qdata0;
output [15:0] es_qdata1;
output [15:0] es_qdata2;
output [15:0] es_qdata3;
output [15:0] es_qdata4;
input es_dmaerr;
input es_status;
input up_es_drp_sel;
input up_es_drp_wr;
input [11:0] up_es_drp_addr;
input [15:0] up_es_drp_wdata;
output [15:0] up_es_drp_rdata;
output up_es_drp_ready;
output up_es_start;
output up_es_stop;
output up_es_init;
output [ 4:0] up_es_prescale;
output [ 1:0] up_es_voffset_range;
output [ 7:0] up_es_voffset_step;
output [ 7:0] up_es_voffset_max;
output [ 7:0] up_es_voffset_min;
output [11:0] up_es_hoffset_max;
output [11:0] up_es_hoffset_min;
output [11:0] up_es_hoffset_step;
output [31:0] up_es_start_addr;
output [15:0] up_es_sdata0;
output [15:0] up_es_sdata1;
output [15:0] up_es_sdata2;
output [15:0] up_es_sdata3;
output [15:0] up_es_sdata4;
output [15:0] up_es_qdata0;
output [15:0] up_es_qdata1;
output [15:0] up_es_qdata2;
output [15:0] up_es_qdata3;
output [15:0] up_es_qdata4;
input up_es_dmaerr;
input up_es_status;
// bus interface
@ -249,6 +241,11 @@ module up_gt (
// internal registers
reg up_gt_pll_preset = 'd1;
reg up_gt_rx_preset = 'd1;
reg up_gt_tx_preset = 'd1;
reg up_rx_preset = 'd1;
reg up_tx_preset = 'd1;
reg up_wack = 'd0;
reg [31:0] up_scratch = 'd0;
reg up_lpm_dfe_n = 'd0;
@ -269,14 +266,19 @@ module up_gt (
reg up_tx_sysref_sel = 'd0;
reg up_tx_sysref = 'd0;
reg up_tx_sync = 'd0;
reg [ 7:0] up_lanesel = 'd0;
reg up_drp_sel_t = 'd0;
reg [ 7:0] up_drp_lanesel = 'd0;
reg up_drp_sel_int = 'd0;
reg up_drp_wr_int = 'd0;
reg up_drp_status = 'd0;
reg up_drp_rwn = 'd0;
reg [11:0] up_drp_addr = 'd0;
reg [15:0] up_drp_wdata = 'd0;
reg [11:0] up_drp_addr_int = 'd0;
reg [15:0] up_drp_wdata_int = 'd0;
reg [15:0] up_drp_rdata_hold = 'd0;
reg up_es_init = 'd0;
reg up_es_stop = 'd0;
reg up_es_stop_hold = 'd0;
reg up_es_start = 'd0;
reg up_es_start_hold = 'd0;
reg [ 4:0] up_es_prescale = 'd0;
reg [ 1:0] up_es_voffset_range = 'd0;
reg [ 7:0] up_es_voffset_step = 'd0;
@ -296,7 +298,7 @@ module up_gt (
reg [15:0] up_es_qdata3 = 'd0;
reg [15:0] up_es_qdata2 = 'd0;
reg [15:0] up_es_qdata4 = 'd0;
reg up_es_dmaerr = 'd0;
reg up_es_dmaerr_hold = 'd0;
reg up_rack = 'd0;
reg [31:0] up_rdata = 'd0;
reg [ 7:0] up_rx_rst_done_m1 = 'd0;
@ -325,20 +327,14 @@ module up_gt (
reg up_rx_status = 'd0;
reg up_tx_status_m1 = 'd0;
reg up_tx_status = 'd0;
reg drp_sel = 'd0;
reg drp_wr = 'd0;
reg [11:0] drp_addr = 'd0;
reg [15:0] drp_wdata = 'd0;
reg [15:0] es_rdata = 'd0;
reg es_ready = 'd0;
reg [15:0] drp_rdata_int = 'd0;
reg drp_ready_int = 'd0;
reg es_start_d1 = 'd0;
reg es_start_d2 = 'd0;
reg es_stop_d1 = 'd0;
reg es_stop_d2 = 'd0;
reg es_start = 'd0;
reg es_stop = 'd0;
reg up_drp_sel = 'd0;
reg up_drp_wr = 'd0;
reg [11:0] up_drp_addr = 'd0;
reg [15:0] up_drp_wdata = 'd0;
reg [15:0] up_es_drp_rdata = 'd0;
reg up_es_drp_ready = 'd0;
reg [15:0] up_drp_rdata_int = 'd0;
reg up_drp_ready_int = 'd0;
// internal signals
@ -348,25 +344,8 @@ module up_gt (
wire up_rx_pll_locked_s;
wire up_tx_rst_done_s;
wire up_tx_pll_locked_s;
wire up_drp_preset_s;
wire up_gt_pll_preset_s;
wire up_gt_rx_preset_s;
wire up_gt_tx_preset_s;
wire up_rx_preset_s;
wire up_tx_preset_s;
wire rx_sysref_s;
wire tx_sysref_s;
wire drp_sel_s;
wire drp_wr_s;
wire [11:0] drp_addr_s;
wire [15:0] drp_wdata_s;
wire [15:0] up_drp_rdata_s;
wire up_drp_status_s;
wire [ 7:0] up_drp_rx_rate_s;
wire es_start_s;
wire es_stop_s;
wire up_es_dmaerr_s;
wire up_es_status_s;
// decode block select
@ -383,12 +362,21 @@ module up_gt (
// resets
assign up_drp_preset_s = ~up_drp_resetn;
assign up_gt_pll_preset_s = ~up_gt_pll_resetn;
assign up_gt_rx_preset_s = ~(up_gt_pll_resetn & up_gt_rx_resetn & up_rx_pll_locked_s);
assign up_gt_tx_preset_s = ~(up_gt_pll_resetn & up_gt_tx_resetn & up_tx_pll_locked_s);
assign up_rx_preset_s = ~(up_gt_pll_resetn & up_gt_rx_resetn & up_rx_resetn & up_rx_pll_locked_s & up_rx_rst_done_s);
assign up_tx_preset_s = ~(up_gt_pll_resetn & up_gt_tx_resetn & up_tx_resetn & up_tx_pll_locked_s & up_tx_rst_done_s);
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_gt_pll_preset <= 1'b1;
up_gt_rx_preset <= 1'b1;
up_gt_tx_preset <= 1'b1;
up_rx_preset <= 1'b1;
up_tx_preset <= 1'b1;
end else begin
up_gt_pll_preset <= ~up_gt_pll_resetn;
up_gt_rx_preset <= ~(up_gt_pll_resetn & up_gt_rx_resetn & up_rx_pll_locked_s);
up_gt_tx_preset <= ~(up_gt_pll_resetn & up_gt_tx_resetn & up_tx_pll_locked_s);
up_rx_preset <= ~(up_gt_pll_resetn & up_gt_rx_resetn & up_rx_resetn & up_rx_pll_locked_s & up_rx_rst_done_s);
up_tx_preset <= ~(up_gt_pll_resetn & up_gt_tx_resetn & up_tx_resetn & up_tx_pll_locked_s & up_tx_rst_done_s);
end
end
// up clock domain reset done
@ -419,14 +407,19 @@ module up_gt (
up_tx_sysref_sel <= 'd0;
up_tx_sysref <= 'd0;
up_tx_sync <= 'd0;
up_lanesel <= 'd0;
up_drp_sel_t <= 'd0;
up_drp_lanesel <= 'd0;
up_drp_sel_int <= 'd0;
up_drp_wr_int <= 'd0;
up_drp_status <= 'd0;
up_drp_rwn <= 'd0;
up_drp_addr <= 'd0;
up_drp_wdata <= 'd0;
up_drp_addr_int <= 'd0;
up_drp_wdata_int <= 'd0;
up_drp_rdata_hold <= 'd0;
up_es_init <= 'd0;
up_es_stop <= 'd0;
up_es_stop_hold <= 'd0;
up_es_start <= 'd0;
up_es_start_hold <= 'd0;
up_es_prescale <= 'd0;
up_es_voffset_range <= 'd0;
up_es_voffset_step <= 'd0;
@ -446,7 +439,7 @@ module up_gt (
up_es_qdata3 <= 'd0;
up_es_qdata2 <= 'd0;
up_es_qdata4 <= 'd0;
up_es_dmaerr <= 'd0;
up_es_dmaerr_hold <= 'd0;
end else begin
up_wack <= up_wreq_s;
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin
@ -495,18 +488,44 @@ module up_gt (
up_tx_sync <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h23)) begin
up_lanesel <= up_wdata[7:0];
up_drp_lanesel <= up_wdata[7:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h24)) begin
up_drp_sel_int <= 1'b1;
up_drp_wr_int <= ~up_wdata[28];
end else begin
up_drp_sel_int <= 1'b0;
up_drp_wr_int <= 1'b0;
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h24)) begin
up_drp_status <= 1'b1;
end else if (up_drp_ready == 1'b1) begin
up_drp_status <= 1'b0;
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h24)) begin
up_drp_sel_t <= ~up_drp_sel_t;
up_drp_rwn <= up_wdata[28];
up_drp_addr <= up_wdata[27:16];
up_drp_wdata <= up_wdata[15:0];
up_drp_addr_int <= up_wdata[27:16];
up_drp_wdata_int <= up_wdata[15:0];
end
if (up_drp_ready_int == 1'b1) begin
up_drp_rdata_hold <= up_drp_rdata_int;
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h28)) begin
up_es_init <= up_wdata[2];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h28)) begin
up_es_stop <= up_wdata[1];
up_es_stop_hold <= up_wdata[1];
end else begin
up_es_stop <= 1'd0;
up_es_stop_hold <= up_es_stop_hold;
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h28)) begin
up_es_start <= up_wdata[0];
up_es_start_hold <= up_wdata[0];
end else begin
up_es_start <= 1'd0;
up_es_start_hold <= up_es_start_hold;
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h29)) begin
up_es_prescale <= up_wdata[4:0];
@ -549,10 +568,10 @@ module up_gt (
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h33)) begin
up_es_qdata4 <= up_wdata[15:0];
end
if (up_es_dmaerr_s == 1'b1) begin
up_es_dmaerr <= 1'b1;
if (up_es_dmaerr == 1'b1) begin
up_es_dmaerr_hold <= 1'b1;
end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h38)) begin
up_es_dmaerr <= up_es_dmaerr & ~up_wdata[1];
up_es_dmaerr_hold <= up_es_dmaerr_hold & ~up_wdata[1];
end
end
end
@ -584,10 +603,10 @@ module up_gt (
8'h1b: up_rdata <= {30'd0, up_tx_sysref_sel, up_tx_sysref};
8'h1c: up_rdata <= {31'd0, up_tx_sync};
8'h1d: up_rdata <= {15'd0, up_tx_status, up_tx_rst_done, up_tx_pll_locked};
8'h23: up_rdata <= {24'd0, up_lanesel};
8'h24: up_rdata <= {3'd0, up_drp_rwn, up_drp_addr, up_drp_wdata};
8'h25: up_rdata <= {15'd0, up_drp_status_s, up_drp_rdata_s};
8'h28: up_rdata <= {29'd0, up_es_init, up_es_stop, up_es_start};
8'h23: up_rdata <= {24'd0, up_drp_lanesel};
8'h24: up_rdata <= {3'd0, up_drp_rwn, up_drp_addr_int, up_drp_wdata_int};
8'h25: up_rdata <= {15'd0, up_drp_status, up_drp_rdata_int};
8'h28: up_rdata <= {29'd0, up_es_init, up_es_stop_hold, up_es_start_hold};
8'h29: up_rdata <= {27'd0, up_es_prescale};
8'h2a: up_rdata <= {6'd0, up_es_voffset_range, up_es_voffset_step, up_es_voffset_max, up_es_voffset_min};
8'h2b: up_rdata <= {4'd0, up_es_hoffset_max, 4'd0, up_es_hoffset_min};
@ -599,8 +618,8 @@ module up_gt (
8'h31: up_rdata <= {up_es_qdata1, up_es_qdata0};
8'h32: up_rdata <= {up_es_qdata3, up_es_qdata2};
8'h33: up_rdata <= up_es_qdata4;
8'h38: up_rdata <= {30'd0, up_es_dmaerr, up_es_status_s};
8'h39: up_rdata <= {24'd0, up_drp_rx_rate_s};
8'h38: up_rdata <= {30'd0, up_es_dmaerr_hold, up_es_status};
8'h39: up_rdata <= {24'd0, up_drp_rxrate};
8'h3a: up_rdata <= PCORE_DEVICE_TYPE;
default: up_rdata <= 0;
endcase
@ -612,14 +631,13 @@ module up_gt (
// resets
ad_rst i_drp_rst_reg (.preset(up_drp_preset_s), .clk(drp_clk), .rst(drp_rst));
ad_rst i_gt_pll_rst_reg (.preset(up_gt_pll_preset_s), .clk(drp_clk), .rst(gt_pll_rst));
ad_rst i_gt_rx_rst_reg (.preset(up_gt_rx_preset_s), .clk(drp_clk), .rst(gt_rx_rst));
ad_rst i_gt_tx_rst_reg (.preset(up_gt_tx_preset_s), .clk(drp_clk), .rst(gt_tx_rst));
ad_rst i_rx_rst_reg (.preset(up_rx_preset_s), .clk(rx_clk), .rst(rx_rst));
ad_rst i_j_rx_rst_reg (.preset(up_rx_preset_s), .clk(up_clk), .rst(rx_jesd_rst));
ad_rst i_tx_rst_reg (.preset(up_tx_preset_s), .clk(tx_clk), .rst(tx_rst));
ad_rst i_j_tx_rst_reg (.preset(up_tx_preset_s), .clk(up_clk), .rst(tx_jesd_rst));
ad_rst i_gt_pll_rst_reg (.preset(up_gt_pll_preset), .clk(up_clk), .rst(gt_pll_rst));
ad_rst i_gt_rx_rst_reg (.preset(up_gt_rx_preset), .clk(up_clk), .rst(gt_rx_rst));
ad_rst i_gt_tx_rst_reg (.preset(up_gt_tx_preset), .clk(up_clk), .rst(gt_tx_rst));
ad_rst i_rx_rst_reg (.preset(up_rx_preset), .clk(rx_clk), .rst(rx_rst));
ad_rst i_j_rx_rst_reg (.preset(up_rx_preset), .clk(up_clk), .rst(rx_jesd_rst));
ad_rst i_tx_rst_reg (.preset(up_tx_preset), .clk(tx_clk), .rst(tx_rst));
ad_rst i_j_tx_rst_reg (.preset(up_tx_preset), .clk(up_clk), .rst(tx_jesd_rst));
// reset done & pll locked
@ -695,7 +713,7 @@ module up_gt (
// status
always @(posedge up_clk) begin
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rx_status_m1 <= 'd0;
up_rx_status <= 'd0;
@ -709,158 +727,41 @@ module up_gt (
end
end
// drp mux (es runs on drp clock)
// drp mux
always @(posedge drp_clk) begin
if (es_status == 1'b1) begin
drp_sel <= es_sel;
drp_wr <= es_wr;
drp_addr <= es_addr;
drp_wdata <= es_wdata;
es_rdata <= drp_rdata;
es_ready <= drp_ready;
drp_rdata_int <= 16'd0;
drp_ready_int <= 1'd0;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_drp_sel <= 'd0;
up_drp_wr <= 'd0;
up_drp_addr <= 'd0;
up_drp_wdata <= 'd0;
up_es_drp_rdata <= 'd0;
up_es_drp_ready <= 'd0;
up_drp_rdata_int <= 'd0;
up_drp_ready_int <= 'd0;
end else begin
drp_sel <= drp_sel_s;
drp_wr <= drp_wr_s;
drp_addr <= drp_addr_s;
drp_wdata <= drp_wdata_s;
es_rdata <= 16'd0;
es_ready <= 1'd0;
drp_rdata_int <= drp_rdata;
drp_ready_int <= drp_ready;
if (up_es_status == 1'b1) begin
up_drp_sel <= up_es_drp_sel;
up_drp_wr <= up_es_drp_wr;
up_drp_addr <= up_es_drp_addr;
up_drp_wdata <= up_es_drp_wdata;
up_es_drp_rdata <= up_drp_rdata;
up_es_drp_ready <= up_drp_ready;
up_drp_rdata_int <= 16'd0;
up_drp_ready_int <= 1'd0;
end else begin
up_drp_sel <= up_drp_sel_int;
up_drp_wr <= up_drp_wr_int;
up_drp_addr <= up_drp_addr_int;
up_drp_wdata <= up_drp_wdata_int;
up_es_drp_rdata <= 16'd0;
up_es_drp_ready <= 1'd0;
up_drp_rdata_int <= up_drp_rdata;
up_drp_ready_int <= up_drp_ready;
end
end
end
// drp control & status
up_drp_cntrl i_drp_cntrl (
.drp_clk (drp_clk),
.drp_rst (drp_rst),
.drp_sel (drp_sel_s),
.drp_wr (drp_wr_s),
.drp_addr (drp_addr_s),
.drp_wdata (drp_wdata_s),
.drp_rdata (drp_rdata_int),
.drp_ready (drp_ready_int),
.drp_locked (1'b0),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_drp_sel_t (up_drp_sel_t),
.up_drp_rwn (up_drp_rwn),
.up_drp_addr (up_drp_addr),
.up_drp_wdata (up_drp_wdata),
.up_drp_rdata (up_drp_rdata_s),
.up_drp_status (up_drp_status_s),
.up_drp_locked ());
// drp control xfer
up_xfer_cntrl #(.DATA_WIDTH(8)) i_drp_xfer_cntrl (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_data_cntrl (up_lanesel),
.up_xfer_done (),
.d_rst (drp_rst),
.d_clk (drp_clk),
.d_data_cntrl (drp_lanesel));
// drp status xfer
up_xfer_status #(.DATA_WIDTH(8)) i_drp_xfer_status (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_data_status (up_drp_rx_rate_s),
.d_rst (drp_rst),
.d_clk (drp_clk),
.d_data_status (drp_rx_rate));
// es start & stop
always @(posedge drp_clk) begin
if (drp_rst == 1'b1) begin
es_start_d1 <= 'd0;
es_start_d2 <= 'd0;
es_stop_d1 <= 'd0;
es_stop_d2 <= 'd0;
es_start <= 'd0;
es_stop <= 'd0;
end else begin
es_start_d1 <= es_start_s;
es_start_d2 <= es_start_d1;
es_stop_d1 <= es_stop_s;
es_stop_d2 <= es_stop_d1;
es_start <= es_start_d1 & ~es_start_d2;
es_stop <= es_stop_d1 & ~es_stop_d2;
end
end
// es control & status
up_xfer_cntrl #(.DATA_WIDTH(263)) i_es_xfer_cntrl (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_data_cntrl ({ up_es_start,
up_es_stop,
up_es_init,
up_lpm_dfe_n,
up_es_prescale,
up_es_voffset_range,
up_es_voffset_step,
up_es_voffset_max,
up_es_voffset_min,
up_es_hoffset_max,
up_es_hoffset_min,
up_es_hoffset_step,
up_es_start_addr,
up_es_sdata1,
up_es_sdata0,
up_es_sdata3,
up_es_sdata2,
up_es_sdata4,
up_es_qdata1,
up_es_qdata0,
up_es_qdata3,
up_es_qdata2,
up_es_qdata4}),
.up_xfer_done (),
.d_rst (drp_rst),
.d_clk (drp_clk),
.d_data_cntrl ({ es_start_s,
es_stop_s,
es_init,
es_lpm_dfe_n,
es_prescale,
es_voffset_range,
es_voffset_step,
es_voffset_max,
es_voffset_min,
es_hoffset_max,
es_hoffset_min,
es_hoffset_step,
es_start_addr,
es_sdata1,
es_sdata0,
es_sdata3,
es_sdata2,
es_sdata4,
es_qdata1,
es_qdata0,
es_qdata3,
es_qdata2,
es_qdata4}));
// status
up_xfer_status #(.DATA_WIDTH(2)) i_es_xfer_status (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_data_status ({up_es_dmaerr_s, up_es_status_s}),
.d_rst (drp_rst),
.d_clk (drp_clk),
.d_data_status ({es_dmaerr, es_status}));
endmodule
// ***************************************************************************