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jesd204:up_common: Move cfg_links_disable to 0x086 address space

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Istvan Csomortani 2018-04-04 08:52:22 +01:00 committed by István Csomortáni
parent 36a3335093
commit e71f9e384e
2 changed files with 12 additions and 11 deletions
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13
library/jesd204/axi_jesd204_common/jesd204_up_common.v
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@ -228,8 +228,7 @@ always @(*) begin
/* 0x32-0x34 reserver for future use */
12'h080: up_rdata <= up_cfg_lanes_disable;
12'h081: up_rdata <= up_cfg_links_disable;
/* 0x82-0x83 reserved for future lane disable bits (max 128 lanes) */
/* 0x81-0x83 reserved for future lane disable bits (max 128 lanes) */
12'h084: up_rdata <= {
/* 24-31 */ 8'h00, /* Reserved for future extensions of octets_per_frame */
/* 16-23 */ up_cfg_octets_per_frame,
@ -241,7 +240,9 @@ always @(*) begin
/* 01 */ up_cfg_disable_char_replacement, /* Disable character replacement */
/* 00 */ up_cfg_disable_scrambler /* Disable scrambler */
};
/* 0x86-0x8f reserved for future use */
12'h086: up_rdata <= up_cfg_links_disable;
/* 0x87-0x8f reserved for future use */
/* 0x90-0x9f reserved for core specific configuration options */
@ -294,9 +295,6 @@ always @(posedge up_clk) begin
12'h080: begin
up_cfg_lanes_disable <= up_wdata[NUM_LANES-1:0];
end
12'h081: begin
up_cfg_links_disable <= up_wdata[NUM_LINKS-1:0];
end
12'h084: begin
up_cfg_octets_per_frame <= up_wdata[23:16];
up_cfg_beats_per_multiframe <= up_wdata[9:DATA_PATH_WIDTH];
@ -305,6 +303,9 @@ always @(posedge up_clk) begin
up_cfg_disable_char_replacement <= up_wdata[1];
up_cfg_disable_scrambler <= up_wdata[0];
end
12'h086: begin
up_cfg_links_disable <= up_wdata[NUM_LINKS-1:0];
end
endcase
end
end

10
library/jesd204/tb/axi_jesd204_rx_regmap_tb.v
View File

@ -273,16 +273,16 @@ module axi_jesd204_rx_tb;
write_reg_and_update('h200, {NUM_LANES{1'b1}});
check_all_registers();
/* Check links enable */
write_reg_and_update('h204, {NUM_LINKS{1'b1}});
check_all_registers();
/* Check JESD common config */
write_reg_and_update('h210, 32'hff03ff);
check_all_registers();
write_reg_and_update('h214, 32'h03);
check_all_registers();
/* Check links enable */
write_reg_and_update('h218, {NUM_LINKS{1'b1}});
check_all_registers();
/* Check JESD RX configuration */
write_reg_and_update('h240, 32'h103fc);
check_all_registers();
@ -293,8 +293,8 @@ module axi_jesd204_rx_tb;
/* Should be read-only when core is out of reset */
invert_register('h200); /* lanes enable */
invert_register('h204); /* links enable */
invert_register('h210); /* octets per frame, beats per multiframe */
invert_register('h218); /* links enable */
invert_register('h240); /* char replacement, scrambler */
check_all_registers();