From e71dbbd6f97d276648f01c0c9ba78f561d2ad386 Mon Sep 17 00:00:00 2001 From: Stanca Pop Date: Fri, 21 Jan 2022 20:07:37 +0200 Subject: [PATCH] cn0561_zed: Initial commit --- projects/cn0561/Readme.md | 8 + projects/cn0561/zed/Makefile | 31 ++++ projects/cn0561/zed/system_bd.tcl | 25 +++ projects/cn0561/zed/system_constr.xdc | 32 ++++ projects/cn0561/zed/system_project.tcl | 15 ++ projects/cn0561/zed/system_top.v | 245 +++++++++++++++++++++++++ 6 files changed, 356 insertions(+) create mode 100755 projects/cn0561/zed/Makefile create mode 100755 projects/cn0561/zed/system_bd.tcl create mode 100755 projects/cn0561/zed/system_constr.xdc create mode 100755 projects/cn0561/zed/system_project.tcl create mode 100755 projects/cn0561/zed/system_top.v diff --git a/projects/cn0561/Readme.md b/projects/cn0561/Readme.md index e69de29bb..677cce477 100644 --- a/projects/cn0561/Readme.md +++ b/projects/cn0561/Readme.md @@ -0,0 +1,8 @@ +# CN0561 HDL Project + +Here are some pointers to help you: + * [Board Product Page](https://www.analog.com/CN0561) + * Parts: [24-Bit, 4-Channel Simultaneous Sampling 1.5 MSPS Precision Alias Free ADC](https://www.analog.com/ad4134) + * Project Doc: https://wiki.analog.com/resources/eval/user-guides/circuits-from-the-lab/cn0561 + * HDL Doc: https://wiki.analog.com/resources/eval/user-guides/cn0561/hdl + * Linux Drivers: https://wiki.analog.com/resources/tools-software/linux-drivers-all diff --git a/projects/cn0561/zed/Makefile b/projects/cn0561/zed/Makefile new file mode 100755 index 000000000..2c167ce19 --- /dev/null +++ b/projects/cn0561/zed/Makefile @@ -0,0 +1,31 @@ +#################################################################################### +## Copyright (c) 2018 - 2021 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +PROJECT_NAME := cn0561_zed + +M_DEPS += ../common/cn0561_bd.tcl +M_DEPS += ../../scripts/adi_pd.tcl +M_DEPS += ../../common/zed/zed_system_constr.xdc +M_DEPS += ../../common/zed/zed_system_bd.tcl +M_DEPS += ../../../library/util_cdc/sync_bits.v +M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../../library/common/ad_edge_detect.v + +LIB_DEPS += axi_clkgen +LIB_DEPS += axi_dmac +LIB_DEPS += axi_hdmi_tx +LIB_DEPS += axi_i2s_adi +LIB_DEPS += axi_pwm_gen +LIB_DEPS += axi_spdif_tx +LIB_DEPS += axi_sysid +LIB_DEPS += spi_engine/axi_spi_engine +LIB_DEPS += spi_engine/spi_engine_execution +LIB_DEPS += spi_engine/spi_engine_interconnect +LIB_DEPS += spi_engine/spi_engine_offload +LIB_DEPS += sysid_rom +LIB_DEPS += util_i2c_mixer + +include ../../scripts/project-xilinx.mk diff --git a/projects/cn0561/zed/system_bd.tcl b/projects/cn0561/zed/system_bd.tcl new file mode 100755 index 000000000..b6043e1e3 --- /dev/null +++ b/projects/cn0561/zed/system_bd.tcl @@ -0,0 +1,25 @@ + +source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl +source $ad_hdl_dir/projects/scripts/adi_pd.tcl + +#system ID +ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9 +ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt" +ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9 + +adi_project_files cn0561_fmc_zed [list \ + "$ad_hdl_dir/library/common/ad_edge_detect.v" \ + "$ad_hdl_dir/library/util_cdc/sync_bits.v" \ +] + +sysid_gen_sys_init_file + +# specify ADC resolution -- the design supports 16/24/32 bit resolutions + +set adc_resolution 24 + +# ADC number of channels + +set adc_num_of_channels 4 + +source ../common/cn0561_bd.tcl diff --git a/projects/cn0561/zed/system_constr.xdc b/projects/cn0561/zed/system_constr.xdc new file mode 100755 index 000000000..8e555e528 --- /dev/null +++ b/projects/cn0561/zed/system_constr.xdc @@ -0,0 +1,32 @@ + +# cn0561 SPI configuration interface + +set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS25} [get_ports cn0561_spi_sdi] ; ## FMC_LPC_LA03_P +set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS25} [get_ports cn0561_spi_sdo] ; ## FMC_LPC_LA04_N +set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25} [get_ports cn0561_spi_sclk] ; ## FMC_LPC_LA01_CC_P +set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS25} [get_ports cn0561_spi_cs] ; ## FMC_LPC_LA05_P + +# cn0561 data interface + +set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS25} [get_ports cn0561_dclk] ; ## FMC_LPC_CLK0_M2C_P +set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS25} [get_ports cn0561_din[0]] ; ## FMC_LPC_LA00_CC_N +set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVCMOS25} [get_ports cn0561_din[1]] ; ## FMC_LPC_LA06_N +set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports cn0561_din[2]] ; ## FMC_LPC_LA02_P +set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports cn0561_din[3]] ; ## FMC_LPC_LA02_N +set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25} [get_ports cn0561_odr] ; ## FMC_LPC_LA00_CC_P + +# cn0561 GPIO lines + +set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVCMOS25} [get_ports cn0561_resetn] ; ## FMC_LPC_LA16_P +set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS25} [get_ports cn0561_pdn] ; ## FMC_LPC_LA07_P +set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports cn0561_mode] ; ## FMC_LPC_LA04_P +set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVCMOS25} [get_ports cn0561_gpio0] ; ## FMC_LPC_LA10_P +set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVCMOS25} [get_ports cn0561_gpio1] ; ## FMC_LPC_LA10_N +set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS25} [get_ports cn0561_gpio2] ; ## FMC_LPC_LA11_P +set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVCMOS25} [get_ports cn0561_gpio4] ; ## FMC_LPC_LA12_P +set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS25} [get_ports cn0561_gpio5] ; ## FMC_LPC_LA12_N +set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVCMOS25} [get_ports cn0561_gpio6] ; ## FMC_LPC_LA13_P +set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS25} [get_ports cn0561_gpio7] ; ## FMC_LPC_LA13_N +set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVCMOS25} [get_ports cn0561_pinbspi] ; ## FMC_LPC_LA06_P + +set_false_path -to [get_pins -hierarchical * -filter {NAME=~*busy_sync/inst/cdc_sync_stage1_reg[0]/D}] diff --git a/projects/cn0561/zed/system_project.tcl b/projects/cn0561/zed/system_project.tcl new file mode 100755 index 000000000..2d5f6362a --- /dev/null +++ b/projects/cn0561/zed/system_project.tcl @@ -0,0 +1,15 @@ + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +adi_project cn0561_zed + +adi_project_files cn0561_zed [list \ + "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "system_top.v" \ + "system_constr.xdc" \ + "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc"] + +adi_project_run cn0561_zed + diff --git a/projects/cn0561/zed/system_top.v b/projects/cn0561/zed/system_top.v new file mode 100755 index 000000000..7bc4e7867 --- /dev/null +++ b/projects/cn0561/zed/system_top.v @@ -0,0 +1,245 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, + + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, + + inout [31:0] gpio_bd, + + output hdmi_out_clk, + output hdmi_vsync, + output hdmi_hsync, + output hdmi_data_e, + output [15:0] hdmi_data, + + output spdif, + + output i2s_mclk, + output i2s_bclk, + output i2s_lrclk, + output i2s_sdata_out, + input i2s_sdata_in, + + + inout iic_scl, + inout iic_sda, + inout [ 1:0] iic_mux_scl, + inout [ 1:0] iic_mux_sda, + + input otg_vbusoc, + + // cn0561 SPI configuration interface + + input cn0561_spi_sdi, + output cn0561_spi_sdo, + output cn0561_spi_sclk, + output cn0561_spi_cs, + + // cn0561 data interface + + output cn0561_dclk, + input [ 3:0] cn0561_din, + output cn0561_odr, + + // cn0561 GPIO lines + + inout cn0561_resetn, + inout cn0561_pdn, + inout cn0561_mode, + inout cn0561_pinbspi, + inout cn0561_gpio0, + inout cn0561_gpio1, + inout cn0561_gpio2, + inout cn0561_gpio4, + inout cn0561_gpio5, + inout cn0561_gpio6, + inout cn0561_gpio7); + + // internal signals + + wire [63:0] gpio_i; + wire [63:0] gpio_o; + wire [63:0] gpio_t; + wire [ 1:0] iic_mux_scl_i_s; + wire [ 1:0] iic_mux_scl_o_s; + wire iic_mux_scl_t_s; + wire [ 1:0] iic_mux_sda_i_s; + wire [ 1:0] iic_mux_sda_o_s; + wire iic_mux_sda_t_s; + + // instantiations + + assign gpio_i[63:43] = gpio_o[63:43]; + ad_iobuf #( + .DATA_WIDTH(11) + ) i_iobuf_cn0561_gpio ( + .dio_t(gpio_t[42:32]), + .dio_i(gpio_o[42:32]), + .dio_o(gpio_i[42:32]), + .dio_p({cn0561_gpio7, // [42] + cn0561_gpio6, // [41] + cn0561_gpio5, // [40] + cn0561_gpio4, // [39] + cn0561_gpio2, // [38] + cn0561_gpio1, // [37] + cn0561_gpio0, // [36] + cn0561_pinbspi, // [35] + cn0561_mode, // [34] + cn0561_pdn, // [33] + cn0561_resetn})); // [32] + + ad_iobuf #( + .DATA_WIDTH(32) + ) i_iobuf ( + .dio_t(gpio_t[31:0]), + .dio_i(gpio_o[31:0]), + .dio_o(gpio_i[31:0]), + .dio_p(gpio_bd)); + + ad_iobuf #( + .DATA_WIDTH(2) + ) i_iic_mux_scl ( + .dio_t({iic_mux_scl_t_s, iic_mux_scl_t_s}), + .dio_i(iic_mux_scl_o_s), + .dio_o(iic_mux_scl_i_s), + .dio_p(iic_mux_scl)); + + ad_iobuf #( + .DATA_WIDTH(2) + ) i_iic_mux_sda ( + .dio_t({iic_mux_sda_t_s, iic_mux_sda_t_s}), + .dio_i(iic_mux_sda_o_s), + .dio_o(iic_mux_sda_i_s), + .dio_p(iic_mux_sda)); + + system_wrapper i_system_wrapper ( + .ddr_addr (ddr_addr), + .ddr_ba (ddr_ba), + .ddr_cas_n (ddr_cas_n), + .ddr_ck_n (ddr_ck_n), + .ddr_ck_p (ddr_ck_p), + .ddr_cke (ddr_cke), + .ddr_cs_n (ddr_cs_n), + .ddr_dm (ddr_dm), + .ddr_dq (ddr_dq), + .ddr_dqs_n (ddr_dqs_n), + .ddr_dqs_p (ddr_dqs_p), + .ddr_odt (ddr_odt), + .ddr_ras_n (ddr_ras_n), + .ddr_reset_n (ddr_reset_n), + .ddr_we_n (ddr_we_n), + .fixed_io_ddr_vrn (fixed_io_ddr_vrn), + .fixed_io_ddr_vrp (fixed_io_ddr_vrp), + .fixed_io_mio (fixed_io_mio), + .fixed_io_ps_clk (fixed_io_ps_clk), + .fixed_io_ps_porb (fixed_io_ps_porb), + .fixed_io_ps_srstb (fixed_io_ps_srstb), + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .gpio_t (gpio_t), + .hdmi_data (hdmi_data), + .hdmi_data_e (hdmi_data_e), + .hdmi_hsync (hdmi_hsync), + .hdmi_out_clk (hdmi_out_clk), + .hdmi_vsync (hdmi_vsync), + .i2s_bclk (i2s_bclk), + .i2s_lrclk (i2s_lrclk), + .i2s_mclk (i2s_mclk), + .i2s_sdata_in (i2s_sdata_in), + .i2s_sdata_out (i2s_sdata_out), + .iic_fmc_scl_io (iic_scl), + .iic_fmc_sda_io (iic_sda), + .iic_mux_scl_i (iic_mux_scl_i_s), + .iic_mux_scl_o (iic_mux_scl_o_s), + .iic_mux_scl_t (iic_mux_scl_t_s), + .iic_mux_sda_i (iic_mux_sda_i_s), + .iic_mux_sda_o (iic_mux_sda_o_s), + .iic_mux_sda_t (iic_mux_sda_t_s), + .spi0_clk_i (cn0561_spi_sclk), + .spi0_clk_o (cn0561_spi_sclk), + .spi0_csn_0_o (cn0561_spi_cs), + .spi0_csn_1_o (), + .spi0_csn_2_o (), + .spi0_csn_i (1'b1), + .spi0_sdi_i (cn0561_spi_sdi), + .spi0_sdo_i (cn0561_spi_sdo), + .spi0_sdo_o (cn0561_spi_sdo), + .spi1_clk_i (1'b0), + .spi1_clk_o (), + .spi1_csn_0_o (), + .spi1_csn_1_o (), + .spi1_csn_2_o (), + .spi1_csn_i (1'b1), + .spi1_sdi_i (1'b0), + .spi1_sdo_i (1'b0), + .spi1_sdo_o (), + .cn0561_di_sdo (), + .cn0561_di_sdo_t (), + .cn0561_di_sdi (cn0561_din), + .cn0561_di_cs (), + .cn0561_di_sclk (cn0561_dclk), + .cn0561_odr (cn0561_odr), + .cn0561_di_three_wire (), + .otg_vbusoc (otg_vbusoc), + .spdif (spdif)); + +endmodule + +// *************************************************************************** +// ***************************************************************************