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motor_control: Updated project to Vivado 14.2. Temporary removed XADC 

- fixed constraints
- updated interrupt system
- used ad_iobuf
- The XADC was removed because the XADC IPI generates vaux inputs 0 and 10 even if 0 and 8 are selected
main
Adrian Costina 2014-12-05 11:48:00 +02:00
parent a70d27c094
commit e6e9c0058d
4 changed files with 110 additions and 114 deletions
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74
projects/motcon1_fmc/common/motcon1_fmc_bd.tcl
View File

@ -41,22 +41,26 @@
set gpo_o [ create_bd_port -dir O -from 7 -to 0 gpo_o ] set gpo_o [ create_bd_port -dir O -from 7 -to 0 gpo_o ]
# interrupts
set motcon1_c_m_1_irq [create_bd_port -dir O motcon1_c_m_1_irq]
set motcon1_c_m_2_irq [create_bd_port -dir O motcon1_c_m_2_irq]
set motcon1_s_d_irq [create_bd_port -dir O motcon1_s_d_irq]
set motcon1_ctrl_irq [create_bd_port -dir O motcon1_ctrl_irq]
# xadc interface # xadc interface
set vp_in [ create_bd_port -dir I vp_in ] #create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux0
set vn_in [ create_bd_port -dir I vn_in ] #create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux8
set vauxp0 [ create_bd_port -dir I vauxp0 ] #create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vp_Vn
set vauxn0 [ create_bd_port -dir I vauxn0 ]
set vauxp8 [ create_bd_port -dir I vauxp8 ] #set muxaddr_out [ create_bd_port -dir O -from 4 -to 0 muxaddr_out ]
set vauxn8 [ create_bd_port -dir I vauxn8 ]
set muxaddr_out [ create_bd_port -dir O -from 4 -to 0 muxaddr_out ]
# additions to default configuration # additions to default configuration
set_property -dict [list CONFIG.NUM_PORTS {7}] $sys_concat_intc
set_property -dict [list CONFIG.NUM_MI {17}] $axi_cpu_interconnect set_property -dict [list CONFIG.NUM_MI {17}] $axi_cpu_interconnect
set_property -dict [ list CONFIG.PCW_USE_S_AXI_HP1 {1} ] $sys_ps7 set_property -dict [list CONFIG.PCW_USE_S_AXI_HP1 {1} ] $sys_ps7
set_property -dict [ list CONFIG.PCW_EN_CLK2_PORT {1} ] $sys_ps7 set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1} ] $sys_ps7
# current monitor 1 peripherals # current monitor 1 peripherals
@ -109,7 +113,8 @@
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {256}] $axi_controller_dma set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {256}] $axi_controller_dma
# controller ILA # controller ILA
set ila_controller [ create_bd_cell -type ip -vlnv xilinx.com:ip:ila:3.0 ila_controller ] set ila_controller [ create_bd_cell -type ip -vlnv xilinx.com:ip:ila:4.0 ila_controller ]
set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_controller
set_property -dict [ list CONFIG.C_ADV_TRIGGER {true} ] $ila_controller set_property -dict [ list CONFIG.C_ADV_TRIGGER {true} ] $ila_controller
set_property -dict [ list CONFIG.C_DATA_DEPTH {8192} ] $ila_controller set_property -dict [ list CONFIG.C_DATA_DEPTH {8192} ] $ila_controller
set_property -dict [ list CONFIG.C_EN_STRG_QUAL {1} ] $ila_controller set_property -dict [ list CONFIG.C_EN_STRG_QUAL {1} ] $ila_controller
@ -144,16 +149,14 @@
# xadc # xadc
set xadc_wiz_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xadc_wiz:3.0 xadc_wiz_1 ] # set xadc_wiz_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xadc_wiz:3.0 xadc_wiz_1 ]
set_property -dict [ list CONFIG.XADC_STARUP_SELECTION {simultaneous_sampling} ] $xadc_wiz_1 # set_property -dict [ list CONFIG.XADC_STARUP_SELECTION {simultaneous_sampling} ] $xadc_wiz_1
set_property -dict [ list CONFIG.OT_ALARM {false} ] $xadc_wiz_1 # set_property -dict [ list CONFIG.OT_ALARM {false} ] $xadc_wiz_1
set_property -dict [ list CONFIG.USER_TEMP_ALARM {false} ] $xadc_wiz_1 # set_property -dict [ list CONFIG.USER_TEMP_ALARM {false} ] $xadc_wiz_1
set_property -dict [ list CONFIG.VCCINT_ALARM {false} ] $xadc_wiz_1 # set_property -dict [ list CONFIG.VCCINT_ALARM {false} ] $xadc_wiz_1
set_property -dict [ list CONFIG.VCCAUX_ALARM {false} ] $xadc_wiz_1 # set_property -dict [ list CONFIG.VCCAUX_ALARM {false} ] $xadc_wiz_1
set_property -dict [ list CONFIG.ENABLE_EXTERNAL_MUX {true} ] $xadc_wiz_1 # set_property -dict [ list CONFIG.ENABLE_EXTERNAL_MUX {true} ] $xadc_wiz_1
set_property -dict [ list CONFIG.EXTERNAL_MUX_CHANNEL {VAUXP0_VAUXN0} ] $xadc_wiz_1 # set_property -dict [list CONFIG.EXTERNAL_MUX_CHANNEL {VAUXP0_VAUXN0}] $xadc_wiz_1
set_property -dict [ list CONFIG.CHANNEL_ENABLE_VAUXP0_VAUXN0 {true} ] $xadc_wiz_1
set_property -dict [ list CONFIG.CHANNEL_ENABLE_VAUXP1_VAUXN1 {false} ] $xadc_wiz_1
# additional interconnect # additional interconnect
@ -164,7 +167,7 @@
# position # position
connect_bd_net -net position_i_1 [get_bd_ports position_i] [get_bd_pins axi_mc_speed_1/position_i] connect_bd_net -net position_i_1 [get_bd_ports position_i] [get_bd_pins axi_mc_speed_1/position_i]
connect_bd_net -net position_i_1 [get_bd_pins axi_mc_speed_1/bemf_i] connect_bd_net -net position_i_1 [get_bd_pins axi_mc_speed_1/bemf_i]
# current monitor 1 # current monitor 1
@ -193,7 +196,7 @@
# interrupt # interrupt
connect_bd_net -net axi_current_monitor_1_dma_irq [get_bd_pins axi_current_monitor_1_dma/irq] [get_bd_pins sys_concat_intc/In2] connect_bd_net -net axi_current_monitor_1_dma_irq [get_bd_pins axi_current_monitor_1_dma/irq] [get_bd_ports motcon1_c_m_1_irq]
# current monitor 2 # current monitor 2
@ -214,7 +217,7 @@
#interrupt #interrupt
connect_bd_net -net axi_current_monitor_2_dma_irq [get_bd_pins axi_current_monitor_2_dma/irq] [get_bd_pins sys_concat_intc/In6] connect_bd_net -net axi_current_monitor_2_dma_irq [get_bd_pins axi_current_monitor_2_dma/irq] [get_bd_ports motcon1_c_m_2_irq]
# speed detector # speed detector
@ -229,7 +232,7 @@
# interrupt # interrupt
connect_bd_net -net axi_speed_detector_dma_irq [get_bd_pins axi_speed_detector_dma/irq] [get_bd_pins sys_concat_intc/In3] connect_bd_net -net axi_speed_detector_dma_irq [get_bd_pins axi_speed_detector_dma/irq] [get_bd_ports motcon1_s_d_irq]
# controller # controller
@ -314,20 +317,17 @@
# interrupt # interrupt
connect_bd_net -net axi_controller_dma_irq [get_bd_pins axi_controller_dma/irq] [get_bd_pins sys_concat_intc/In5] connect_bd_net -net axi_controller_dma_irq [get_bd_pins axi_controller_dma/irq] [get_bd_ports motcon1_ctrl_irq]
# xadc # xadc
connect_bd_net -net sys_100m_clk [get_bd_pins xadc_wiz_1/s_axi_aclk] $sys_100m_clk_source # connect_bd_net -net sys_100m_clk [get_bd_pins xadc_wiz_1/s_axi_aclk] $sys_100m_clk_source
connect_bd_net -net sys_100m_resetn [get_bd_pins xadc_wiz_1/s_axi_aresetn] $sys_100m_resetn_source # connect_bd_net -net sys_100m_resetn [get_bd_pins xadc_wiz_1/s_axi_aresetn] $sys_100m_resetn_source
connect_bd_net -net vp_in_1 [get_bd_ports vp_in] [get_bd_pins xadc_wiz_1/vp_in] # connect_bd_intf_net [get_bd_intf_pins xadc_wiz_1/Vp_Vn] [get_bd_intf_ports Vp_Vn]
connect_bd_net -net vn_in_1 [get_bd_ports vn_in] [get_bd_pins xadc_wiz_1/vn_in] # connect_bd_intf_net [get_bd_intf_pins xadc_wiz_1/Vaux0] [get_bd_intf_ports Vaux0]
connect_bd_net -net vauxp0_1 [get_bd_ports vauxp0] [get_bd_pins xadc_wiz_1/vauxp0] # connect_bd_intf_net [get_bd_intf_pins xadc_wiz_1/Vaux8] [get_bd_intf_ports Vaux8]
connect_bd_net -net vauxn0_1 [get_bd_ports vauxn0] [get_bd_pins xadc_wiz_1/vauxn0] # connect_bd_net -net xadc_wiz_1_muxaddr_out [get_bd_ports muxaddr_out] [get_bd_pins xadc_wiz_1/muxaddr_out]
connect_bd_net -net vauxp8_1 [get_bd_ports vauxp8] [get_bd_pins xadc_wiz_1/vauxp8]
connect_bd_net -net vauxn8_1 [get_bd_ports vauxn8] [get_bd_pins xadc_wiz_1/vauxn8]
connect_bd_net -net xadc_wiz_1_muxaddr_out [get_bd_ports muxaddr_out] [get_bd_pins xadc_wiz_1/muxaddr_out]
# interconnect (cpu) # interconnect (cpu)
@ -335,7 +335,7 @@
connect_bd_intf_net -intf_net axi_cpu_interconnect_m08_axi [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins axi_mc_speed_1/s_axi] connect_bd_intf_net -intf_net axi_cpu_interconnect_m08_axi [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins axi_mc_speed_1/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m09_axi [get_bd_intf_pins axi_cpu_interconnect/M09_AXI] [get_bd_intf_pins axi_mc_controller/s_axi] connect_bd_intf_net -intf_net axi_cpu_interconnect_m09_axi [get_bd_intf_pins axi_cpu_interconnect/M09_AXI] [get_bd_intf_pins axi_mc_controller/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m10_axi [get_bd_intf_pins axi_cpu_interconnect/M10_AXI] [get_bd_intf_pins axi_mc_current_monitor_2/s_axi] connect_bd_intf_net -intf_net axi_cpu_interconnect_m10_axi [get_bd_intf_pins axi_cpu_interconnect/M10_AXI] [get_bd_intf_pins axi_mc_current_monitor_2/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m11_axi [get_bd_intf_pins axi_cpu_interconnect/M11_AXI] [get_bd_intf_pins xadc_wiz_1/s_axi_lite] # connect_bd_intf_net -intf_net axi_cpu_interconnect_m11_axi [get_bd_intf_pins axi_cpu_interconnect/M11_AXI] [get_bd_intf_pins xadc_wiz_1/s_axi_lite]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m12_axi [get_bd_intf_pins axi_cpu_interconnect/M12_AXI] [get_bd_intf_pins axi_speed_detector_dma/s_axi] connect_bd_intf_net -intf_net axi_cpu_interconnect_m12_axi [get_bd_intf_pins axi_cpu_interconnect/M12_AXI] [get_bd_intf_pins axi_speed_detector_dma/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m13_axi [get_bd_intf_pins axi_cpu_interconnect/M13_AXI] [get_bd_intf_pins axi_current_monitor_1_dma/s_axi] connect_bd_intf_net -intf_net axi_cpu_interconnect_m13_axi [get_bd_intf_pins axi_cpu_interconnect/M13_AXI] [get_bd_intf_pins axi_current_monitor_1_dma/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m14_axi [get_bd_intf_pins axi_cpu_interconnect/M14_AXI] [get_bd_intf_pins axi_current_monitor_2_dma/s_axi] connect_bd_intf_net -intf_net axi_cpu_interconnect_m14_axi [get_bd_intf_pins axi_cpu_interconnect/M14_AXI] [get_bd_intf_pins axi_current_monitor_2_dma/s_axi]
@ -441,7 +441,7 @@
create_bd_addr_seg -range 0x10000 -offset 0x40510000 $sys_addr_cntrl_space [get_bd_addr_segs axi_mc_speed_1/s_axi/axi_lite] SEG_data_s_d create_bd_addr_seg -range 0x10000 -offset 0x40510000 $sys_addr_cntrl_space [get_bd_addr_segs axi_mc_speed_1/s_axi/axi_lite] SEG_data_s_d
create_bd_addr_seg -range 0x10000 -offset 0x40520000 $sys_addr_cntrl_space [get_bd_addr_segs axi_mc_controller/s_axi/axi_lite] SEG_data_t_c create_bd_addr_seg -range 0x10000 -offset 0x40520000 $sys_addr_cntrl_space [get_bd_addr_segs axi_mc_controller/s_axi/axi_lite] SEG_data_t_c
create_bd_addr_seg -range 0x10000 -offset 0x40530000 $sys_addr_cntrl_space [get_bd_addr_segs axi_mc_current_monitor_2/s_axi/axi_lite] SEG_data_c_m_2 create_bd_addr_seg -range 0x10000 -offset 0x40530000 $sys_addr_cntrl_space [get_bd_addr_segs axi_mc_current_monitor_2/s_axi/axi_lite] SEG_data_c_m_2
create_bd_addr_seg -range 0x10000 -offset 0x43200000 $sys_addr_cntrl_space [get_bd_addr_segs xadc_wiz_1/s_axi_lite/Reg] SEG_data_xadc # create_bd_addr_seg -range 0x10000 -offset 0x43200000 $sys_addr_cntrl_space [get_bd_addr_segs xadc_wiz_1/s_axi_lite/Reg] SEG_data_xadc
create_bd_addr_seg -range 0x4000000 -offset 0x7C000000 $sys_addr_cntrl_space [get_bd_addr_segs foc_controller/s_axi/axi_lite] SEG_foc_controller_f_c create_bd_addr_seg -range 0x4000000 -offset 0x7C000000 $sys_addr_cntrl_space [get_bd_addr_segs foc_controller/s_axi/axi_lite] SEG_foc_controller_f_c
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_current_monitor_1_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_current_monitor_1_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm

51
projects/motcon1_fmc/zed/system_constr.xdc
View File

@ -1,20 +1,5 @@
# Motor Control # Motor Control
#Test
#reset_property -dict {PACKAGE_PIN IOSTANDARD } [get_ports gpio_bd[27]] ; ## XADC-GIO0
#reset_property -dict {PACKAGE_PIN IOSTANDARD } [get_ports gpio_bd[28]] ; ## XADC-GIO1
#reset_property -dict {PACKAGE_PIN IOSTANDARD } [get_ports gpio_bd[29]] ; ## XADC-GIO2
#reset_property -dict {PACKAGE_PIN IOSTANDARD } [get_ports gpio_bd[30]] ; ## XADC-GIO3
set_property -dict {PACKAGE_PIN Y21 IOSTANDARD LVCMOS33} [get_ports gpio_bd[27]] ; ## XADC-GIO0
set_property -dict {PACKAGE_PIN Y20 IOSTANDARD LVCMOS33} [get_ports gpio_bd[28]] ; ## XADC-GIO1
set_property -dict {PACKAGE_PIN AB20 IOSTANDARD LVCMOS33} [get_ports gpio_bd[29]] ; ## XADC-GIO2
set_property -dict {PACKAGE_PIN AB19 IOSTANDARD LVCMOS33} [get_ports gpio_bd[30]] ; ## XADC-GIO3
#End Test
set_property PACKAGE_PIN J16 [get_ports {position_i[0]}] set_property PACKAGE_PIN J16 [get_ports {position_i[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports {position_i[0]}] set_property IOSTANDARD LVCMOS25 [get_ports {position_i[0]}]
set_property PACKAGE_PIN J17 [get_ports {position_i[1]}] set_property PACKAGE_PIN J17 [get_ports {position_i[1]}]
@ -89,31 +74,13 @@ set_property PACKAGE_PIN E21 [get_ports adc_it_clk_d_o]
set_property IOSTANDARD LVCMOS25 [get_ports adc_it_clk_d_o] set_property IOSTANDARD LVCMOS25 [get_ports adc_it_clk_d_o]
set_property PACKAGE_PIN H15 [get_ports {muxaddr_out[0]}] #set_property PACKAGE_PIN H15 [get_ports {muxaddr_out[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports {muxaddr_out[0]}] #set_property IOSTANDARD LVCMOS25 [get_ports {muxaddr_out[0]}]
set_property PACKAGE_PIN R15 [get_ports {muxaddr_out[1]}] #set_property PACKAGE_PIN R15 [get_ports {muxaddr_out[1]}]
set_property IOSTANDARD LVCMOS25 [get_ports {muxaddr_out[1]}] #set_property IOSTANDARD LVCMOS25 [get_ports {muxaddr_out[1]}]
set_property PACKAGE_PIN K15 [get_ports {muxaddr_out[2]}] #set_property PACKAGE_PIN K15 [get_ports {muxaddr_out[2]}]
set_property IOSTANDARD LVCMOS25 [get_ports {muxaddr_out[2]}] #set_property IOSTANDARD LVCMOS25 [get_ports {muxaddr_out[2]}]
set_property PACKAGE_PIN J15 [get_ports {muxaddr_out[3]}] #set_property PACKAGE_PIN J15 [get_ports {muxaddr_out[3]}]
set_property IOSTANDARD LVCMOS25 [get_ports {muxaddr_out[3]}] #set_property IOSTANDARD LVCMOS25 [get_ports {muxaddr_out[3]}]
set_property PACKAGE_PIN E16 [get_ports vauxn0] set_false_path -through [get_pins {i_system_wrapper/system_i/foc_controller/inst*/*/*/*}]
set_property IOSTANDARD LVCMOS25 [get_ports vauxn0]
set_property PACKAGE_PIN D17 [get_ports vauxn8]
set_property IOSTANDARD LVCMOS25 [get_ports vauxn8]
set_property PACKAGE_PIN F16 [get_ports vauxp0]
set_property IOSTANDARD LVCMOS25 [get_ports vauxp0]
set_property PACKAGE_PIN D16 [get_ports vauxp8]
set_property IOSTANDARD LVCMOS25 [get_ports vauxp8]
set_property PACKAGE_PIN M12 [get_ports vn_in]
set_property IOSTANDARD LVCMOS25 [get_ports vn_in]
set_property PACKAGE_PIN L11 [get_ports vp_in]
set_property IOSTANDARD LVCMOS25 [get_ports vp_in]
create_clock -name ctrl_clk -period 20.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK2]
create_clock -name ps7_clk_2 -period 20.00 [get_pins i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[2]]
set_clock_groups -asynchronous -group {ctrl_clk}
set_clock_groups -asynchronous -group {ps7_clk_2}

1
projects/motcon1_fmc/zed/system_project.tcl
View File

@ -6,6 +6,7 @@ adi_project_create motcon1_fmc_zed
adi_project_files motcon1_fmc_zed [list \ adi_project_files motcon1_fmc_zed [list \
"system_top.v" \ "system_top.v" \
"system_constr.xdc" \ "system_constr.xdc" \
"$ad_hdl_dir/library/common/ad_iobuf.v" \
"$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc" ] "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc" ]
adi_project_run motcon1_fmc_zed adi_project_run motcon1_fmc_zed

98
projects/motcon1_fmc/zed/system_top.v
View File

@ -97,13 +97,13 @@ module system_top (
pwm_ch_o, pwm_ch_o,
pwm_cl_o, pwm_cl_o,
vauxn0, //vauxn0,
vauxn8, //vauxn8,
vauxp0, //vauxp0,
vauxp8, //vauxp8,
vn_in, //vn_in,
vp_in, //vp_in,
muxaddr_out, //muxaddr_out,
i2s_mclk, i2s_mclk,
i2s_bclk, i2s_bclk,
@ -176,13 +176,13 @@ module system_top (
output pwm_ch_o; output pwm_ch_o;
output pwm_cl_o; output pwm_cl_o;
input vauxn0; //input vauxn0;
input vauxn8; //input vauxn8;
input vauxp0; //input vauxp0;
input vauxp8; //input vauxp8;
input vn_in; //input vn_in;
input vp_in; //input vp_in;
output [3:0]muxaddr_out; //output [3:0] muxaddr_out;
output spdif; output spdif;
@ -211,24 +211,33 @@ module system_top (
wire [ 1:0] iic_mux_sda_i_s; wire [ 1:0] iic_mux_sda_i_s;
wire [ 1:0] iic_mux_sda_o_s; wire [ 1:0] iic_mux_sda_o_s;
wire iic_mux_sda_t_s; wire iic_mux_sda_t_s;
wire [15:0] ps_intrs;
// instantiations // instantiations
genvar n; ad_iobuf #(
generate .DATA_WIDTH(32))
for (n = 0; n <= 31; n = n + 1) begin: g_iobuf_gpio_bd i_gpio_bd (
IOBUF i_iobuf_gpio_bd ( .dt(gpio_t),
.I (gpio_o[n]), .di(gpio_o),
.O (gpio_i[n]), .do(gpio_i),
.T (gpio_t[n]), .dio(gpio_bd));
.IO (gpio_bd[n]));
end
endgenerate
IOBUF i_iic_mux_scl_0 (.I(iic_mux_scl_o_s[0]), .O(iic_mux_scl_i_s[0]), .T(iic_mux_scl_t_s), .IO(iic_mux_scl[0])); ad_iobuf #(
IOBUF i_iic_mux_scl_1 (.I(iic_mux_scl_o_s[1]), .O(iic_mux_scl_i_s[1]), .T(iic_mux_scl_t_s), .IO(iic_mux_scl[1])); .DATA_WIDTH(2))
IOBUF i_iic_mux_sda_0 (.I(iic_mux_sda_o_s[0]), .O(iic_mux_sda_i_s[0]), .T(iic_mux_sda_t_s), .IO(iic_mux_sda[0])); i_iic_mux_scl (
IOBUF i_iic_mux_sda_1 (.I(iic_mux_sda_o_s[1]), .O(iic_mux_sda_i_s[1]), .T(iic_mux_sda_t_s), .IO(iic_mux_sda[1])); .dt({iic_mux_scl_t_s, iic_mux_scl_t_s}),
.di(iic_mux_scl_o_s),
.do(iic_mux_scl_i_s),
.dio(iic_mux_scl));
ad_iobuf #(
.DATA_WIDTH(2))
i_iic_mux_sda (
.dt({iic_mux_sda_t_s, iic_mux_sda_t_s}),
.di(iic_mux_sda_o_s),
.do(iic_mux_sda_i_s),
.dio(iic_mux_sda));
system_wrapper i_system_wrapper ( system_wrapper i_system_wrapper (
.DDR_addr (DDR_addr), .DDR_addr (DDR_addr),
@ -284,13 +293,13 @@ module system_top (
.pwm_bl_o(pwm_bl_o), .pwm_bl_o(pwm_bl_o),
.pwm_ch_o(pwm_ch_o), .pwm_ch_o(pwm_ch_o),
.pwm_cl_o(pwm_cl_o), .pwm_cl_o(pwm_cl_o),
.vauxn0(vauxn0), //.Vaux0_v_n(vauxn0),
.vauxn8(vauxn8), //.Vaux0_v_p(vauxp0),
.vauxp0(vauxp0), //.vauxn8(vauxn8),
.vauxp8(vauxp8), //.vauxp8(vauxp8),
.vn_in(vn_in), //.Vp_Vn_v_n(vn_in),
.vp_in(vp_in), //.Vp_Vn_v_p(vp_in),
.muxaddr_out(muxaddr_out), //.muxaddr_out(muxaddr_out),
.i2s_bclk (i2s_bclk), .i2s_bclk (i2s_bclk),
.i2s_lrclk (i2s_lrclk), .i2s_lrclk (i2s_lrclk),
.i2s_mclk (i2s_mclk), .i2s_mclk (i2s_mclk),
@ -304,6 +313,25 @@ module system_top (
.iic_mux_sda_I (iic_mux_sda_i_s), .iic_mux_sda_I (iic_mux_sda_i_s),
.iic_mux_sda_O (iic_mux_sda_o_s), .iic_mux_sda_O (iic_mux_sda_o_s),
.iic_mux_sda_T (iic_mux_sda_t_s), .iic_mux_sda_T (iic_mux_sda_t_s),
.ps_intr_0 (ps_intrs[0]),
.ps_intr_1 (ps_intrs[1]),
.ps_intr_10 (ps_intrs[10]),
.ps_intr_11 (ps_intrs[11]),
.ps_intr_12 (ps_intrs[12]),
.ps_intr_13 (ps_intrs[13]),
.ps_intr_2 (ps_intrs[2]),
.ps_intr_3 (ps_intrs[3]),
.ps_intr_4 (ps_intrs[4]),
.ps_intr_5 (ps_intrs[5]),
.ps_intr_6 (ps_intrs[6]),
.ps_intr_7 (ps_intrs[7]),
.ps_intr_8 (ps_intrs[8]),
.ps_intr_9 (ps_intrs[9]),
.iic_fmc_intr(ps_intrs[11]),
.motcon1_c_m_1_irq(ps_intrs[13]),
.motcon1_c_m_2_irq(ps_intrs[9]),
.motcon1_s_d_irq(ps_intrs[12]),
.motcon1_ctrl_irq(ps_intrs[10]),
.otg_vbusoc (otg_vbusoc), .otg_vbusoc (otg_vbusoc),
.spdif (spdif)); .spdif (spdif));