From e6b9e21ad1ed4cacdc4304404d68d5c753179f20 Mon Sep 17 00:00:00 2001 From: Laszlo Nagy Date: Fri, 19 Jul 2019 10:15:06 +0100 Subject: [PATCH] ad_serdes_out: Add tristate option --- library/axi_ad9122/axi_ad9122_if.v | 3 +++ library/axi_ad9739a/axi_ad9739a_if.v | 3 +++ library/xilinx/common/ad_serdes_out.v | 28 +++++++++++++++------------ 3 files changed, 22 insertions(+), 12 deletions(-) diff --git a/library/axi_ad9122/axi_ad9122_if.v b/library/axi_ad9122/axi_ad9122_if.v index b3fef7ed9..482467658 100644 --- a/library/axi_ad9122/axi_ad9122_if.v +++ b/library/axi_ad9122/axi_ad9122_if.v @@ -136,6 +136,7 @@ module axi_ad9122_if #( .clk (dac_clk), .div_clk (dac_div_clk), .loaden (loaden_s), + .data_oe (1'b1), .data_s0 (dac_data_i0), .data_s1 (dac_data_q0), .data_s2 (dac_data_i1), @@ -159,6 +160,7 @@ module axi_ad9122_if #( .clk (dac_clk), .div_clk (dac_div_clk), .loaden (loaden_s), + .data_oe (1'b1), .data_s0 (dac_frame_i0), .data_s1 (dac_frame_q0), .data_s2 (dac_frame_i1), @@ -182,6 +184,7 @@ module axi_ad9122_if #( .clk (dac_clk), .div_clk (dac_div_clk), .loaden (loaden_s), + .data_oe (1'b1), .data_s0 (1'b1), .data_s1 (1'b0), .data_s2 (1'b1), diff --git a/library/axi_ad9739a/axi_ad9739a_if.v b/library/axi_ad9739a/axi_ad9739a_if.v index 821451c68..a4ca862f1 100644 --- a/library/axi_ad9739a/axi_ad9739a_if.v +++ b/library/axi_ad9739a/axi_ad9739a_if.v @@ -108,6 +108,7 @@ module axi_ad9739a_if #( .clk (dac_clk), .div_clk (dac_div_clk), .loaden (1'b0), + .data_oe (1'b1), .data_s0 (dac_data_00[15:2]), .data_s1 (dac_data_02[15:2]), .data_s2 (dac_data_04[15:2]), @@ -132,6 +133,7 @@ module axi_ad9739a_if #( .clk (dac_clk), .div_clk (dac_div_clk), .loaden (1'b0), + .data_oe (1'b1), .data_s0 (dac_data_01[15:2]), .data_s1 (dac_data_03[15:2]), .data_s2 (dac_data_05[15:2]), @@ -156,6 +158,7 @@ module axi_ad9739a_if #( .clk (dac_clk), .div_clk (dac_div_clk), .loaden (1'b0), + .data_oe (1'b1), .data_s0 (1'b1), .data_s1 (1'b0), .data_s2 (1'b1), diff --git a/library/xilinx/common/ad_serdes_out.v b/library/xilinx/common/ad_serdes_out.v index 85bb722e1..35c7a374b 100644 --- a/library/xilinx/common/ad_serdes_out.v +++ b/library/xilinx/common/ad_serdes_out.v @@ -51,7 +51,7 @@ module ad_serdes_out #( input loaden, // data interface - + input data_oe, input [(DATA_WIDTH-1):0] data_s0, // 1st bit to be transmitted input [(DATA_WIDTH-1):0] data_s1, input [(DATA_WIDTH-1):0] data_s2, @@ -80,9 +80,12 @@ module ad_serdes_out #( wire [(DATA_WIDTH-1):0] data_out_s; wire [(DATA_WIDTH-1):0] serdes_shift1_s; wire [(DATA_WIDTH-1):0] serdes_shift2_s; + wire [(DATA_WIDTH-1):0] data_t; + wire buffer_disable; assign data_out_se = data_out_s; + assign buffer_disable = ~data_oe; // instantiations genvar l_inst; @@ -105,10 +108,10 @@ module ad_serdes_out #( .D6 (data_s5[l_inst]), .D7 (data_s6[l_inst]), .D8 (data_s7[l_inst]), - .T1 (1'b0), - .T2 (1'b0), - .T3 (1'b0), - .T4 (1'b0), + .T1 (buffer_disable), + .T2 (buffer_disable), + .T3 (buffer_disable), + .T4 (buffer_disable), .SHIFTIN1 (1'b0), .SHIFTIN2 (1'b0), .SHIFTOUT1 (), @@ -117,13 +120,13 @@ module ad_serdes_out #( .CLK (clk), .CLKDIV (div_clk), .OQ (data_out_s[l_inst]), - .TQ (), + .TQ (data_t[l_inst]), .OFB (), .TFB (), .TBYTEIN (1'b0), .TBYTEOUT (), - .TCE (1'b0), - .RST (rst)); + .TCE (1'b1), + .RST (rst & data_oe)); end if (FPGA_TECHNOLOGY == ULTRASCALE || FPGA_TECHNOLOGY == ULTRASCALE_PLUS) begin @@ -139,15 +142,16 @@ module ad_serdes_out #( data_s2[l_inst], data_s1[l_inst], data_s0[l_inst]}), - .T (4'b0), + .T (buffer_disable), .CLK (clk), .CLKDIV (div_clk), .OQ (data_out_s[l_inst]), - .T_OUT (), - .RST (rst)); + .T_OUT (data_t[l_inst]), + .RST (rst & data_oe)); end - OBUFDS i_obuf ( + OBUFTDS i_obuf ( + .T (data_t[l_inst]), .I (data_out_s[l_inst]), .O (data_out_p[l_inst]), .OB (data_out_n[l_inst]));