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ad_serdes_out: Add tristate option

main
Laszlo Nagy 2019-07-19 10:15:06 +01:00 committed by Laszlo Nagy
parent c5c772127d
commit e6b9e21ad1
3 changed files with 22 additions and 12 deletions
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3
library/axi_ad9122/axi_ad9122_if.v
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@ -136,6 +136,7 @@ module axi_ad9122_if #(
.clk (dac_clk),
.div_clk (dac_div_clk),
.loaden (loaden_s),
.data_oe (1'b1),
.data_s0 (dac_data_i0),
.data_s1 (dac_data_q0),
.data_s2 (dac_data_i1),
@ -159,6 +160,7 @@ module axi_ad9122_if #(
.clk (dac_clk),
.div_clk (dac_div_clk),
.loaden (loaden_s),
.data_oe (1'b1),
.data_s0 (dac_frame_i0),
.data_s1 (dac_frame_q0),
.data_s2 (dac_frame_i1),
@ -182,6 +184,7 @@ module axi_ad9122_if #(
.clk (dac_clk),
.div_clk (dac_div_clk),
.loaden (loaden_s),
.data_oe (1'b1),
.data_s0 (1'b1),
.data_s1 (1'b0),
.data_s2 (1'b1),

3
library/axi_ad9739a/axi_ad9739a_if.v
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@ -108,6 +108,7 @@ module axi_ad9739a_if #(
.clk (dac_clk),
.div_clk (dac_div_clk),
.loaden (1'b0),
.data_oe (1'b1),
.data_s0 (dac_data_00[15:2]),
.data_s1 (dac_data_02[15:2]),
.data_s2 (dac_data_04[15:2]),
@ -132,6 +133,7 @@ module axi_ad9739a_if #(
.clk (dac_clk),
.div_clk (dac_div_clk),
.loaden (1'b0),
.data_oe (1'b1),
.data_s0 (dac_data_01[15:2]),
.data_s1 (dac_data_03[15:2]),
.data_s2 (dac_data_05[15:2]),
@ -156,6 +158,7 @@ module axi_ad9739a_if #(
.clk (dac_clk),
.div_clk (dac_div_clk),
.loaden (1'b0),
.data_oe (1'b1),
.data_s0 (1'b1),
.data_s1 (1'b0),
.data_s2 (1'b1),

28
library/xilinx/common/ad_serdes_out.v
View File

@ -51,7 +51,7 @@ module ad_serdes_out #(
input loaden,
// data interface
input data_oe,
input [(DATA_WIDTH-1):0] data_s0, // 1st bit to be transmitted
input [(DATA_WIDTH-1):0] data_s1,
input [(DATA_WIDTH-1):0] data_s2,
@ -80,9 +80,12 @@ module ad_serdes_out #(
wire [(DATA_WIDTH-1):0] data_out_s;
wire [(DATA_WIDTH-1):0] serdes_shift1_s;
wire [(DATA_WIDTH-1):0] serdes_shift2_s;
wire [(DATA_WIDTH-1):0] data_t;
wire buffer_disable;
assign data_out_se = data_out_s;
assign buffer_disable = ~data_oe;
// instantiations
genvar l_inst;
@ -105,10 +108,10 @@ module ad_serdes_out #(
.D6 (data_s5[l_inst]),
.D7 (data_s6[l_inst]),
.D8 (data_s7[l_inst]),
.T1 (1'b0),
.T2 (1'b0),
.T3 (1'b0),
.T4 (1'b0),
.T1 (buffer_disable),
.T2 (buffer_disable),
.T3 (buffer_disable),
.T4 (buffer_disable),
.SHIFTIN1 (1'b0),
.SHIFTIN2 (1'b0),
.SHIFTOUT1 (),
@ -117,13 +120,13 @@ module ad_serdes_out #(
.CLK (clk),
.CLKDIV (div_clk),
.OQ (data_out_s[l_inst]),
.TQ (),
.TQ (data_t[l_inst]),
.OFB (),
.TFB (),
.TBYTEIN (1'b0),
.TBYTEOUT (),
.TCE (1'b0),
.RST (rst));
.TCE (1'b1),
.RST (rst & data_oe));
end
if (FPGA_TECHNOLOGY == ULTRASCALE || FPGA_TECHNOLOGY == ULTRASCALE_PLUS) begin
@ -139,15 +142,16 @@ module ad_serdes_out #(
data_s2[l_inst],
data_s1[l_inst],
data_s0[l_inst]}),
.T (4'b0),
.T (buffer_disable),
.CLK (clk),
.CLKDIV (div_clk),
.OQ (data_out_s[l_inst]),
.T_OUT (),
.RST (rst));
.T_OUT (data_t[l_inst]),
.RST (rst & data_oe));
end
OBUFDS i_obuf (
OBUFTDS i_obuf (
.T (data_t[l_inst]),
.I (data_out_s[l_inst]),
.O (data_out_p[l_inst]),
.OB (data_out_n[l_inst]));