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axi_dmac: Better support debug IDs when ID_WIDTH != 3 

The current layout of the debug ID register assumes that the ID_WIDTH is 3.
Change things so that the padding 0 width depends on the ID_WIDTH
parameter so that we end up with the same register layout regardless of the
value of ID_WIDTH.

Also split things into two registers, this allows for an ID_WIDTH up to 8
(which should hopefully be enough for all practical applications).

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2017-08-24 13:14:03 +02:00
parent d05ed29212
commit e6aacd2f56
1 changed files with 22 additions and 11 deletions
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33
library/axi_dmac/axi_dmac.v
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@ -228,6 +228,7 @@ localparam ID_WIDTH = (FIFO_SIZE) > 64 ? 8 :
(FIFO_SIZE) > 4 ? 4 :
(FIFO_SIZE) > 2 ? 3 :
(FIFO_SIZE) > 1 ? 2 : 1;
localparam DBG_ID_PADDING = ID_WIDTH > 8 ? 0 : 8 - ID_WIDTH;
// Register interface signals
reg [31:0] up_rdata = 'd0;
@ -285,7 +286,8 @@ wire [ID_WIDTH-1:0] src_data_id;
wire [ID_WIDTH-1:0] src_address_id;
wire [ID_WIDTH-1:0] src_response_id;
wire [7:0] dbg_status;
wire [31:0] dbg_ids;
wire [31:0] dbg_ids0;
wire [31:0] dbg_ids1;
assign m_dest_axi_araddr = 'd0;
assign m_dest_axi_arlen = 'd0;
@ -409,10 +411,18 @@ begin
end
end
assign dbg_ids = {
src_response_id, 1'b0, src_data_id, 1'b0, src_address_id, 1'b0,
src_request_id, 1'b0, dest_response_id, 1'b0, dest_data_id, 1'b0,
dest_address_id, 1'b0, dest_request_id
assign dbg_ids0 = {
{DBG_ID_PADDING{1'b0}}, dest_data_id,
{DBG_ID_PADDING{1'b0}}, dest_response_id,
{DBG_ID_PADDING{1'b0}}, dest_address_id,
{DBG_ID_PADDING{1'b0}}, dest_request_id
};
assign dbg_ids1 = {
{DBG_ID_PADDING{1'b0}}, src_data_id,
{DBG_ID_PADDING{1'b0}}, src_response_id,
{DBG_ID_PADDING{1'b0}}, src_address_id,
{DBG_ID_PADDING{1'b0}}, src_request_id
};
always @(posedge s_axi_aclk)
@ -450,8 +460,9 @@ begin
9'h10c: up_rdata <= 'h00; // Status
9'h10d: up_rdata <= DISABLE_DEBUG_REGISTERS ? 32'h00 : m_dest_axi_awaddr; //HAS_DEST_ADDR ? 'h00 : 'h00; // Current dest address
9'h10e: up_rdata <= DISABLE_DEBUG_REGISTERS ? 32'h00 : m_src_axi_araddr; //HAS_SRC_ADDR ? 'h00 : 'h00; // Current src address
9'h10f: up_rdata <= DISABLE_DEBUG_REGISTERS ? 32'h00 : dbg_ids;
9'h110: up_rdata <= DISABLE_DEBUG_REGISTERS ? 32'h00 : dbg_status;
9'h10f: up_rdata <= DISABLE_DEBUG_REGISTERS ? 32'h00 : dbg_status;
9'h110: up_rdata <= DISABLE_DEBUG_REGISTERS ? 32'h00 : dbg_ids0;
9'h111: up_rdata <= DISABLE_DEBUG_REGISTERS ? 32'h00 : dbg_ids1;
default: up_rdata <= 'h00;
endcase
end
@ -645,12 +656,12 @@ dmac_request_arb #(
// DBG
.dbg_dest_request_id(dest_request_id),
.dbg_dest_address_id(dest_address_id),
.dbg_dest_data_id(dest_data_id),
.dbg_dest_address_id(dest_data_id),
.dbg_dest_data_id(dest_address_id),
.dbg_dest_response_id(dest_response_id),
.dbg_src_request_id(src_request_id),
.dbg_src_address_id(src_address_id),
.dbg_src_data_id(src_data_id),
.dbg_src_address_id(src_data_id),
.dbg_src_data_id(src_address_id),
.dbg_src_response_id(src_response_id),
.dbg_status(dbg_status)
);