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axi_dmac: Fix a bug occuring on transfers < one beat 

Signed-off-by: Paul Cercueil <paul.cercueil@analog.com>
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Paul Cercueil 2015-08-18 14:13:55 +02:00
parent e221c3b48c
commit e64baad54a
1 changed files with 2 additions and 1 deletions
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3
library/axi_dmac/address_generator.v
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@ -103,7 +103,7 @@ end
always @(posedge clk) begin always @(posedge clk) begin
if (addr_valid == 1'b0) begin if (addr_valid == 1'b0) begin
if (eot == 1'b1) if (eot == 1'b1)
length <= req_last_burst_length; length <= last_burst_len;
else else
length <= MAX_BEATS_PER_BURST - 1; length <= MAX_BEATS_PER_BURST - 1;
end end
@ -130,6 +130,7 @@ always @(posedge clk) begin
if (req_valid && enable) begin if (req_valid && enable) begin
address <= req_address; address <= req_address;
req_ready <= 1'b0; req_ready <= 1'b0;
last_burst_len <= req_last_burst_length;
end end
end else begin end else begin
if (addr_valid && addr_ready) begin if (addr_valid && addr_ready) begin