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fmcomms8: ZCU102: Added DAC FIFO

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Adrian Costina 2019-11-04 15:57:11 +00:00
parent 016a1d540d
commit e51d9372cd
5 changed files with 37 additions and 9 deletions
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31
projects/fmcomms8/common/fmcomms8_bd.tcl
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@ -5,6 +5,8 @@ create_bd_port -dir I ref_clk_d
create_bd_port -dir I core_clk_c
create_bd_port -dir I core_clk_d
create_bd_port -dir I dac_fifo_bypass
# TX parameters
set TX_NUM_OF_LANES 8 ; # L
set TX_NUM_OF_CONVERTERS 8 ; # M
@ -31,6 +33,12 @@ set OBS_SAMPLES_PER_CHANNEL 2 ; # L * 32 / (M * N)
source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl
set dac_fifo_name axi_adrv9009_fmc_tx_fifo
set dac_data_width 256
set dac_dma_data_width 256
ad_dacfifo_create $dac_fifo_name $dac_data_width $dac_dma_data_width $dac_fifo_address_width
ad_ip_instance axi_adxcvr axi_adrv9009_fmc_tx_xcvr
ad_ip_parameter axi_adrv9009_fmc_tx_xcvr CONFIG.NUM_OF_LANES $TX_NUM_OF_LANES
ad_ip_parameter axi_adrv9009_fmc_tx_xcvr CONFIG.QPLL_ENABLE 1
@ -57,7 +65,7 @@ ad_ip_parameter axi_adrv9009_fmc_tx_dma CONFIG.CYCLIC 1
ad_ip_parameter axi_adrv9009_fmc_tx_dma CONFIG.AXI_SLICE_SRC 1
ad_ip_parameter axi_adrv9009_fmc_tx_dma CONFIG.AXI_SLICE_DEST 1
ad_ip_parameter axi_adrv9009_fmc_tx_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter axi_adrv9009_fmc_tx_dma CONFIG.DMA_DATA_WIDTH_DEST 128
ad_ip_parameter axi_adrv9009_fmc_tx_dma CONFIG.DMA_DATA_WIDTH_DEST 256
ad_ip_parameter axi_adrv9009_fmc_tx_dma CONFIG.DMA_DATA_WIDTH_SRC 128
ad_ip_parameter axi_adrv9009_fmc_tx_dma CONFIG.FIFO_SIZE 32
ad_ip_parameter axi_adrv9009_fmc_tx_dma CONFIG.MAX_BYTES_PER_BURST 512
@ -172,6 +180,24 @@ for {set i 0} {$i < $TX_NUM_OF_CONVERTERS} {incr i} {
ad_connect tx_adrv9009_fmc_tpl_core/dac_dunf util_fmc_tx_upack/fifo_rd_underflow
ad_connect core_clk_c axi_adrv9009_fmc_tx_fifo/dac_clk
ad_connect core_clk_c_rstgen/peripheral_reset axi_adrv9009_fmc_tx_fifo/dac_rst
ad_connect util_fmc_tx_upack/s_axis_valid VCC
ad_connect util_fmc_tx_upack/s_axis_ready axi_adrv9009_fmc_tx_fifo/dac_valid
ad_connect util_fmc_tx_upack/s_axis_data axi_adrv9009_fmc_tx_fifo/dac_data
ad_connect core_clk_c axi_adrv9009_fmc_tx_fifo/dma_clk
ad_connect core_clk_c_rstgen/peripheral_reset axi_adrv9009_fmc_tx_fifo/dma_rst
ad_connect core_clk_c axi_adrv9009_fmc_tx_dma/m_axis_aclk
ad_connect axi_adrv9009_fmc_tx_fifo/dma_xfer_req axi_adrv9009_fmc_tx_dma/m_axis_xfer_req
ad_connect axi_adrv9009_fmc_tx_fifo/dma_ready axi_adrv9009_fmc_tx_dma/m_axis_ready
ad_connect axi_adrv9009_fmc_tx_fifo/dma_data axi_adrv9009_fmc_tx_dma/m_axis_data
ad_connect axi_adrv9009_fmc_tx_fifo/dma_valid axi_adrv9009_fmc_tx_dma/m_axis_valid
ad_connect axi_adrv9009_fmc_tx_fifo/dma_xfer_last axi_adrv9009_fmc_tx_dma/m_axis_last
ad_connect axi_adrv9009_fmc_tx_fifo/bypass dac_fifo_bypass
ad_connect core_clk_d rx_adrv9009_fmc_tpl_core/link_clk
ad_connect axi_adrv9009_fmc_rx_jesd/rx_sof rx_adrv9009_fmc_tpl_core/link_sof
ad_connect axi_adrv9009_fmc_rx_jesd/rx_data_tdata rx_adrv9009_fmc_tpl_core/link_data
@ -206,9 +232,6 @@ for {set i 0} {$i < $OBS_NUM_OF_CONVERTERS} {incr i} {
ad_connect obs_adrv9009_fmc_tpl_core/adc_dovf util_fmc_obs_cpack/fifo_wr_overflow
ad_connect util_fmc_obs_cpack/packed_fifo_wr axi_adrv9009_fmc_obs_dma/fifo_wr
ad_connect core_clk_c axi_adrv9009_fmc_tx_dma/m_axis_aclk
ad_connect util_fmc_tx_upack/s_axis_valid VCC_1/dout
ad_cpu_interconnect 0x45A00000 rx_adrv9009_fmc_tpl_core
ad_cpu_interconnect 0x45A04000 tx_adrv9009_fmc_tpl_core

1
projects/fmcomms8/zcu102/Makefile
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@ -25,6 +25,7 @@ LIB_DEPS += jesd204/jesd204_tx
LIB_DEPS += util_pack/util_cpack2
LIB_DEPS += util_pack/util_upack2
LIB_DEPS += sysid_rom
LIB_DEPS += util_dacfifo
LIB_DEPS += xilinx/axi_adcfifo
LIB_DEPS += xilinx/axi_dacfifo
LIB_DEPS += xilinx/axi_adxcvr

4
projects/fmcomms8/zcu102/system_bd.tcl
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@ -2,6 +2,9 @@
source $ad_hdl_dir/projects/common/zcu102/zcu102_system_bd.tcl
source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl
## FIFO depth is 8Mb - 500k samples
set dac_fifo_address_width 16
#system ID
ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt"
@ -10,3 +13,4 @@ set sys_cstring "sys rom custom string placeholder"
sysid_gen_sys_init_file $sys_cstring
source ../common/fmcomms8_bd.tcl
ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ 300

8
projects/fmcomms8/zcu102/system_constr.xdc
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@ -10,10 +10,10 @@ set_property PACKAGE_PIN F2 [get_ports {rx_data_c_p[2]}]; # A06 FMC_HPC0_DP2_M2C
set_property PACKAGE_PIN F1 [get_ports {rx_data_c_n[2]}]; # A07 FMC_HPC0_DP2_M2C_N
set_property PACKAGE_PIN K2 [get_ports {rx_data_c_p[3]}]; # A10 FMC_HPC0_DP3_M2C_P
set_property PACKAGE_PIN K1 [get_ports {rx_data_c_n[3]}]; # A11 FMC_HPC0_DP3_M2C_N
set_property PACKAGE_PIN H6 [get_ports {tx_data_c_p[0]}]; # A22 FMC_HPC0_DP1_C2M_P
set_property PACKAGE_PIN H5 [get_ports {tx_data_c_n[0]}]; # A23 FMC_HPC0_DP1_C2M_N
set_property PACKAGE_PIN G4 [get_ports {tx_data_c_p[1]}]; # C02 FMC_HPC0_DP0_C2M_P
set_property PACKAGE_PIN G3 [get_ports {tx_data_c_n[1]}]; # C03 FMC_HPC0_DP0_C2M_N
set_property PACKAGE_PIN G4 [get_ports {tx_data_c_p[0]}]; # C02 FMC_HPC0_DP0_C2M_P
set_property PACKAGE_PIN G3 [get_ports {tx_data_c_n[0]}]; # C03 FMC_HPC0_DP0_C2M_N
set_property PACKAGE_PIN H6 [get_ports {tx_data_c_p[1]}]; # A22 FMC_HPC0_DP1_C2M_P
set_property PACKAGE_PIN H5 [get_ports {tx_data_c_n[1]}]; # A23 FMC_HPC0_DP1_C2M_N
set_property PACKAGE_PIN F6 [get_ports {tx_data_c_p[2]}]; # A26 FMC_HPC0_DP2_C2M_P
set_property PACKAGE_PIN F5 [get_ports {tx_data_c_n[2]}]; # A27 FMC_HPC0_DP2_C2M_N
set_property PACKAGE_PIN K6 [get_ports {tx_data_c_p[3]}]; # A30 FMC_HPC0_DP3_C2M_P

2
projects/fmcomms8/zcu102/system_top.v
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@ -345,7 +345,7 @@ module system_top (
.tx_data_7_p (tx_data_d_p[3]),
.tx_sync_0 (tx_sync),
.tx_sysref_0 (sysref_c),
//.dac_fifo_bypass(gpio_o[90]),
.dac_fifo_bypass(gpio_o[68]),
.spi0_sclk (spi_clk),
.spi0_csn (spi_csn),