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fmcadc5: Integrate ad_sysref_gen into the project

main
Istvan Csomortani 2017-01-03 13:52:39 +02:00
parent 14ded4f123
commit e4e5b30ade
4 changed files with 10 additions and 9 deletions
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1
projects/fmcadc5/vc707/Makefile
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@ -21,6 +21,7 @@ M_DEPS += ../../common/vc707/vc707_system_constr.xdc
M_DEPS += ../../common/vc707/vc707_system_bd.tcl
M_DEPS += ../../../library/xilinx/common/ad_lvds_out.v
M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
M_DEPS += ../../../library/common/ad_sysref_gen.v
M_DEPS += ../../../library/axi_ad9625/axi_ad9625.xpr
M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr
M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr

4
projects/fmcadc5/vc707/system_constr.xdc
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@ -87,5 +87,7 @@ create_clock -name rx_ref_clk_1 -period 1.60 [get_ports rx_ref_clk_1_p]
create_clock -name rx_div_clk -period 6.40 [get_pins i_system_wrapper/system_i/util_fmcadc5_0_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]
set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9625_0_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]*]
set_false_path -to [get_cells rx_sysref_m1_reg]
set_property shreg_extract no [get_cells -hier -filter {name =~ *sysref_en_m*}]
set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m1* && IS_SEQUENTIAL}]

1
projects/fmcadc5/vc707/system_project.tcl
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@ -10,6 +10,7 @@ adi_project_files fmcadc5_vc707 [list \
"$ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc" \
"$ad_hdl_dir/library/xilinx/common/ad_lvds_out.v" \
"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
"$ad_hdl_dir/library/common/ad_sysref_gen.v" \
"../common/fmcadc5_spi.v" \
"../common/fmcadc5_psync.v" \
"system_constr.xdc"\

13
projects/fmcadc5/vc707/system_top.v
View File

@ -138,9 +138,6 @@ module system_top (
reg [ 4:0] gpio_o_60_56_d = 'd0;
reg gpio_dld = 'd0;
reg rx_sysref_m1 = 'd0;
reg rx_sysref_m2 = 'd0;
reg rx_sysref_int = 'd0;
// internal signals
@ -160,6 +157,7 @@ module system_top (
wire rx_sync_1;
wire up_rstn;
wire up_clk;
wire rx_sysref_int;
// spi
@ -194,11 +192,10 @@ module system_top (
// sysref internal
always @(posedge rx_clk) begin
rx_sysref_m1 <= gpio_o[32];
rx_sysref_m2 <= rx_sysref_m1;
rx_sysref_int <= rx_sysref_m1 & ~rx_sysref_m2;
end
ad_sysref_gen i_sysref (
.core_clk (rx_clk),
.sysref_en (gpio_o[32]),
.sysref_out (rx_sysref_int));
// instantiations