Renamed ad9379 to adrv9009
Adrian Costina
parent
96c5cc9a66
commit
e4d579726d
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@ -35,7 +35,7 @@ clean:
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$(MAKE) -C axi_ad9265 clean
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$(MAKE) -C axi_ad9361 clean
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$(MAKE) -C axi_ad9371 clean
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$(MAKE) -C axi_ad9379 clean
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$(MAKE) -C axi_adrv9009 clean
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$(MAKE) -C axi_ad9434 clean
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$(MAKE) -C axi_ad9467 clean
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$(MAKE) -C axi_ad9625 clean
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@ -141,7 +141,7 @@ lib:
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$(MAKE) -C axi_ad9265
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$(MAKE) -C axi_ad9361
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$(MAKE) -C axi_ad9371
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$(MAKE) -C axi_ad9379
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$(MAKE) -C axi_adrv9009
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$(MAKE) -C axi_ad9434
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$(MAKE) -C axi_ad9467
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$(MAKE) -C axi_ad9625
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@ -3,7 +3,7 @@
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## Auto-generated, do not modify!
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####################################################################################
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LIBRARY_NAME := axi_ad9379
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LIBRARY_NAME := axi_adrv9009
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GENERIC_DEPS += ../common/ad_datafmt.v
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GENERIC_DEPS += ../common/ad_dds.v
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@ -20,13 +20,13 @@ GENERIC_DEPS += ../common/up_dac_channel.v
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GENERIC_DEPS += ../common/up_dac_common.v
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GENERIC_DEPS += ../common/up_xfer_cntrl.v
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GENERIC_DEPS += ../common/up_xfer_status.v
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GENERIC_DEPS += axi_ad9379.v
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GENERIC_DEPS += axi_ad9379_if.v
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GENERIC_DEPS += axi_ad9379_rx.v
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GENERIC_DEPS += axi_ad9379_rx_channel.v
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GENERIC_DEPS += axi_ad9379_rx_os.v
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GENERIC_DEPS += axi_ad9379_tx.v
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GENERIC_DEPS += axi_ad9379_tx_channel.v
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GENERIC_DEPS += axi_adrv9009.v
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GENERIC_DEPS += axi_adrv9009_if.v
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GENERIC_DEPS += axi_adrv9009_rx.v
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GENERIC_DEPS += axi_adrv9009_rx_channel.v
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GENERIC_DEPS += axi_adrv9009_rx_os.v
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GENERIC_DEPS += axi_adrv9009_tx.v
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GENERIC_DEPS += axi_adrv9009_tx_channel.v
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XILINX_DEPS += ../xilinx/common/ad_dcfilter.v
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XILINX_DEPS += ../xilinx/common/ad_mul.v
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@ -34,7 +34,7 @@ XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc
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XILINX_DEPS += ../xilinx/common/up_clock_mon_constr.xdc
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XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
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XILINX_DEPS += ../xilinx/common/up_xfer_status_constr.xdc
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XILINX_DEPS += axi_ad9379_ip.tcl
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XILINX_DEPS += axi_adrv9009_ip.tcl
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ALTERA_DEPS += ../altera/common/ad_dcfilter.v
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ALTERA_DEPS += ../altera/common/ad_mul.v
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@ -42,6 +42,6 @@ ALTERA_DEPS += ../altera/common/up_clock_mon_constr.sdc
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ALTERA_DEPS += ../altera/common/up_rst_constr.sdc
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ALTERA_DEPS += ../altera/common/up_xfer_cntrl_constr.sdc
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ALTERA_DEPS += ../altera/common/up_xfer_status_constr.sdc
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ALTERA_DEPS += axi_ad9379_hw.tcl
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ALTERA_DEPS += axi_adrv9009_hw.tcl
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include ../scripts/library.mk
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@ -35,7 +35,7 @@
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`timescale 1ns/100ps
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module axi_ad9379 #(
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module axi_adrv9009 #(
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parameter ID = 0,
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parameter DAC_DATAPATH_DISABLE = 0,
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@ -185,7 +185,7 @@ module axi_ad9379 #(
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// device interface
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axi_ad9379_if i_if (
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axi_adrv9009_if i_if (
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.adc_clk (adc_clk),
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.adc_rx_sof (adc_rx_sof),
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.adc_rx_data (adc_rx_data),
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@ -201,7 +201,7 @@ module axi_ad9379 #(
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// receive
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axi_ad9379_rx #(
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axi_adrv9009_rx #(
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.ID (ID),
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.DATAPATH_DISABLE (ADC_DATAPATH_DISABLE))
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i_rx (
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@ -235,7 +235,7 @@ module axi_ad9379 #(
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// receive (o/s)
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axi_ad9379_rx_os #(
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axi_adrv9009_rx_os #(
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.ID (ID),
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.DATAPATH_DISABLE (ADC_DATAPATH_DISABLE))
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i_rx_os (
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@ -264,7 +264,7 @@ module axi_ad9379 #(
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// transmit
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axi_ad9379_tx #(
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axi_adrv9009_tx #(
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.ID (ID),
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.DATAPATH_DISABLE (DAC_DATAPATH_DISABLE))
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i_tx (
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@ -4,16 +4,16 @@ package require qsys
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source ../scripts/adi_env.tcl
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source ../scripts/adi_ip_alt.tcl
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set_module_property NAME axi_ad9379
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set_module_property DESCRIPTION "AXI AD9379 Interface"
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set_module_property NAME axi_adrv9009
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set_module_property DESCRIPTION "AXI adrv9009 Interface"
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set_module_property VERSION 1.0
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set_module_property GROUP "Analog Devices"
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set_module_property DISPLAY_NAME axi_ad9379
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set_module_property DISPLAY_NAME axi_adrv9009
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# files
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add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
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set_fileset_property quartus_synth TOP_LEVEL axi_ad9379
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set_fileset_property quartus_synth TOP_LEVEL axi_adrv9009
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add_fileset_file ad_rst.v VERILOG PATH $ad_hdl_dir/library/common/ad_rst.v
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add_fileset_file ad_mul.v VERILOG PATH $ad_hdl_dir/library/altera/common/ad_mul.v
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add_fileset_file ad_dds_sine.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds_sine.v
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@ -31,13 +31,13 @@ add_fileset_file up_adc_channel.v VERILOG PATH $ad_hdl_dir/library/com
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add_fileset_file up_dac_common.v VERILOG PATH $ad_hdl_dir/library/common/up_dac_common.v
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add_fileset_file up_dac_channel.v VERILOG PATH $ad_hdl_dir/library/common/up_dac_channel.v
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add_fileset_file ad_xcvr_rx_if.v VERILOG PATH $ad_hdl_dir/library/common/ad_xcvr_rx_if.v
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add_fileset_file axi_ad9379_if.v VERILOG PATH axi_ad9379_if.v
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add_fileset_file axi_ad9379_rx_channel.v VERILOG PATH axi_ad9379_rx_channel.v
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add_fileset_file axi_ad9379_rx.v VERILOG PATH axi_ad9379_rx.v
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add_fileset_file axi_ad9379_rx_os.v VERILOG PATH axi_ad9379_rx_os.v
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add_fileset_file axi_ad9379_tx_channel.v VERILOG PATH axi_ad9379_tx_channel.v
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add_fileset_file axi_ad9379_tx.v VERILOG PATH axi_ad9379_tx.v
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add_fileset_file axi_ad9379.v VERILOG PATH axi_ad9379.v TOP_LEVEL_FILE
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add_fileset_file axi_adrv9009_if.v VERILOG PATH axi_adrv9009_if.v
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add_fileset_file axi_adrv9009_rx_channel.v VERILOG PATH axi_adrv9009_rx_channel.v
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add_fileset_file axi_adrv9009_rx.v VERILOG PATH axi_adrv9009_rx.v
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add_fileset_file axi_adrv9009_rx_os.v VERILOG PATH axi_adrv9009_rx_os.v
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add_fileset_file axi_adrv9009_tx_channel.v VERILOG PATH axi_adrv9009_tx_channel.v
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add_fileset_file axi_adrv9009_tx.v VERILOG PATH axi_adrv9009_tx.v
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add_fileset_file axi_adrv9009.v VERILOG PATH axi_adrv9009.v TOP_LEVEL_FILE
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add_fileset_file up_xfer_cntrl_constr.sdc SDC PATH $ad_hdl_dir/library/altera/common/up_xfer_cntrl_constr.sdc
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add_fileset_file up_xfer_status_constr.sdc SDC PATH $ad_hdl_dir/library/altera/common/up_xfer_status_constr.sdc
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add_fileset_file up_clock_mon_constr.sdc SDC PATH $ad_hdl_dir/library/altera/common/up_clock_mon_constr.sdc
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@ -35,7 +35,7 @@
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`timescale 1ns/100ps
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module axi_ad9379_if (
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module axi_adrv9009_if (
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// receive
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input adc_clk,
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@ -3,8 +3,8 @@
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source ../scripts/adi_env.tcl
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source $ad_hdl_dir/library/scripts/adi_ip.tcl
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adi_ip_create axi_ad9379
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adi_ip_files axi_ad9379 [list \
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adi_ip_create axi_adrv9009
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adi_ip_files axi_adrv9009 [list \
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"$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \
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"$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \
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"$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \
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@ -26,15 +26,15 @@ adi_ip_files axi_ad9379 [list \
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"$ad_hdl_dir/library/common/up_dac_common.v" \
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"$ad_hdl_dir/library/common/up_dac_channel.v" \
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"$ad_hdl_dir/library/common/ad_xcvr_rx_if.v" \
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"axi_ad9379_if.v" \
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"axi_ad9379_rx_channel.v" \
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"axi_ad9379_rx.v" \
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"axi_ad9379_rx_os.v" \
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"axi_ad9379_tx_channel.v" \
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"axi_ad9379_tx.v" \
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"axi_ad9379.v" ]
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"axi_adrv9009_if.v" \
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"axi_adrv9009_rx_channel.v" \
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"axi_adrv9009_rx.v" \
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"axi_adrv9009_rx_os.v" \
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"axi_adrv9009_tx_channel.v" \
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"axi_adrv9009_tx.v" \
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"axi_adrv9009.v" ]
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adi_ip_properties axi_ad9379
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adi_ip_properties axi_adrv9009
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set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
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set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]
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@ -35,7 +35,7 @@
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`timescale 1ns/100ps
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module axi_ad9379_rx #(
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module axi_adrv9009_rx #(
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parameter DATAPATH_DISABLE = 0,
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parameter ID = 0) (
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@ -125,7 +125,7 @@ module axi_ad9379_rx #(
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// channel 0 (i)
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axi_ad9379_rx_channel #(
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axi_adrv9009_rx_channel #(
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.Q_OR_I_N (0),
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.COMMON_ID ('h01),
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.CHANNEL_ID (0),
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@ -157,7 +157,7 @@ module axi_ad9379_rx #(
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// channel 1 (q)
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axi_ad9379_rx_channel #(
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axi_adrv9009_rx_channel #(
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.Q_OR_I_N (1),
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.COMMON_ID ('h01),
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.CHANNEL_ID (1),
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@ -189,7 +189,7 @@ module axi_ad9379_rx #(
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// channel 2 (i)
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axi_ad9379_rx_channel #(
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axi_adrv9009_rx_channel #(
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.Q_OR_I_N (0),
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.COMMON_ID ('h01),
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.CHANNEL_ID (2),
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@ -221,7 +221,7 @@ module axi_ad9379_rx #(
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// channel 3 (q)
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axi_ad9379_rx_channel #(
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axi_adrv9009_rx_channel #(
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.Q_OR_I_N (1),
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.COMMON_ID ('h01),
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.CHANNEL_ID (3),
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@ -35,7 +35,7 @@
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`timescale 1ns/100ps
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module axi_ad9379_rx_channel #(
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module axi_adrv9009_rx_channel #(
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parameter Q_OR_I_N = 0,
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parameter COMMON_ID = 0,
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@ -35,7 +35,7 @@
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`timescale 1ns/100ps
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module axi_ad9379_rx_os #(
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module axi_adrv9009_rx_os #(
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parameter DATAPATH_DISABLE = 0,
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parameter ID = 0) (
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@ -111,7 +111,7 @@ module axi_ad9379_rx_os #(
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// channel o/s (i)
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axi_ad9379_rx_channel #(
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axi_adrv9009_rx_channel #(
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.Q_OR_I_N (0),
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.COMMON_ID ('h21),
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.CHANNEL_ID (0),
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@ -143,7 +143,7 @@ module axi_ad9379_rx_os #(
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// channel o/s (q)
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axi_ad9379_rx_channel #(
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axi_adrv9009_rx_channel #(
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.Q_OR_I_N (1),
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.COMMON_ID ('h21),
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.CHANNEL_ID (1),
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@ -35,7 +35,7 @@
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`timescale 1ns/100ps
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module axi_ad9379_tx #(
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module axi_adrv9009_tx #(
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parameter DATAPATH_DISABLE = 0,
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parameter ID = 0) (
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@ -127,7 +127,7 @@ module axi_ad9379_tx #(
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assign dac_valid_i0 = 1'b1;
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axi_ad9379_tx_channel #(
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axi_adrv9009_tx_channel #(
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.CHANNEL_ID (0),
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.Q_OR_I_N (0),
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.DATAPATH_DISABLE (DATAPATH_DISABLE))
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@ -156,7 +156,7 @@ module axi_ad9379_tx #(
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assign dac_valid_q0 = 1'b1;
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axi_ad9379_tx_channel #(
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axi_adrv9009_tx_channel #(
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.CHANNEL_ID (1),
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.Q_OR_I_N (1),
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.DATAPATH_DISABLE (DATAPATH_DISABLE))
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@ -185,7 +185,7 @@ module axi_ad9379_tx #(
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assign dac_valid_i1 = 1'b1;
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axi_ad9379_tx_channel #(
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axi_adrv9009_tx_channel #(
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.CHANNEL_ID (2),
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.Q_OR_I_N (0),
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.DATAPATH_DISABLE (DATAPATH_DISABLE))
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@ -214,7 +214,7 @@ module axi_ad9379_tx #(
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assign dac_valid_q1 = 1'b1;
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axi_ad9379_tx_channel #(
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axi_adrv9009_tx_channel #(
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.CHANNEL_ID (3),
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.Q_OR_I_N (1),
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.DATAPATH_DISABLE (DATAPATH_DISABLE))
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@ -35,7 +35,7 @@
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`timescale 1ns/100ps
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module axi_ad9379_tx_channel #(
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module axi_adrv9009_tx_channel #(
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parameter CHANNEL_ID = 32'h0,
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parameter Q_OR_I_N = 0,
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@ -0,0 +1,286 @@
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source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl
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# adrv9009
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create_bd_port -dir I dac_fifo_bypass
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# dac peripherals
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ad_ip_instance axi_clkgen axi_adrv9009_tx_clkgen
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ad_ip_parameter axi_adrv9009_tx_clkgen CONFIG.ID 2
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ad_ip_parameter axi_adrv9009_tx_clkgen CONFIG.CLKIN_PERIOD 4
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ad_ip_parameter axi_adrv9009_tx_clkgen CONFIG.VCO_DIV 1
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ad_ip_parameter axi_adrv9009_tx_clkgen CONFIG.VCO_MUL 4
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ad_ip_parameter axi_adrv9009_tx_clkgen CONFIG.CLK0_DIV 4
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ad_ip_instance axi_adxcvr axi_adrv9009_tx_xcvr
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ad_ip_parameter axi_adrv9009_tx_xcvr CONFIG.NUM_OF_LANES 4
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ad_ip_parameter axi_adrv9009_tx_xcvr CONFIG.QPLL_ENABLE 1
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ad_ip_parameter axi_adrv9009_tx_xcvr CONFIG.TX_OR_RX_N 1
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adi_axi_jesd204_tx_create axi_adrv9009_tx_jesd 4
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ad_ip_instance util_upack util_adrv9009_tx_upack
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ad_ip_parameter util_adrv9009_tx_upack CONFIG.CHANNEL_DATA_WIDTH 32
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ad_ip_parameter util_adrv9009_tx_upack CONFIG.NUM_OF_CHANNELS 4
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ad_ip_instance axi_dmac axi_adrv9009_tx_dma
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ad_ip_parameter axi_adrv9009_tx_dma CONFIG.DMA_TYPE_SRC 0
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ad_ip_parameter axi_adrv9009_tx_dma CONFIG.DMA_TYPE_DEST 1
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ad_ip_parameter axi_adrv9009_tx_dma CONFIG.CYCLIC 1
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ad_ip_parameter axi_adrv9009_tx_dma CONFIG.AXI_SLICE_SRC 0
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ad_ip_parameter axi_adrv9009_tx_dma CONFIG.AXI_SLICE_DEST 1
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ad_ip_parameter axi_adrv9009_tx_dma CONFIG.ASYNC_CLK_DEST_REQ 1
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ad_ip_parameter axi_adrv9009_tx_dma CONFIG.ASYNC_CLK_SRC_DEST 1
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ad_ip_parameter axi_adrv9009_tx_dma CONFIG.ASYNC_CLK_REQ_SRC 1
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ad_ip_parameter axi_adrv9009_tx_dma CONFIG.DMA_2D_TRANSFER 0
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ad_ip_parameter axi_adrv9009_tx_dma CONFIG.DMA_DATA_WIDTH_DEST 128
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|
||||
# adc peripherals
|
||||
|
||||
ad_ip_instance axi_clkgen axi_adrv9009_rx_clkgen
|
||||
ad_ip_parameter axi_adrv9009_rx_clkgen CONFIG.ID 2
|
||||
ad_ip_parameter axi_adrv9009_rx_clkgen CONFIG.CLKIN_PERIOD 4
|
||||
ad_ip_parameter axi_adrv9009_rx_clkgen CONFIG.VCO_DIV 1
|
||||
ad_ip_parameter axi_adrv9009_rx_clkgen CONFIG.VCO_MUL 4
|
||||
ad_ip_parameter axi_adrv9009_rx_clkgen CONFIG.CLK0_DIV 4
|
||||
|
||||
ad_ip_instance axi_adxcvr axi_adrv9009_rx_xcvr
|
||||
ad_ip_parameter axi_adrv9009_rx_xcvr CONFIG.NUM_OF_LANES 2
|
||||
ad_ip_parameter axi_adrv9009_rx_xcvr CONFIG.QPLL_ENABLE 0
|
||||
ad_ip_parameter axi_adrv9009_rx_xcvr CONFIG.TX_OR_RX_N 0
|
||||
|
||||
adi_axi_jesd204_rx_create axi_adrv9009_rx_jesd 2
|
||||
|
||||
ad_ip_instance util_cpack util_adrv9009_rx_cpack
|
||||
ad_ip_parameter util_adrv9009_rx_cpack CONFIG.CHANNEL_DATA_WIDTH 16
|
||||
ad_ip_parameter util_adrv9009_rx_cpack CONFIG.NUM_OF_CHANNELS 4
|
||||
|
||||
ad_ip_instance axi_dmac axi_adrv9009_rx_dma
|
||||
ad_ip_parameter axi_adrv9009_rx_dma CONFIG.DMA_TYPE_SRC 2
|
||||
ad_ip_parameter axi_adrv9009_rx_dma CONFIG.DMA_TYPE_DEST 0
|
||||
ad_ip_parameter axi_adrv9009_rx_dma CONFIG.CYCLIC 0
|
||||
ad_ip_parameter axi_adrv9009_rx_dma CONFIG.SYNC_TRANSFER_START 1
|
||||
ad_ip_parameter axi_adrv9009_rx_dma CONFIG.AXI_SLICE_SRC 0
|
||||
ad_ip_parameter axi_adrv9009_rx_dma CONFIG.AXI_SLICE_DEST 0
|
||||
ad_ip_parameter axi_adrv9009_rx_dma CONFIG.ASYNC_CLK_DEST_REQ 1
|
||||
ad_ip_parameter axi_adrv9009_rx_dma CONFIG.ASYNC_CLK_SRC_DEST 1
|
||||
ad_ip_parameter axi_adrv9009_rx_dma CONFIG.ASYNC_CLK_REQ_SRC 1
|
||||
ad_ip_parameter axi_adrv9009_rx_dma CONFIG.DMA_2D_TRANSFER 0
|
||||
ad_ip_parameter axi_adrv9009_rx_dma CONFIG.DMA_DATA_WIDTH_SRC 64
|
||||
|
||||
# adc-os peripherals
|
||||
|
||||
ad_ip_instance axi_clkgen axi_adrv9009_rx_os_clkgen
|
||||
ad_ip_parameter axi_adrv9009_rx_os_clkgen CONFIG.ID 2
|
||||
ad_ip_parameter axi_adrv9009_rx_os_clkgen CONFIG.CLKIN_PERIOD 4
|
||||
ad_ip_parameter axi_adrv9009_rx_os_clkgen CONFIG.VCO_DIV 1
|
||||
ad_ip_parameter axi_adrv9009_rx_os_clkgen CONFIG.VCO_MUL 4
|
||||
ad_ip_parameter axi_adrv9009_rx_os_clkgen CONFIG.CLK0_DIV 4
|
||||
|
||||
ad_ip_instance axi_adxcvr axi_adrv9009_rx_os_xcvr
|
||||
ad_ip_parameter axi_adrv9009_rx_os_xcvr CONFIG.NUM_OF_LANES 2
|
||||
ad_ip_parameter axi_adrv9009_rx_os_xcvr CONFIG.QPLL_ENABLE 0
|
||||
ad_ip_parameter axi_adrv9009_rx_os_xcvr CONFIG.TX_OR_RX_N 0
|
||||
|
||||
adi_axi_jesd204_rx_create axi_adrv9009_rx_os_jesd 2
|
||||
|
||||
ad_ip_instance util_cpack util_adrv9009_rx_os_cpack
|
||||
ad_ip_parameter util_adrv9009_rx_os_cpack CONFIG.CHANNEL_DATA_WIDTH 32
|
||||
ad_ip_parameter util_adrv9009_rx_os_cpack CONFIG.NUM_OF_CHANNELS 2
|
||||
|
||||
ad_ip_instance axi_dmac axi_adrv9009_rx_os_dma
|
||||
ad_ip_parameter axi_adrv9009_rx_os_dma CONFIG.DMA_TYPE_SRC 2
|
||||
ad_ip_parameter axi_adrv9009_rx_os_dma CONFIG.DMA_TYPE_DEST 0
|
||||
ad_ip_parameter axi_adrv9009_rx_os_dma CONFIG.CYCLIC 0
|
||||
ad_ip_parameter axi_adrv9009_rx_os_dma CONFIG.SYNC_TRANSFER_START 1
|
||||
ad_ip_parameter axi_adrv9009_rx_os_dma CONFIG.AXI_SLICE_SRC 0
|
||||
ad_ip_parameter axi_adrv9009_rx_os_dma CONFIG.AXI_SLICE_DEST 0
|
||||
ad_ip_parameter axi_adrv9009_rx_os_dma CONFIG.ASYNC_CLK_DEST_REQ 1
|
||||
ad_ip_parameter axi_adrv9009_rx_os_dma CONFIG.ASYNC_CLK_SRC_DEST 1
|
||||
ad_ip_parameter axi_adrv9009_rx_os_dma CONFIG.ASYNC_CLK_REQ_SRC 1
|
||||
ad_ip_parameter axi_adrv9009_rx_os_dma CONFIG.DMA_2D_TRANSFER 0
|
||||
ad_ip_parameter axi_adrv9009_rx_os_dma CONFIG.DMA_DATA_WIDTH_SRC 64
|
||||
|
||||
# common cores
|
||||
|
||||
ad_ip_instance axi_adrv9009 axi_adrv9009_core
|
||||
|
||||
ad_ip_instance util_adxcvr util_adrv9009_xcvr
|
||||
ad_ip_parameter util_adrv9009_xcvr CONFIG.RX_NUM_OF_LANES 4
|
||||
ad_ip_parameter util_adrv9009_xcvr CONFIG.TX_NUM_OF_LANES 4
|
||||
ad_ip_parameter util_adrv9009_xcvr CONFIG.TX_OUT_DIV 1
|
||||
ad_ip_parameter util_adrv9009_xcvr CONFIG.CPLL_FBDIV 4
|
||||
ad_ip_parameter util_adrv9009_xcvr CONFIG.RX_CLK25_DIV 10
|
||||
ad_ip_parameter util_adrv9009_xcvr CONFIG.TX_CLK25_DIV 10
|
||||
ad_ip_parameter util_adrv9009_xcvr CONFIG.RX_PMA_CFG 0x001E7080
|
||||
ad_ip_parameter util_adrv9009_xcvr CONFIG.RX_CDR_CFG 0x0b000023ff10400020
|
||||
ad_ip_parameter util_adrv9009_xcvr CONFIG.QPLL_FBDIV 0x080
|
||||
|
||||
# xcvr interfaces
|
||||
|
||||
create_bd_port -dir I tx_ref_clk_0
|
||||
create_bd_port -dir I rx_ref_clk_0
|
||||
create_bd_port -dir I rx_ref_clk_2
|
||||
|
||||
ad_xcvrpll tx_ref_clk_0 util_adrv9009_xcvr/qpll_ref_clk_0
|
||||
ad_xcvrpll rx_ref_clk_0 util_adrv9009_xcvr/cpll_ref_clk_0
|
||||
ad_xcvrpll rx_ref_clk_0 util_adrv9009_xcvr/cpll_ref_clk_1
|
||||
ad_xcvrpll rx_ref_clk_2 util_adrv9009_xcvr/cpll_ref_clk_2
|
||||
ad_xcvrpll rx_ref_clk_2 util_adrv9009_xcvr/cpll_ref_clk_3
|
||||
ad_xcvrpll axi_adrv9009_tx_xcvr/up_pll_rst util_adrv9009_xcvr/up_qpll_rst_0
|
||||
ad_xcvrpll axi_adrv9009_rx_xcvr/up_pll_rst util_adrv9009_xcvr/up_cpll_rst_0
|
||||
ad_xcvrpll axi_adrv9009_rx_xcvr/up_pll_rst util_adrv9009_xcvr/up_cpll_rst_1
|
||||
ad_xcvrpll axi_adrv9009_rx_os_xcvr/up_pll_rst util_adrv9009_xcvr/up_cpll_rst_2
|
||||
ad_xcvrpll axi_adrv9009_rx_os_xcvr/up_pll_rst util_adrv9009_xcvr/up_cpll_rst_3
|
||||
ad_connect sys_cpu_resetn util_adrv9009_xcvr/up_rstn
|
||||
ad_connect sys_cpu_clk util_adrv9009_xcvr/up_clk
|
||||
|
||||
ad_xcvrcon util_adrv9009_xcvr axi_adrv9009_tx_xcvr axi_adrv9009_tx_jesd {0 3 2 1}
|
||||
ad_reconct util_adrv9009_xcvr/tx_out_clk_0 axi_adrv9009_tx_clkgen/clk
|
||||
ad_connect axi_adrv9009_tx_clkgen/clk_0 util_adrv9009_xcvr/tx_clk_0
|
||||
ad_connect axi_adrv9009_tx_clkgen/clk_0 util_adrv9009_xcvr/tx_clk_1
|
||||
ad_connect axi_adrv9009_tx_clkgen/clk_0 util_adrv9009_xcvr/tx_clk_2
|
||||
ad_connect axi_adrv9009_tx_clkgen/clk_0 util_adrv9009_xcvr/tx_clk_3
|
||||
ad_connect axi_adrv9009_tx_clkgen/clk_0 axi_adrv9009_tx_jesd/device_clk
|
||||
ad_connect axi_adrv9009_tx_clkgen/clk_0 axi_adrv9009_tx_jesd_rstgen/slowest_sync_clk
|
||||
ad_xcvrcon util_adrv9009_xcvr axi_adrv9009_rx_xcvr axi_adrv9009_rx_jesd
|
||||
ad_reconct util_adrv9009_xcvr/rx_out_clk_0 axi_adrv9009_rx_clkgen/clk
|
||||
ad_connect axi_adrv9009_rx_clkgen/clk_0 util_adrv9009_xcvr/rx_clk_0
|
||||
ad_connect axi_adrv9009_rx_clkgen/clk_0 util_adrv9009_xcvr/rx_clk_1
|
||||
ad_connect axi_adrv9009_rx_clkgen/clk_0 axi_adrv9009_rx_jesd/device_clk
|
||||
ad_connect axi_adrv9009_rx_clkgen/clk_0 axi_adrv9009_rx_jesd_rstgen/slowest_sync_clk
|
||||
ad_xcvrcon util_adrv9009_xcvr axi_adrv9009_rx_os_xcvr axi_adrv9009_rx_os_jesd
|
||||
ad_reconct util_adrv9009_xcvr/rx_out_clk_2 axi_adrv9009_rx_os_clkgen/clk
|
||||
ad_connect axi_adrv9009_rx_os_clkgen/clk_0 util_adrv9009_xcvr/rx_clk_2
|
||||
ad_connect axi_adrv9009_rx_os_clkgen/clk_0 util_adrv9009_xcvr/rx_clk_3
|
||||
ad_connect axi_adrv9009_rx_os_clkgen/clk_0 axi_adrv9009_rx_os_jesd/device_clk
|
||||
ad_connect axi_adrv9009_rx_os_clkgen/clk_0 axi_adrv9009_rx_os_jesd_rstgen/slowest_sync_clk
|
||||
|
||||
# dma clock & reset
|
||||
|
||||
ad_ip_instance proc_sys_reset sys_dma_rstgen
|
||||
ad_ip_parameter sys_dma_rstgen CONFIG.C_EXT_RST_WIDTH 1
|
||||
|
||||
ad_connect sys_dma_clk sys_dma_rstgen/slowest_sync_clk
|
||||
ad_connect sys_dma_resetn sys_dma_rstgen/peripheral_aresetn
|
||||
ad_connect sys_dma_reset sys_dma_rstgen/peripheral_reset
|
||||
ad_connect sys_dma_reset axi_adrv9009_dacfifo/dma_rst
|
||||
|
||||
# connections (dac)
|
||||
|
||||
ad_connect axi_adrv9009_tx_clkgen/clk_0 axi_adrv9009_core/dac_clk
|
||||
ad_connect axi_adrv9009_tx_jesd/tx_data_tdata axi_adrv9009_core/dac_tx_data
|
||||
ad_connect axi_adrv9009_tx_clkgen/clk_0 util_adrv9009_tx_upack/dac_clk
|
||||
ad_connect axi_adrv9009_core/dac_valid_i0 util_adrv9009_tx_upack/dac_valid_0
|
||||
ad_connect axi_adrv9009_core/dac_enable_i0 util_adrv9009_tx_upack/dac_enable_0
|
||||
ad_connect axi_adrv9009_core/dac_data_i0 util_adrv9009_tx_upack/dac_data_0
|
||||
ad_connect axi_adrv9009_core/dac_valid_q0 util_adrv9009_tx_upack/dac_valid_1
|
||||
ad_connect axi_adrv9009_core/dac_enable_q0 util_adrv9009_tx_upack/dac_enable_1
|
||||
ad_connect axi_adrv9009_core/dac_data_q0 util_adrv9009_tx_upack/dac_data_1
|
||||
ad_connect axi_adrv9009_core/dac_valid_i1 util_adrv9009_tx_upack/dac_valid_2
|
||||
ad_connect axi_adrv9009_core/dac_enable_i1 util_adrv9009_tx_upack/dac_enable_2
|
||||
ad_connect axi_adrv9009_core/dac_data_i1 util_adrv9009_tx_upack/dac_data_2
|
||||
ad_connect axi_adrv9009_core/dac_valid_q1 util_adrv9009_tx_upack/dac_valid_3
|
||||
ad_connect axi_adrv9009_core/dac_enable_q1 util_adrv9009_tx_upack/dac_enable_3
|
||||
ad_connect axi_adrv9009_core/dac_data_q1 util_adrv9009_tx_upack/dac_data_3
|
||||
ad_connect axi_adrv9009_tx_clkgen/clk_0 axi_adrv9009_dacfifo/dac_clk
|
||||
ad_connect axi_adrv9009_tx_jesd_rstgen/peripheral_reset axi_adrv9009_dacfifo/dac_rst
|
||||
ad_connect util_adrv9009_tx_upack/dac_valid axi_adrv9009_dacfifo/dac_valid
|
||||
ad_connect util_adrv9009_tx_upack/dac_data axi_adrv9009_dacfifo/dac_data
|
||||
ad_connect sys_dma_clk axi_adrv9009_dacfifo/dma_clk
|
||||
ad_connect sys_dma_clk axi_adrv9009_tx_dma/m_axis_aclk
|
||||
ad_connect axi_adrv9009_dacfifo/dma_valid axi_adrv9009_tx_dma/m_axis_valid
|
||||
ad_connect axi_adrv9009_dacfifo/dma_data axi_adrv9009_tx_dma/m_axis_data
|
||||
ad_connect axi_adrv9009_dacfifo/dma_ready axi_adrv9009_tx_dma/m_axis_ready
|
||||
ad_connect axi_adrv9009_dacfifo/dma_xfer_req axi_adrv9009_tx_dma/m_axis_xfer_req
|
||||
ad_connect axi_adrv9009_dacfifo/dma_xfer_last axi_adrv9009_tx_dma/m_axis_last
|
||||
ad_connect axi_adrv9009_dacfifo/dac_dunf axi_adrv9009_core/dac_dunf
|
||||
ad_connect axi_adrv9009_dacfifo/bypass dac_fifo_bypass
|
||||
ad_connect sys_dma_resetn axi_adrv9009_tx_dma/m_src_axi_aresetn
|
||||
|
||||
# connections (adc)
|
||||
|
||||
ad_connect axi_adrv9009_rx_clkgen/clk_0 axi_adrv9009_core/adc_clk
|
||||
ad_connect axi_adrv9009_rx_jesd/rx_sof axi_adrv9009_core/adc_rx_sof
|
||||
ad_connect axi_adrv9009_rx_jesd/rx_data_tdata axi_adrv9009_core/adc_rx_data
|
||||
ad_connect axi_adrv9009_rx_clkgen/clk_0 util_adrv9009_rx_cpack/adc_clk
|
||||
ad_connect axi_adrv9009_rx_jesd_rstgen/peripheral_reset util_adrv9009_rx_cpack/adc_rst
|
||||
ad_connect axi_adrv9009_core/adc_enable_i0 util_adrv9009_rx_cpack/adc_enable_0
|
||||
ad_connect axi_adrv9009_core/adc_valid_i0 util_adrv9009_rx_cpack/adc_valid_0
|
||||
ad_connect axi_adrv9009_core/adc_data_i0 util_adrv9009_rx_cpack/adc_data_0
|
||||
ad_connect axi_adrv9009_core/adc_enable_q0 util_adrv9009_rx_cpack/adc_enable_1
|
||||
ad_connect axi_adrv9009_core/adc_valid_q0 util_adrv9009_rx_cpack/adc_valid_1
|
||||
ad_connect axi_adrv9009_core/adc_data_q0 util_adrv9009_rx_cpack/adc_data_1
|
||||
ad_connect axi_adrv9009_core/adc_enable_i1 util_adrv9009_rx_cpack/adc_enable_2
|
||||
ad_connect axi_adrv9009_core/adc_valid_i1 util_adrv9009_rx_cpack/adc_valid_2
|
||||
ad_connect axi_adrv9009_core/adc_data_i1 util_adrv9009_rx_cpack/adc_data_2
|
||||
ad_connect axi_adrv9009_core/adc_enable_q1 util_adrv9009_rx_cpack/adc_enable_3
|
||||
ad_connect axi_adrv9009_core/adc_valid_q1 util_adrv9009_rx_cpack/adc_valid_3
|
||||
ad_connect axi_adrv9009_core/adc_data_q1 util_adrv9009_rx_cpack/adc_data_3
|
||||
ad_connect axi_adrv9009_rx_clkgen/clk_0 axi_adrv9009_rx_dma/fifo_wr_clk
|
||||
ad_connect util_adrv9009_rx_cpack/adc_valid axi_adrv9009_rx_dma/fifo_wr_en
|
||||
ad_connect util_adrv9009_rx_cpack/adc_sync axi_adrv9009_rx_dma/fifo_wr_sync
|
||||
ad_connect util_adrv9009_rx_cpack/adc_data axi_adrv9009_rx_dma/fifo_wr_din
|
||||
ad_connect axi_adrv9009_rx_dma/fifo_wr_overflow axi_adrv9009_core/adc_dovf
|
||||
ad_connect sys_dma_resetn axi_adrv9009_rx_dma/m_dest_axi_aresetn
|
||||
|
||||
# connections (adc-os)
|
||||
|
||||
ad_connect axi_adrv9009_rx_os_clkgen/clk_0 axi_adrv9009_core/adc_os_clk
|
||||
ad_connect axi_adrv9009_rx_os_jesd/rx_sof axi_adrv9009_core/adc_rx_os_sof
|
||||
ad_connect axi_adrv9009_rx_os_jesd/rx_data_tdata axi_adrv9009_core/adc_rx_os_data
|
||||
ad_connect axi_adrv9009_rx_os_clkgen/clk_0 util_adrv9009_rx_os_cpack/adc_clk
|
||||
ad_connect axi_adrv9009_rx_os_jesd_rstgen/peripheral_reset util_adrv9009_rx_os_cpack/adc_rst
|
||||
ad_connect axi_adrv9009_core/adc_os_enable_i0 util_adrv9009_rx_os_cpack/adc_enable_0
|
||||
ad_connect axi_adrv9009_core/adc_os_valid_i0 util_adrv9009_rx_os_cpack/adc_valid_0
|
||||
ad_connect axi_adrv9009_core/adc_os_data_i0 util_adrv9009_rx_os_cpack/adc_data_0
|
||||
ad_connect axi_adrv9009_core/adc_os_enable_q0 util_adrv9009_rx_os_cpack/adc_enable_1
|
||||
ad_connect axi_adrv9009_core/adc_os_valid_q0 util_adrv9009_rx_os_cpack/adc_valid_1
|
||||
ad_connect axi_adrv9009_core/adc_os_data_q0 util_adrv9009_rx_os_cpack/adc_data_1
|
||||
ad_connect axi_adrv9009_rx_os_clkgen/clk_0 axi_adrv9009_rx_os_dma/fifo_wr_clk
|
||||
ad_connect util_adrv9009_rx_os_cpack/adc_valid axi_adrv9009_rx_os_dma/fifo_wr_en
|
||||
ad_connect util_adrv9009_rx_os_cpack/adc_sync axi_adrv9009_rx_os_dma/fifo_wr_sync
|
||||
ad_connect util_adrv9009_rx_os_cpack/adc_data axi_adrv9009_rx_os_dma/fifo_wr_din
|
||||
ad_connect axi_adrv9009_rx_os_dma/fifo_wr_overflow axi_adrv9009_core/adc_os_dovf
|
||||
ad_connect sys_dma_resetn axi_adrv9009_rx_os_dma/m_dest_axi_aresetn
|
||||
|
||||
# interconnect (cpu)
|
||||
|
||||
ad_cpu_interconnect 0x44A00000 axi_adrv9009_core
|
||||
ad_cpu_interconnect 0x44A80000 axi_adrv9009_tx_xcvr
|
||||
ad_cpu_interconnect 0x43C00000 axi_adrv9009_tx_clkgen
|
||||
ad_cpu_interconnect 0x44A90000 axi_adrv9009_tx_jesd
|
||||
ad_cpu_interconnect 0x7c420000 axi_adrv9009_tx_dma
|
||||
ad_cpu_interconnect 0x44A60000 axi_adrv9009_rx_xcvr
|
||||
ad_cpu_interconnect 0x43C10000 axi_adrv9009_rx_clkgen
|
||||
ad_cpu_interconnect 0x44AA0000 axi_adrv9009_rx_jesd
|
||||
ad_cpu_interconnect 0x7c400000 axi_adrv9009_rx_dma
|
||||
ad_cpu_interconnect 0x44A50000 axi_adrv9009_rx_os_xcvr
|
||||
ad_cpu_interconnect 0x43C20000 axi_adrv9009_rx_os_clkgen
|
||||
ad_cpu_interconnect 0x44AB0000 axi_adrv9009_rx_os_jesd
|
||||
ad_cpu_interconnect 0x7c440000 axi_adrv9009_rx_os_dma
|
||||
|
||||
# gt uses hp3, and 100MHz clock for both DRP and AXI4
|
||||
|
||||
ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3
|
||||
ad_mem_hp3_interconnect sys_cpu_clk axi_adrv9009_rx_xcvr/m_axi
|
||||
ad_mem_hp3_interconnect sys_cpu_clk axi_adrv9009_rx_os_xcvr/m_axi
|
||||
|
||||
# interconnect (mem/dac)
|
||||
|
||||
ad_mem_hp1_interconnect sys_dma_clk sys_ps7/S_AXI_HP1
|
||||
ad_mem_hp1_interconnect sys_dma_clk axi_adrv9009_tx_dma/m_src_axi
|
||||
ad_mem_hp2_interconnect sys_dma_clk sys_ps7/S_AXI_HP2
|
||||
ad_mem_hp2_interconnect sys_dma_clk axi_adrv9009_rx_dma/m_dest_axi
|
||||
ad_mem_hp2_interconnect sys_dma_clk axi_adrv9009_rx_os_dma/m_dest_axi
|
||||
|
||||
# interrupts
|
||||
|
||||
ad_cpu_interrupt ps-8 mb-8 axi_adrv9009_rx_os_jesd/irq
|
||||
ad_cpu_interrupt ps-9 mb-7 axi_adrv9009_tx_jesd/irq
|
||||
ad_cpu_interrupt ps-10 mb-15 axi_adrv9009_rx_jesd/irq
|
||||
ad_cpu_interrupt ps-11 mb-14 axi_adrv9009_rx_os_dma/irq
|
||||
ad_cpu_interrupt ps-12 mb-13- axi_adrv9009_tx_dma/irq
|
||||
ad_cpu_interrupt ps-13 mb-12 axi_adrv9009_rx_dma/irq
|
||||
|
|
@ -3,9 +3,9 @@
|
|||
## Auto-generated, do not modify!
|
||||
####################################################################################
|
||||
|
||||
PROJECT_NAME := adrv9379_zc706
|
||||
PROJECT_NAME := adrv9009_zc706
|
||||
|
||||
M_DEPS += ../common/adrv9379_bd.tcl
|
||||
M_DEPS += ../common/adrv9009_bd.tcl
|
||||
M_DEPS += ../../common/zc706/zc706_system_constr.xdc
|
||||
M_DEPS += ../../common/zc706/zc706_system_bd.tcl
|
||||
M_DEPS += ../../common/zc706/zc706_plddr3_dacfifo_bd.tcl
|
||||
|
|
@ -13,7 +13,7 @@ M_DEPS += ../../common/zc706/zc706_plddr3_constr.xdc
|
|||
M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
|
||||
M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl
|
||||
|
||||
LIB_DEPS += axi_ad9379
|
||||
LIB_DEPS += axi_adrv9009
|
||||
LIB_DEPS += axi_clkgen
|
||||
LIB_DEPS += axi_dmac
|
||||
LIB_DEPS += axi_hdmi_tx
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
|
||||
set dac_fifo_name axi_ad9379_dacfifo
|
||||
set dac_fifo_name axi_adrv9009_dacfifo
|
||||
set dac_fifo_address_width 10
|
||||
set dac_data_width 128
|
||||
set dac_dma_data_width 128
|
||||
|
|
@ -9,7 +9,7 @@ source $ad_hdl_dir/projects/common/zc706/zc706_plddr3_dacfifo_bd.tcl
|
|||
|
||||
ad_ip_parameter sys_ps7 CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ 250
|
||||
|
||||
source ../common/adrv9379_bd.tcl
|
||||
source ../common/adrv9009_bd.tcl
|
||||
|
||||
ad_connect sys_dma_clk sys_ps7/FCLK_CLK2
|
||||
ad_connect sys_ps7/FCLK_RESET2_N sys_dma_rstgen/ext_reset_in
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
|
||||
# ad9379
|
||||
# adrv9009
|
||||
|
||||
set_property -dict {PACKAGE_PIN AD10} [get_ports ref_clk0_p] ; ## D04 FMC_HPC_GBTCLK0_M2C_P (NC)
|
||||
set_property -dict {PACKAGE_PIN AD9 } [get_ports ref_clk0_n] ; ## D05 FMC_HPC_GBTCLK0_M2C_N (NC)
|
||||
|
|
@ -35,45 +35,45 @@ set_property -dict {PACKAGE_PIN AG21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_
|
|||
set_property -dict {PACKAGE_PIN AH21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports sysref_out_n] ; ## D09 FMC_HPC_LA01_CC_N
|
||||
|
||||
set_property -dict {PACKAGE_PIN AE21 IOSTANDARD LVCMOS25} [get_ports spi_csn_ad9528] ; ## D15 FMC_HPC_LA09_N
|
||||
set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVCMOS25} [get_ports spi_csn_ad9379] ; ## D14 FMC_HPC_LA09_P
|
||||
set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVCMOS25} [get_ports spi_csn_adrv9009] ; ## D14 FMC_HPC_LA09_P
|
||||
set_property -dict {PACKAGE_PIN AJ23 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## H13 FMC_HPC_LA07_P
|
||||
set_property -dict {PACKAGE_PIN AJ24 IOSTANDARD LVCMOS25} [get_ports spi_mosi] ; ## H14 FMC_HPC_LA07_N
|
||||
set_property -dict {PACKAGE_PIN AF19 IOSTANDARD LVCMOS25} [get_ports spi_miso] ; ## G12 FMC_HPC_LA08_P
|
||||
|
||||
set_property -dict {PACKAGE_PIN R28 IOSTANDARD LVCMOS25} [get_ports ad9528_reset_b] ; ## D26 FMC_HPC_LA26_P
|
||||
set_property -dict {PACKAGE_PIN T28 IOSTANDARD LVCMOS25} [get_ports ad9528_sysref_req] ; ## D27 FMC_HPC_LA26_N
|
||||
set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVCMOS25} [get_ports ad9379_tx1_enable] ; ## D17 FMC_HPC_LA13_P
|
||||
set_property -dict {PACKAGE_PIN AC24 IOSTANDARD LVCMOS25} [get_ports ad9379_tx2_enable] ; ## C18 FMC_HPC_LA14_P
|
||||
set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVCMOS25} [get_ports ad9379_rx1_enable] ; ## D18 FMC_HPC_LA13_N
|
||||
set_property -dict {PACKAGE_PIN AD24 IOSTANDARD LVCMOS25} [get_ports ad9379_rx2_enable] ; ## C19 FMC_HPC_LA14_N
|
||||
set_property -dict {PACKAGE_PIN AH23 IOSTANDARD LVCMOS25} [get_ports ad9379_test] ; ## D11 FMC_HPC_LA05_P
|
||||
set_property -dict {PACKAGE_PIN AJ20 IOSTANDARD LVCMOS25} [get_ports ad9379_reset_b] ; ## H10 FMC_HPC_LA04_P
|
||||
set_property -dict {PACKAGE_PIN AK20 IOSTANDARD LVCMOS25} [get_ports ad9379_gpint] ; ## H11 FMC_HPC_LA04_N
|
||||
set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVCMOS25} [get_ports adrv9009_tx1_enable] ; ## D17 FMC_HPC_LA13_P
|
||||
set_property -dict {PACKAGE_PIN AC24 IOSTANDARD LVCMOS25} [get_ports adrv9009_tx2_enable] ; ## C18 FMC_HPC_LA14_P
|
||||
set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVCMOS25} [get_ports adrv9009_rx1_enable] ; ## D18 FMC_HPC_LA13_N
|
||||
set_property -dict {PACKAGE_PIN AD24 IOSTANDARD LVCMOS25} [get_ports adrv9009_rx2_enable] ; ## C19 FMC_HPC_LA14_N
|
||||
set_property -dict {PACKAGE_PIN AH23 IOSTANDARD LVCMOS25} [get_ports adrv9009_test] ; ## D11 FMC_HPC_LA05_P
|
||||
set_property -dict {PACKAGE_PIN AJ20 IOSTANDARD LVCMOS25} [get_ports adrv9009_reset_b] ; ## H10 FMC_HPC_LA04_P
|
||||
set_property -dict {PACKAGE_PIN AK20 IOSTANDARD LVCMOS25} [get_ports adrv9009_gpint] ; ## H11 FMC_HPC_LA04_N
|
||||
|
||||
set_property -dict {PACKAGE_PIN Y22 IOSTANDARD LVCMOS25} [get_ports ad9379_gpio_00] ; ## H19 FMC_HPC_LA15_P
|
||||
set_property -dict {PACKAGE_PIN Y23 IOSTANDARD LVCMOS25} [get_ports ad9379_gpio_01] ; ## H20 FMC_HPC_LA15_N
|
||||
set_property -dict {PACKAGE_PIN AA24 IOSTANDARD LVCMOS25} [get_ports ad9379_gpio_02] ; ## G18 FMC_HPC_LA16_P
|
||||
set_property -dict {PACKAGE_PIN AB24 IOSTANDARD LVCMOS25} [get_ports ad9379_gpio_03] ; ## G19 FMC_HPC_LA16_N
|
||||
set_property -dict {PACKAGE_PIN W29 IOSTANDARD LVCMOS25} [get_ports ad9379_gpio_04] ; ## H25 FMC_HPC_LA21_P
|
||||
set_property -dict {PACKAGE_PIN W30 IOSTANDARD LVCMOS25} [get_ports ad9379_gpio_05] ; ## H26 FMC_HPC_LA21_N
|
||||
set_property -dict {PACKAGE_PIN W25 IOSTANDARD LVCMOS25} [get_ports ad9379_gpio_06] ; ## C22 FMC_HPC_LA18_CC_P
|
||||
set_property -dict {PACKAGE_PIN W26 IOSTANDARD LVCMOS25} [get_ports ad9379_gpio_07] ; ## C23 FMC_HPC_LA18_CC_N
|
||||
set_property -dict {PACKAGE_PIN W28 IOSTANDARD LVCMOS25} [get_ports ad9379_gpio_08] ; ## G25 FMC_HPC_LA22_N (LVDS Pairs?)
|
||||
set_property -dict {PACKAGE_PIN T24 IOSTANDARD LVCMOS25} [get_ports ad9379_gpio_09] ; ## H22 FMC_HPC_LA19_P (LVDS Pairs?)
|
||||
set_property -dict {PACKAGE_PIN T25 IOSTANDARD LVCMOS25} [get_ports ad9379_gpio_10] ; ## H23 FMC_HPC_LA19_N (LVDS Pairs?)
|
||||
set_property -dict {PACKAGE_PIN U25 IOSTANDARD LVCMOS25} [get_ports ad9379_gpio_11] ; ## G21 FMC_HPC_LA20_P (LVDS Pairs?)
|
||||
set_property -dict {PACKAGE_PIN V26 IOSTANDARD LVCMOS25} [get_ports ad9379_gpio_12] ; ## G22 FMC_HPC_LA20_N (LVDS Pairs?)
|
||||
set_property -dict {PACKAGE_PIN R26 IOSTANDARD LVCMOS25} [get_ports ad9379_gpio_13] ; ## G31 FMC_HPC_LA29_N (LVDS Pairs?)
|
||||
set_property -dict {PACKAGE_PIN R25 IOSTANDARD LVCMOS25} [get_ports ad9379_gpio_14] ; ## G30 FMC_HPC_LA29_P (LVDS Pairs?)
|
||||
set_property -dict {PACKAGE_PIN V27 IOSTANDARD LVCMOS25} [get_ports ad9379_gpio_15] ; ## G24 FMC_HPC_LA22_P (LVDS Pairs?)
|
||||
set_property -dict {PACKAGE_PIN U27 IOSTANDARD LVCMOS25} [get_ports ad9379_gpio_16] ; ## G03 FMC_HPC_CLK1_M2C_N (LVDS Pairs?)
|
||||
set_property -dict {PACKAGE_PIN U26 IOSTANDARD LVCMOS25} [get_ports ad9379_gpio_17] ; ## G02 FMC_HPC_CLK1_M2C_P (LVDS Pairs?)
|
||||
set_property -dict {PACKAGE_PIN AH24 IOSTANDARD LVCMOS25} [get_ports ad9379_gpio_18] ; ## D12 FMC_HPC_LA05_N
|
||||
set_property -dict {PACKAGE_PIN Y22 IOSTANDARD LVCMOS25} [get_ports adrv9009_gpio_00] ; ## H19 FMC_HPC_LA15_P
|
||||
set_property -dict {PACKAGE_PIN Y23 IOSTANDARD LVCMOS25} [get_ports adrv9009_gpio_01] ; ## H20 FMC_HPC_LA15_N
|
||||
set_property -dict {PACKAGE_PIN AA24 IOSTANDARD LVCMOS25} [get_ports adrv9009_gpio_02] ; ## G18 FMC_HPC_LA16_P
|
||||
set_property -dict {PACKAGE_PIN AB24 IOSTANDARD LVCMOS25} [get_ports adrv9009_gpio_03] ; ## G19 FMC_HPC_LA16_N
|
||||
set_property -dict {PACKAGE_PIN W29 IOSTANDARD LVCMOS25} [get_ports adrv9009_gpio_04] ; ## H25 FMC_HPC_LA21_P
|
||||
set_property -dict {PACKAGE_PIN W30 IOSTANDARD LVCMOS25} [get_ports adrv9009_gpio_05] ; ## H26 FMC_HPC_LA21_N
|
||||
set_property -dict {PACKAGE_PIN W25 IOSTANDARD LVCMOS25} [get_ports adrv9009_gpio_06] ; ## C22 FMC_HPC_LA18_CC_P
|
||||
set_property -dict {PACKAGE_PIN W26 IOSTANDARD LVCMOS25} [get_ports adrv9009_gpio_07] ; ## C23 FMC_HPC_LA18_CC_N
|
||||
set_property -dict {PACKAGE_PIN W28 IOSTANDARD LVCMOS25} [get_ports adrv9009_gpio_08] ; ## G25 FMC_HPC_LA22_N (LVDS Pairs?)
|
||||
set_property -dict {PACKAGE_PIN T24 IOSTANDARD LVCMOS25} [get_ports adrv9009_gpio_09] ; ## H22 FMC_HPC_LA19_P (LVDS Pairs?)
|
||||
set_property -dict {PACKAGE_PIN T25 IOSTANDARD LVCMOS25} [get_ports adrv9009_gpio_10] ; ## H23 FMC_HPC_LA19_N (LVDS Pairs?)
|
||||
set_property -dict {PACKAGE_PIN U25 IOSTANDARD LVCMOS25} [get_ports adrv9009_gpio_11] ; ## G21 FMC_HPC_LA20_P (LVDS Pairs?)
|
||||
set_property -dict {PACKAGE_PIN V26 IOSTANDARD LVCMOS25} [get_ports adrv9009_gpio_12] ; ## G22 FMC_HPC_LA20_N (LVDS Pairs?)
|
||||
set_property -dict {PACKAGE_PIN R26 IOSTANDARD LVCMOS25} [get_ports adrv9009_gpio_13] ; ## G31 FMC_HPC_LA29_N (LVDS Pairs?)
|
||||
set_property -dict {PACKAGE_PIN R25 IOSTANDARD LVCMOS25} [get_ports adrv9009_gpio_14] ; ## G30 FMC_HPC_LA29_P (LVDS Pairs?)
|
||||
set_property -dict {PACKAGE_PIN V27 IOSTANDARD LVCMOS25} [get_ports adrv9009_gpio_15] ; ## G24 FMC_HPC_LA22_P (LVDS Pairs?)
|
||||
set_property -dict {PACKAGE_PIN U27 IOSTANDARD LVCMOS25} [get_ports adrv9009_gpio_16] ; ## G03 FMC_HPC_CLK1_M2C_N (LVDS Pairs?)
|
||||
set_property -dict {PACKAGE_PIN U26 IOSTANDARD LVCMOS25} [get_ports adrv9009_gpio_17] ; ## G02 FMC_HPC_CLK1_M2C_P (LVDS Pairs?)
|
||||
set_property -dict {PACKAGE_PIN AH24 IOSTANDARD LVCMOS25} [get_ports adrv9009_gpio_18] ; ## D12 FMC_HPC_LA05_N
|
||||
|
||||
# clocks
|
||||
|
||||
create_clock -name tx_ref_clk -period 4.00 [get_ports ref_clk0_p]
|
||||
create_clock -name rx_ref_clk -period 4.00 [get_ports ref_clk1_p]
|
||||
create_clock -name tx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/util_ad9379_xcvr/inst/i_xch_0/i_gtxe2_channel/TXOUTCLK]
|
||||
create_clock -name rx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/util_ad9379_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]
|
||||
create_clock -name rx_os_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/util_ad9379_xcvr/inst/i_xch_2/i_gtxe2_channel/RXOUTCLK]
|
||||
create_clock -name tx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/util_adrv9009_xcvr/inst/i_xch_0/i_gtxe2_channel/TXOUTCLK]
|
||||
create_clock -name rx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/util_adrv9009_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]
|
||||
create_clock -name rx_os_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/util_adrv9009_xcvr/inst/i_xch_2/i_gtxe2_channel/RXOUTCLK]
|
||||
|
|
@ -5,14 +5,14 @@ source ../../scripts/adi_env.tcl
|
|||
source $ad_hdl_dir/projects/scripts/adi_project.tcl
|
||||
source $ad_hdl_dir/projects/scripts/adi_board.tcl
|
||||
|
||||
adi_project_xilinx adrv9379_zc706
|
||||
adi_project_files adrv9379_zc706 [list \
|
||||
adi_project_xilinx adrv9009_zc706
|
||||
adi_project_files adrv9009_zc706 [list \
|
||||
"system_top.v" \
|
||||
"system_constr.xdc"\
|
||||
"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
|
||||
"$ad_hdl_dir/projects/common/zc706/zc706_plddr3_constr.xdc" \
|
||||
"$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
|
||||
|
||||
adi_project_run adrv9379_zc706
|
||||
adi_project_run adrv9009_zc706
|
||||
|
||||
|
||||
|
|
@ -96,40 +96,40 @@ module system_top (
|
|||
output sysref_out_n,
|
||||
|
||||
output spi_csn_ad9528,
|
||||
output spi_csn_ad9379,
|
||||
output spi_csn_adrv9009,
|
||||
output spi_clk,
|
||||
output spi_mosi,
|
||||
input spi_miso,
|
||||
|
||||
inout ad9528_reset_b,
|
||||
inout ad9528_sysref_req,
|
||||
inout ad9379_tx1_enable,
|
||||
inout ad9379_tx2_enable,
|
||||
inout ad9379_rx1_enable,
|
||||
inout ad9379_rx2_enable,
|
||||
inout ad9379_test,
|
||||
inout ad9379_reset_b,
|
||||
inout ad9379_gpint,
|
||||
inout adrv9009_tx1_enable,
|
||||
inout adrv9009_tx2_enable,
|
||||
inout adrv9009_rx1_enable,
|
||||
inout adrv9009_rx2_enable,
|
||||
inout adrv9009_test,
|
||||
inout adrv9009_reset_b,
|
||||
inout adrv9009_gpint,
|
||||
|
||||
inout ad9379_gpio_00,
|
||||
inout ad9379_gpio_01,
|
||||
inout ad9379_gpio_02,
|
||||
inout ad9379_gpio_03,
|
||||
inout ad9379_gpio_04,
|
||||
inout ad9379_gpio_05,
|
||||
inout ad9379_gpio_06,
|
||||
inout ad9379_gpio_07,
|
||||
inout ad9379_gpio_15,
|
||||
inout ad9379_gpio_08,
|
||||
inout ad9379_gpio_09,
|
||||
inout ad9379_gpio_10,
|
||||
inout ad9379_gpio_11,
|
||||
inout ad9379_gpio_12,
|
||||
inout ad9379_gpio_14,
|
||||
inout ad9379_gpio_13,
|
||||
inout ad9379_gpio_17,
|
||||
inout ad9379_gpio_16,
|
||||
inout ad9379_gpio_18,
|
||||
inout adrv9009_gpio_00,
|
||||
inout adrv9009_gpio_01,
|
||||
inout adrv9009_gpio_02,
|
||||
inout adrv9009_gpio_03,
|
||||
inout adrv9009_gpio_04,
|
||||
inout adrv9009_gpio_05,
|
||||
inout adrv9009_gpio_06,
|
||||
inout adrv9009_gpio_07,
|
||||
inout adrv9009_gpio_15,
|
||||
inout adrv9009_gpio_08,
|
||||
inout adrv9009_gpio_09,
|
||||
inout adrv9009_gpio_10,
|
||||
inout adrv9009_gpio_11,
|
||||
inout adrv9009_gpio_12,
|
||||
inout adrv9009_gpio_14,
|
||||
inout adrv9009_gpio_13,
|
||||
inout adrv9009_gpio_17,
|
||||
inout adrv9009_gpio_16,
|
||||
inout adrv9009_gpio_18,
|
||||
|
||||
input sys_rst,
|
||||
input sys_clk_p,
|
||||
|
|
@ -221,32 +221,32 @@ module system_top (
|
|||
.dio_o ({gpio_i[59:32]}),
|
||||
.dio_p ({ ad9528_reset_b, // 59
|
||||
ad9528_sysref_req, // 58
|
||||
ad9379_tx1_enable, // 57
|
||||
ad9379_tx2_enable, // 56
|
||||
ad9379_rx1_enable, // 55
|
||||
ad9379_rx2_enable, // 54
|
||||
ad9379_test, // 53
|
||||
ad9379_reset_b, // 52
|
||||
ad9379_gpint, // 51
|
||||
ad9379_gpio_00, // 50
|
||||
ad9379_gpio_01, // 49
|
||||
ad9379_gpio_02, // 48
|
||||
ad9379_gpio_03, // 47
|
||||
ad9379_gpio_04, // 46
|
||||
ad9379_gpio_05, // 45
|
||||
ad9379_gpio_06, // 44
|
||||
ad9379_gpio_07, // 43
|
||||
ad9379_gpio_15, // 42
|
||||
ad9379_gpio_08, // 41
|
||||
ad9379_gpio_09, // 40
|
||||
ad9379_gpio_10, // 39
|
||||
ad9379_gpio_11, // 38
|
||||
ad9379_gpio_12, // 37
|
||||
ad9379_gpio_14, // 36
|
||||
ad9379_gpio_13, // 35
|
||||
ad9379_gpio_17, // 34
|
||||
ad9379_gpio_16, // 33
|
||||
ad9379_gpio_18})); // 32
|
||||
adrv9009_tx1_enable, // 57
|
||||
adrv9009_tx2_enable, // 56
|
||||
adrv9009_rx1_enable, // 55
|
||||
adrv9009_rx2_enable, // 54
|
||||
adrv9009_test, // 53
|
||||
adrv9009_reset_b, // 52
|
||||
adrv9009_gpint, // 51
|
||||
adrv9009_gpio_00, // 50
|
||||
adrv9009_gpio_01, // 49
|
||||
adrv9009_gpio_02, // 48
|
||||
adrv9009_gpio_03, // 47
|
||||
adrv9009_gpio_04, // 46
|
||||
adrv9009_gpio_05, // 45
|
||||
adrv9009_gpio_06, // 44
|
||||
adrv9009_gpio_07, // 43
|
||||
adrv9009_gpio_15, // 42
|
||||
adrv9009_gpio_08, // 41
|
||||
adrv9009_gpio_09, // 40
|
||||
adrv9009_gpio_10, // 39
|
||||
adrv9009_gpio_11, // 38
|
||||
adrv9009_gpio_12, // 37
|
||||
adrv9009_gpio_14, // 36
|
||||
adrv9009_gpio_13, // 35
|
||||
adrv9009_gpio_17, // 34
|
||||
adrv9009_gpio_16, // 33
|
||||
adrv9009_gpio_18})); // 32
|
||||
|
||||
ad_iobuf #(.DATA_WIDTH(15)) i_iobuf_bd (
|
||||
.dio_t (gpio_t[14:0]),
|
||||
|
|
@ -327,7 +327,7 @@ module system_top (
|
|||
.spdif (spdif),
|
||||
.spi0_clk_i (spi_clk),
|
||||
.spi0_clk_o (spi_clk),
|
||||
.spi0_csn_0_o (spi_csn_ad9379),
|
||||
.spi0_csn_0_o (spi_csn_adrv9009),
|
||||
.spi0_csn_1_o (spi_csn_ad9528),
|
||||
.spi0_csn_2_o (),
|
||||
.spi0_csn_i (1'b1),
|
||||
|
|
@ -3,16 +3,16 @@
|
|||
## Auto-generated, do not modify!
|
||||
####################################################################################
|
||||
|
||||
PROJECT_NAME := adrv9379_zcu102
|
||||
PROJECT_NAME := adrv9009_zcu102
|
||||
|
||||
M_DEPS += ../common/adrv9379_bd.tcl
|
||||
M_DEPS += ../common/adrv9009_bd.tcl
|
||||
M_DEPS += ../../common/zcu102/zcu102_system_constr.xdc
|
||||
M_DEPS += ../../common/zcu102/zcu102_system_bd.tcl
|
||||
M_DEPS += ../../common/xilinx/dacfifo_bd.tcl
|
||||
M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
|
||||
M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl
|
||||
|
||||
LIB_DEPS += axi_ad9379
|
||||
LIB_DEPS += axi_adrv9009
|
||||
LIB_DEPS += axi_clkgen
|
||||
LIB_DEPS += axi_dmac
|
||||
LIB_DEPS += jesd204/axi_jesd204_rx
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
|
||||
set dac_fifo_name axi_adrv9009_dacfifo
|
||||
set dac_fifo_address_width 10
|
||||
set dac_data_width 128
|
||||
set dac_dma_data_width 128
|
||||
|
||||
source $ad_hdl_dir/projects/common/zcu102/zcu102_system_bd.tcl
|
||||
source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl
|
||||
|
||||
ad_ip_parameter sys_ps8 CONFIG.PSU__FPGA_PL2_ENABLE 1
|
||||
ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL2_REF_CTRL__SRCSEL {IOPLL}
|
||||
ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ 200
|
||||
|
||||
source ../common/adrv9009_bd.tcl
|
||||
|
||||
ad_connect sys_dma_clk sys_ps8/pl_clk2
|
||||
ad_connect sys_dma_rstgen/ext_reset_in sys_rstgen/peripheral_reset
|
||||
|
||||
ad_ip_parameter axi_adrv9009_tx_xcvr CONFIG.XCVR_TYPE 2
|
||||
ad_ip_parameter axi_adrv9009_rx_xcvr CONFIG.XCVR_TYPE 2
|
||||
ad_ip_parameter axi_adrv9009_rx_os_xcvr CONFIG.XCVR_TYPE 2
|
||||
|
||||
ad_ip_parameter util_adrv9009_xcvr CONFIG.XCVR_TYPE 2
|
||||
ad_ip_parameter util_adrv9009_xcvr CONFIG.QPLL_FBDIV 80
|
||||
ad_ip_parameter util_adrv9009_xcvr CONFIG.QPLL_REFCLK_DIV 1
|
||||
|
||||
ad_ip_parameter axi_adrv9009_rx_clkgen CONFIG.DEVICE_TYPE 2
|
||||
ad_ip_parameter axi_adrv9009_tx_clkgen CONFIG.DEVICE_TYPE 2
|
||||
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
|
||||
# ad9379
|
||||
# adrv9009
|
||||
|
||||
set_property -dict {PACKAGE_PIN G27} [get_ports ref_clk0_p] ; ## D04 FMC_HPC1_GBTCLK0_M2C_C_P (NC)
|
||||
set_property -dict {PACKAGE_PIN G28} [get_ports ref_clk0_n] ; ## D05 FMC_HPC1_GBTCLK0_M2C_C_N (NC)
|
||||
|
|
@ -35,51 +35,51 @@ set_property -dict {PACKAGE_PIN AJ6 IOSTANDARD LVDS } [get_ports sysref_out_p
|
|||
set_property -dict {PACKAGE_PIN AJ5 IOSTANDARD LVDS } [get_ports sysref_out_n] ; ## D09 FMC_HPC1_LA01_CC_N
|
||||
|
||||
set_property -dict {PACKAGE_PIN AE1 IOSTANDARD LVCMOS18} [get_ports spi_csn_ad9528] ; ## D15 FMC_HPC1_LA09_N
|
||||
set_property -dict {PACKAGE_PIN AE2 IOSTANDARD LVCMOS18} [get_ports spi_csn_ad9379] ; ## D14 FMC_HPC1_LA09_P
|
||||
set_property -dict {PACKAGE_PIN AE2 IOSTANDARD LVCMOS18} [get_ports spi_csn_adrv9009] ; ## D14 FMC_HPC1_LA09_P
|
||||
set_property -dict {PACKAGE_PIN AD4 IOSTANDARD LVCMOS18} [get_ports spi_clk] ; ## H13 FMC_HPC1_LA07_P
|
||||
set_property -dict {PACKAGE_PIN AE4 IOSTANDARD LVCMOS18} [get_ports spi_mosi] ; ## H14 FMC_HPC1_LA07_N
|
||||
set_property -dict {PACKAGE_PIN AE3 IOSTANDARD LVCMOS18} [get_ports spi_miso] ; ## G12 FMC_HPC1_LA08_P
|
||||
|
||||
set_property -dict {PACKAGE_PIN T12 IOSTANDARD LVCMOS18} [get_ports ad9528_reset_b] ; ## D26 FMC_HPC1_LA26_P
|
||||
set_property -dict {PACKAGE_PIN R12 IOSTANDARD LVCMOS18} [get_ports ad9528_sysref_req] ; ## D27 FMC_HPC1_LA26_N
|
||||
set_property -dict {PACKAGE_PIN AG8 IOSTANDARD LVCMOS18} [get_ports ad9379_tx1_enable] ; ## D17 FMC_HPC1_LA13_P
|
||||
set_property -dict {PACKAGE_PIN AH7 IOSTANDARD LVCMOS18} [get_ports ad9379_tx2_enable] ; ## C18 FMC_HPC1_LA14_P
|
||||
set_property -dict {PACKAGE_PIN AH8 IOSTANDARD LVCMOS18} [get_ports ad9379_rx1_enable] ; ## D18 FMC_HPC1_LA13_N
|
||||
set_property -dict {PACKAGE_PIN AH6 IOSTANDARD LVCMOS18} [get_ports ad9379_rx2_enable] ; ## C19 FMC_HPC1_LA14_N
|
||||
set_property -dict {PACKAGE_PIN AE8 IOSTANDARD LVCMOS18} [get_ports ad9379_test] ; ## H16 FMC_HPC1_LA11_P
|
||||
#set_property -dict {PACKAGE_PIN AG3 IOSTANDARD LVCMOS18} [get_ports ad9379_test] ; ## D11 FMC_HPC1_LA05_P
|
||||
set_property -dict {PACKAGE_PIN AF2 IOSTANDARD LVCMOS18} [get_ports ad9379_reset_b] ; ## H10 FMC_HPC1_LA04_P
|
||||
set_property -dict {PACKAGE_PIN AF1 IOSTANDARD LVCMOS18} [get_ports ad9379_gpint] ; ## H11 FMC_HPC1_LA04_N
|
||||
set_property -dict {PACKAGE_PIN AG8 IOSTANDARD LVCMOS18} [get_ports adrv9009_tx1_enable] ; ## D17 FMC_HPC1_LA13_P
|
||||
set_property -dict {PACKAGE_PIN AH7 IOSTANDARD LVCMOS18} [get_ports adrv9009_tx2_enable] ; ## C18 FMC_HPC1_LA14_P
|
||||
set_property -dict {PACKAGE_PIN AH8 IOSTANDARD LVCMOS18} [get_ports adrv9009_rx1_enable] ; ## D18 FMC_HPC1_LA13_N
|
||||
set_property -dict {PACKAGE_PIN AH6 IOSTANDARD LVCMOS18} [get_ports adrv9009_rx2_enable] ; ## C19 FMC_HPC1_LA14_N
|
||||
set_property -dict {PACKAGE_PIN AE8 IOSTANDARD LVCMOS18} [get_ports adrv9009_test] ; ## H16 FMC_HPC1_LA11_P
|
||||
#set_property -dict {PACKAGE_PIN AG3 IOSTANDARD LVCMOS18} [get_ports adrv9009_test] ; ## D11 FMC_HPC1_LA05_P
|
||||
set_property -dict {PACKAGE_PIN AF2 IOSTANDARD LVCMOS18} [get_ports adrv9009_reset_b] ; ## H10 FMC_HPC1_LA04_P
|
||||
set_property -dict {PACKAGE_PIN AF1 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpint] ; ## H11 FMC_HPC1_LA04_N
|
||||
|
||||
set_property -dict {PACKAGE_PIN AD10 IOSTANDARD LVCMOS18} [get_ports ad9379_gpio_00] ; ## H19 FMC_HPC1_LA15_P
|
||||
set_property -dict {PACKAGE_PIN AE9 IOSTANDARD LVCMOS18} [get_ports ad9379_gpio_01] ; ## H20 FMC_HPC1_LA15_N
|
||||
set_property -dict {PACKAGE_PIN AG10 IOSTANDARD LVCMOS18} [get_ports ad9379_gpio_02] ; ## G18 FMC_HPC1_LA16_P
|
||||
set_property -dict {PACKAGE_PIN AG9 IOSTANDARD LVCMOS18} [get_ports ad9379_gpio_03] ; ## G19 FMC_HPC1_LA16_N
|
||||
set_property -dict {PACKAGE_PIN AC12 IOSTANDARD LVCMOS18} [get_ports ad9379_gpio_04] ; ## H25 FMC_HPC1_LA21_P
|
||||
set_property -dict {PACKAGE_PIN AC11 IOSTANDARD LVCMOS18} [get_ports ad9379_gpio_05] ; ## H26 FMC_HPC1_LA21_N
|
||||
set_property -dict {PACKAGE_PIN Y8 IOSTANDARD LVCMOS18} [get_ports ad9379_gpio_06] ; ## C22 FMC_HPC1_LA18_CC_P
|
||||
set_property -dict {PACKAGE_PIN Y7 IOSTANDARD LVCMOS18} [get_ports ad9379_gpio_07] ; ## C23 FMC_HPC1_LA18_CC_N
|
||||
set_property -dict {PACKAGE_PIN AG11 IOSTANDARD LVCMOS18} [get_ports ad9379_gpio_08] ; ## G25 FMC_HPC1_LA22_N (LVDS Pairs?)
|
||||
set_property -dict {PACKAGE_PIN AA11 IOSTANDARD LVCMOS18} [get_ports ad9379_gpio_09] ; ## H22 FMC_HPC1_LA19_P (LVDS Pairs?)
|
||||
set_property -dict {PACKAGE_PIN AA10 IOSTANDARD LVCMOS18} [get_ports ad9379_gpio_10] ; ## H23 FMC_HPC1_LA19_N (LVDS Pairs?)
|
||||
set_property -dict {PACKAGE_PIN AB11 IOSTANDARD LVCMOS18} [get_ports ad9379_gpio_11] ; ## G21 FMC_HPC1_LA20_P (LVDS Pairs?)
|
||||
set_property -dict {PACKAGE_PIN AB10 IOSTANDARD LVCMOS18} [get_ports ad9379_gpio_12] ; ## G22 FMC_HPC1_LA20_N (LVDS Pairs?)
|
||||
set_property -dict {PACKAGE_PIN AD6 IOSTANDARD LVCMOS18} [get_ports ad9379_gpio_13] ; ## G16 FMC_HPC1_LA12_N (LVDS Pairs?)
|
||||
set_property -dict {PACKAGE_PIN AD7 IOSTANDARD LVCMOS18} [get_ports ad9379_gpio_14] ; ## G15 FMC_HPC1_LA12_P (LVDS Pairs?)
|
||||
#set_property -dict {PACKAGE_PIN W11 IOSTANDARD LVCMOS18} [get_ports ad9379_gpio_13] ; ## G31 FMC_HPC1_LA29_N (LVDS Pairs?)
|
||||
#set_property -dict {PACKAGE_PIN W12 IOSTANDARD LVCMOS18} [get_ports ad9379_gpio_14] ; ## G30 FMC_HPC1_LA29_P (LVDS Pairs?)
|
||||
set_property -dict {PACKAGE_PIN AF11 IOSTANDARD LVCMOS18} [get_ports ad9379_gpio_15] ; ## G24 FMC_HPC1_LA22_P (LVDS Pairs?)
|
||||
set_property -dict {PACKAGE_PIN AJ2 IOSTANDARD LVCMOS18} [get_ports ad9379_gpio_16] ; ## C11 FMC_HPC1_LA06_N (LVDS Pairs?)
|
||||
set_property -dict {PACKAGE_PIN AH2 IOSTANDARD LVCMOS18} [get_ports ad9379_gpio_17] ; ## C10 FMC_HPC1_LA06_P (LVDS Pairs?)
|
||||
set_property -dict {PACKAGE_PIN AF8 IOSTANDARD LVCMOS18} [get_ports ad9379_gpio_18] ; ## H17 FMC_HPC1_LA11_N
|
||||
#set_property -dict {PACKAGE_PIN P9 IOSTANDARD LVCMOS18} [get_ports ad9379_gpio_16] ; ## G03 FMC_HPC1_CLK1_M2C_N (LVDS Pairs?)
|
||||
#set_property -dict {PACKAGE_PIN P10 IOSTANDARD LVCMOS18} [get_ports ad9379_gpio_17] ; ## G02 FMC_HPC1_CLK1_M2C_P (LVDS Pairs?)
|
||||
#set_property -dict {PACKAGE_PIN AH3 IOSTANDARD LVCMOS18} [get_ports ad9379_gpio_18] ; ## D12 FMC_HPC1_LA05_N
|
||||
set_property -dict {PACKAGE_PIN AD10 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_00] ; ## H19 FMC_HPC1_LA15_P
|
||||
set_property -dict {PACKAGE_PIN AE9 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_01] ; ## H20 FMC_HPC1_LA15_N
|
||||
set_property -dict {PACKAGE_PIN AG10 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_02] ; ## G18 FMC_HPC1_LA16_P
|
||||
set_property -dict {PACKAGE_PIN AG9 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_03] ; ## G19 FMC_HPC1_LA16_N
|
||||
set_property -dict {PACKAGE_PIN AC12 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_04] ; ## H25 FMC_HPC1_LA21_P
|
||||
set_property -dict {PACKAGE_PIN AC11 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_05] ; ## H26 FMC_HPC1_LA21_N
|
||||
set_property -dict {PACKAGE_PIN Y8 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_06] ; ## C22 FMC_HPC1_LA18_CC_P
|
||||
set_property -dict {PACKAGE_PIN Y7 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_07] ; ## C23 FMC_HPC1_LA18_CC_N
|
||||
set_property -dict {PACKAGE_PIN AG11 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_08] ; ## G25 FMC_HPC1_LA22_N (LVDS Pairs?)
|
||||
set_property -dict {PACKAGE_PIN AA11 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_09] ; ## H22 FMC_HPC1_LA19_P (LVDS Pairs?)
|
||||
set_property -dict {PACKAGE_PIN AA10 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_10] ; ## H23 FMC_HPC1_LA19_N (LVDS Pairs?)
|
||||
set_property -dict {PACKAGE_PIN AB11 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_11] ; ## G21 FMC_HPC1_LA20_P (LVDS Pairs?)
|
||||
set_property -dict {PACKAGE_PIN AB10 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_12] ; ## G22 FMC_HPC1_LA20_N (LVDS Pairs?)
|
||||
set_property -dict {PACKAGE_PIN AD6 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_13] ; ## G16 FMC_HPC1_LA12_N (LVDS Pairs?)
|
||||
set_property -dict {PACKAGE_PIN AD7 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_14] ; ## G15 FMC_HPC1_LA12_P (LVDS Pairs?)
|
||||
#set_property -dict {PACKAGE_PIN W11 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_13] ; ## G31 FMC_HPC1_LA29_N (LVDS Pairs?)
|
||||
#set_property -dict {PACKAGE_PIN W12 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_14] ; ## G30 FMC_HPC1_LA29_P (LVDS Pairs?)
|
||||
set_property -dict {PACKAGE_PIN AF11 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_15] ; ## G24 FMC_HPC1_LA22_P (LVDS Pairs?)
|
||||
set_property -dict {PACKAGE_PIN AJ2 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_16] ; ## C11 FMC_HPC1_LA06_N (LVDS Pairs?)
|
||||
set_property -dict {PACKAGE_PIN AH2 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_17] ; ## C10 FMC_HPC1_LA06_P (LVDS Pairs?)
|
||||
set_property -dict {PACKAGE_PIN AF8 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_18] ; ## H17 FMC_HPC1_LA11_N
|
||||
#set_property -dict {PACKAGE_PIN P9 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_16] ; ## G03 FMC_HPC1_CLK1_M2C_N (LVDS Pairs?)
|
||||
#set_property -dict {PACKAGE_PIN P10 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_17] ; ## G02 FMC_HPC1_CLK1_M2C_P (LVDS Pairs?)
|
||||
#set_property -dict {PACKAGE_PIN AH3 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_18] ; ## D12 FMC_HPC1_LA05_N
|
||||
|
||||
# clocks
|
||||
|
||||
create_clock -name tx_ref_clk -period 4.00 [get_ports ref_clk0_p]
|
||||
create_clock -name rx_ref_clk -period 4.00 [get_ports ref_clk1_p]
|
||||
create_clock -name tx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/util_ad9379_xcvr/inst/i_xch_0/i_gthe4_channel/TXOUTCLK]
|
||||
create_clock -name rx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/util_ad9379_xcvr/inst/i_xch_0/i_gthe4_channel/RXOUTCLK]
|
||||
create_clock -name rx_os_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/util_ad9379_xcvr/inst/i_xch_2/i_gthe4_channel/RXOUTCLK]
|
||||
create_clock -name tx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/util_adrv9009_xcvr/inst/i_xch_0/i_gthe4_channel/TXOUTCLK]
|
||||
create_clock -name rx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/util_adrv9009_xcvr/inst/i_xch_0/i_gthe4_channel/RXOUTCLK]
|
||||
create_clock -name rx_os_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/util_adrv9009_xcvr/inst/i_xch_2/i_gthe4_channel/RXOUTCLK]
|
||||
|
|
@ -3,12 +3,12 @@ source ../../scripts/adi_env.tcl
|
|||
source $ad_hdl_dir/projects/scripts/adi_project.tcl
|
||||
source $ad_hdl_dir/projects/scripts/adi_board.tcl
|
||||
|
||||
adi_project_xilinx adrv9379_zcu102
|
||||
adi_project_files adrv9379_zcu102 [list \
|
||||
adi_project_xilinx adrv9009_zcu102
|
||||
adi_project_files adrv9009_zcu102 [list \
|
||||
"system_top.v" \
|
||||
"system_constr.xdc"\
|
||||
"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
|
||||
"$ad_hdl_dir/projects/common/zcu102/zcu102_system_constr.xdc" ]
|
||||
|
||||
adi_project_run adrv9379_zcu102
|
||||
adi_project_run adrv9009_zcu102
|
||||
|
||||
|
|
@ -66,40 +66,40 @@ module system_top (
|
|||
output sysref_out_n,
|
||||
|
||||
output spi_csn_ad9528,
|
||||
output spi_csn_ad9379,
|
||||
output spi_csn_adrv9009,
|
||||
output spi_clk,
|
||||
output spi_mosi,
|
||||
input spi_miso,
|
||||
|
||||
inout ad9528_reset_b,
|
||||
inout ad9528_sysref_req,
|
||||
inout ad9379_tx1_enable,
|
||||
inout ad9379_tx2_enable,
|
||||
inout ad9379_rx1_enable,
|
||||
inout ad9379_rx2_enable,
|
||||
inout ad9379_test,
|
||||
inout ad9379_reset_b,
|
||||
inout ad9379_gpint,
|
||||
inout adrv9009_tx1_enable,
|
||||
inout adrv9009_tx2_enable,
|
||||
inout adrv9009_rx1_enable,
|
||||
inout adrv9009_rx2_enable,
|
||||
inout adrv9009_test,
|
||||
inout adrv9009_reset_b,
|
||||
inout adrv9009_gpint,
|
||||
|
||||
inout ad9379_gpio_00,
|
||||
inout ad9379_gpio_01,
|
||||
inout ad9379_gpio_02,
|
||||
inout ad9379_gpio_03,
|
||||
inout ad9379_gpio_04,
|
||||
inout ad9379_gpio_05,
|
||||
inout ad9379_gpio_06,
|
||||
inout ad9379_gpio_07,
|
||||
inout ad9379_gpio_15,
|
||||
inout ad9379_gpio_08,
|
||||
inout ad9379_gpio_09,
|
||||
inout ad9379_gpio_10,
|
||||
inout ad9379_gpio_11,
|
||||
inout ad9379_gpio_12,
|
||||
inout ad9379_gpio_14,
|
||||
inout ad9379_gpio_13,
|
||||
inout ad9379_gpio_17,
|
||||
inout ad9379_gpio_16,
|
||||
inout ad9379_gpio_18);
|
||||
inout adrv9009_gpio_00,
|
||||
inout adrv9009_gpio_01,
|
||||
inout adrv9009_gpio_02,
|
||||
inout adrv9009_gpio_03,
|
||||
inout adrv9009_gpio_04,
|
||||
inout adrv9009_gpio_05,
|
||||
inout adrv9009_gpio_06,
|
||||
inout adrv9009_gpio_07,
|
||||
inout adrv9009_gpio_15,
|
||||
inout adrv9009_gpio_08,
|
||||
inout adrv9009_gpio_09,
|
||||
inout adrv9009_gpio_10,
|
||||
inout adrv9009_gpio_11,
|
||||
inout adrv9009_gpio_12,
|
||||
inout adrv9009_gpio_14,
|
||||
inout adrv9009_gpio_13,
|
||||
inout adrv9009_gpio_17,
|
||||
inout adrv9009_gpio_16,
|
||||
inout adrv9009_gpio_18);
|
||||
|
||||
// internal signals
|
||||
|
||||
|
|
@ -172,32 +172,32 @@ module system_top (
|
|||
.dio_o ({gpio_i[59:32]}),
|
||||
.dio_p ({ ad9528_reset_b, // 59
|
||||
ad9528_sysref_req, // 58
|
||||
ad9379_tx1_enable, // 57
|
||||
ad9379_tx2_enable, // 56
|
||||
ad9379_rx1_enable, // 55
|
||||
ad9379_rx2_enable, // 54
|
||||
ad9379_test, // 53
|
||||
ad9379_reset_b, // 52
|
||||
ad9379_gpint, // 51
|
||||
ad9379_gpio_00, // 50
|
||||
ad9379_gpio_01, // 49
|
||||
ad9379_gpio_02, // 48
|
||||
ad9379_gpio_03, // 47
|
||||
ad9379_gpio_04, // 46
|
||||
ad9379_gpio_05, // 45
|
||||
ad9379_gpio_06, // 44
|
||||
ad9379_gpio_07, // 43
|
||||
ad9379_gpio_15, // 42
|
||||
ad9379_gpio_08, // 41
|
||||
ad9379_gpio_09, // 40
|
||||
ad9379_gpio_10, // 39
|
||||
ad9379_gpio_11, // 38
|
||||
ad9379_gpio_12, // 37
|
||||
ad9379_gpio_14, // 36
|
||||
ad9379_gpio_13, // 35
|
||||
ad9379_gpio_17, // 34
|
||||
ad9379_gpio_16, // 33
|
||||
ad9379_gpio_18})); // 32
|
||||
adrv9009_tx1_enable, // 57
|
||||
adrv9009_tx2_enable, // 56
|
||||
adrv9009_rx1_enable, // 55
|
||||
adrv9009_rx2_enable, // 54
|
||||
adrv9009_test, // 53
|
||||
adrv9009_reset_b, // 52
|
||||
adrv9009_gpint, // 51
|
||||
adrv9009_gpio_00, // 50
|
||||
adrv9009_gpio_01, // 49
|
||||
adrv9009_gpio_02, // 48
|
||||
adrv9009_gpio_03, // 47
|
||||
adrv9009_gpio_04, // 46
|
||||
adrv9009_gpio_05, // 45
|
||||
adrv9009_gpio_06, // 44
|
||||
adrv9009_gpio_07, // 43
|
||||
adrv9009_gpio_15, // 42
|
||||
adrv9009_gpio_08, // 41
|
||||
adrv9009_gpio_09, // 40
|
||||
adrv9009_gpio_10, // 39
|
||||
adrv9009_gpio_11, // 38
|
||||
adrv9009_gpio_12, // 37
|
||||
adrv9009_gpio_14, // 36
|
||||
adrv9009_gpio_13, // 35
|
||||
adrv9009_gpio_17, // 34
|
||||
adrv9009_gpio_16, // 33
|
||||
adrv9009_gpio_18})); // 32
|
||||
|
||||
ad_iobuf #(.DATA_WIDTH(21)) i_iobuf_bd (
|
||||
.dio_t (gpio_t[20:0]),
|
||||
|
|
@ -209,7 +209,7 @@ module system_top (
|
|||
assign gpio_bd_o = gpio_bd[ 7:0];
|
||||
|
||||
assign spi_csn_ad9528 = spi_csn[0];
|
||||
assign spi_csn_ad9379 = spi_csn[1];
|
||||
assign spi_csn_adrv9009 = spi_csn[1];
|
||||
|
||||
system_wrapper i_system_wrapper (
|
||||
.dac_fifo_bypass (gpio_o[60]),
|
||||
|
|
@ -1,286 +0,0 @@
|
|||
|
||||
source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl
|
||||
|
||||
# ad9379
|
||||
|
||||
create_bd_port -dir I dac_fifo_bypass
|
||||
|
||||
# dac peripherals
|
||||
|
||||
ad_ip_instance axi_clkgen axi_ad9379_tx_clkgen
|
||||
ad_ip_parameter axi_ad9379_tx_clkgen CONFIG.ID 2
|
||||
ad_ip_parameter axi_ad9379_tx_clkgen CONFIG.CLKIN_PERIOD 4
|
||||
ad_ip_parameter axi_ad9379_tx_clkgen CONFIG.VCO_DIV 1
|
||||
ad_ip_parameter axi_ad9379_tx_clkgen CONFIG.VCO_MUL 4
|
||||
ad_ip_parameter axi_ad9379_tx_clkgen CONFIG.CLK0_DIV 4
|
||||
|
||||
ad_ip_instance axi_adxcvr axi_ad9379_tx_xcvr
|
||||
ad_ip_parameter axi_ad9379_tx_xcvr CONFIG.NUM_OF_LANES 4
|
||||
ad_ip_parameter axi_ad9379_tx_xcvr CONFIG.QPLL_ENABLE 1
|
||||
ad_ip_parameter axi_ad9379_tx_xcvr CONFIG.TX_OR_RX_N 1
|
||||
|
||||
adi_axi_jesd204_tx_create axi_ad9379_tx_jesd 4
|
||||
|
||||
ad_ip_instance util_upack util_ad9379_tx_upack
|
||||
ad_ip_parameter util_ad9379_tx_upack CONFIG.CHANNEL_DATA_WIDTH 32
|
||||
ad_ip_parameter util_ad9379_tx_upack CONFIG.NUM_OF_CHANNELS 4
|
||||
|
||||
ad_ip_instance axi_dmac axi_ad9379_tx_dma
|
||||
ad_ip_parameter axi_ad9379_tx_dma CONFIG.DMA_TYPE_SRC 0
|
||||
ad_ip_parameter axi_ad9379_tx_dma CONFIG.DMA_TYPE_DEST 1
|
||||
ad_ip_parameter axi_ad9379_tx_dma CONFIG.CYCLIC 1
|
||||
ad_ip_parameter axi_ad9379_tx_dma CONFIG.AXI_SLICE_SRC 0
|
||||
ad_ip_parameter axi_ad9379_tx_dma CONFIG.AXI_SLICE_DEST 1
|
||||
ad_ip_parameter axi_ad9379_tx_dma CONFIG.ASYNC_CLK_DEST_REQ 1
|
||||
ad_ip_parameter axi_ad9379_tx_dma CONFIG.ASYNC_CLK_SRC_DEST 1
|
||||
ad_ip_parameter axi_ad9379_tx_dma CONFIG.ASYNC_CLK_REQ_SRC 1
|
||||
ad_ip_parameter axi_ad9379_tx_dma CONFIG.DMA_2D_TRANSFER 0
|
||||
ad_ip_parameter axi_ad9379_tx_dma CONFIG.DMA_DATA_WIDTH_DEST 128
|
||||
|
||||
# adc peripherals
|
||||
|
||||
ad_ip_instance axi_clkgen axi_ad9379_rx_clkgen
|
||||
ad_ip_parameter axi_ad9379_rx_clkgen CONFIG.ID 2
|
||||
ad_ip_parameter axi_ad9379_rx_clkgen CONFIG.CLKIN_PERIOD 4
|
||||
ad_ip_parameter axi_ad9379_rx_clkgen CONFIG.VCO_DIV 1
|
||||
ad_ip_parameter axi_ad9379_rx_clkgen CONFIG.VCO_MUL 4
|
||||
ad_ip_parameter axi_ad9379_rx_clkgen CONFIG.CLK0_DIV 4
|
||||
|
||||
ad_ip_instance axi_adxcvr axi_ad9379_rx_xcvr
|
||||
ad_ip_parameter axi_ad9379_rx_xcvr CONFIG.NUM_OF_LANES 2
|
||||
ad_ip_parameter axi_ad9379_rx_xcvr CONFIG.QPLL_ENABLE 0
|
||||
ad_ip_parameter axi_ad9379_rx_xcvr CONFIG.TX_OR_RX_N 0
|
||||
|
||||
adi_axi_jesd204_rx_create axi_ad9379_rx_jesd 2
|
||||
|
||||
ad_ip_instance util_cpack util_ad9379_rx_cpack
|
||||
ad_ip_parameter util_ad9379_rx_cpack CONFIG.CHANNEL_DATA_WIDTH 16
|
||||
ad_ip_parameter util_ad9379_rx_cpack CONFIG.NUM_OF_CHANNELS 4
|
||||
|
||||
ad_ip_instance axi_dmac axi_ad9379_rx_dma
|
||||
ad_ip_parameter axi_ad9379_rx_dma CONFIG.DMA_TYPE_SRC 2
|
||||
ad_ip_parameter axi_ad9379_rx_dma CONFIG.DMA_TYPE_DEST 0
|
||||
ad_ip_parameter axi_ad9379_rx_dma CONFIG.CYCLIC 0
|
||||
ad_ip_parameter axi_ad9379_rx_dma CONFIG.SYNC_TRANSFER_START 1
|
||||
ad_ip_parameter axi_ad9379_rx_dma CONFIG.AXI_SLICE_SRC 0
|
||||
ad_ip_parameter axi_ad9379_rx_dma CONFIG.AXI_SLICE_DEST 0
|
||||
ad_ip_parameter axi_ad9379_rx_dma CONFIG.ASYNC_CLK_DEST_REQ 1
|
||||
ad_ip_parameter axi_ad9379_rx_dma CONFIG.ASYNC_CLK_SRC_DEST 1
|
||||
ad_ip_parameter axi_ad9379_rx_dma CONFIG.ASYNC_CLK_REQ_SRC 1
|
||||
ad_ip_parameter axi_ad9379_rx_dma CONFIG.DMA_2D_TRANSFER 0
|
||||
ad_ip_parameter axi_ad9379_rx_dma CONFIG.DMA_DATA_WIDTH_SRC 64
|
||||
|
||||
# adc-os peripherals
|
||||
|
||||
ad_ip_instance axi_clkgen axi_ad9379_rx_os_clkgen
|
||||
ad_ip_parameter axi_ad9379_rx_os_clkgen CONFIG.ID 2
|
||||
ad_ip_parameter axi_ad9379_rx_os_clkgen CONFIG.CLKIN_PERIOD 4
|
||||
ad_ip_parameter axi_ad9379_rx_os_clkgen CONFIG.VCO_DIV 1
|
||||
ad_ip_parameter axi_ad9379_rx_os_clkgen CONFIG.VCO_MUL 4
|
||||
ad_ip_parameter axi_ad9379_rx_os_clkgen CONFIG.CLK0_DIV 4
|
||||
|
||||
ad_ip_instance axi_adxcvr axi_ad9379_rx_os_xcvr
|
||||
ad_ip_parameter axi_ad9379_rx_os_xcvr CONFIG.NUM_OF_LANES 2
|
||||
ad_ip_parameter axi_ad9379_rx_os_xcvr CONFIG.QPLL_ENABLE 0
|
||||
ad_ip_parameter axi_ad9379_rx_os_xcvr CONFIG.TX_OR_RX_N 0
|
||||
|
||||
adi_axi_jesd204_rx_create axi_ad9379_rx_os_jesd 2
|
||||
|
||||
ad_ip_instance util_cpack util_ad9379_rx_os_cpack
|
||||
ad_ip_parameter util_ad9379_rx_os_cpack CONFIG.CHANNEL_DATA_WIDTH 32
|
||||
ad_ip_parameter util_ad9379_rx_os_cpack CONFIG.NUM_OF_CHANNELS 2
|
||||
|
||||
ad_ip_instance axi_dmac axi_ad9379_rx_os_dma
|
||||
ad_ip_parameter axi_ad9379_rx_os_dma CONFIG.DMA_TYPE_SRC 2
|
||||
ad_ip_parameter axi_ad9379_rx_os_dma CONFIG.DMA_TYPE_DEST 0
|
||||
ad_ip_parameter axi_ad9379_rx_os_dma CONFIG.CYCLIC 0
|
||||
ad_ip_parameter axi_ad9379_rx_os_dma CONFIG.SYNC_TRANSFER_START 1
|
||||
ad_ip_parameter axi_ad9379_rx_os_dma CONFIG.AXI_SLICE_SRC 0
|
||||
ad_ip_parameter axi_ad9379_rx_os_dma CONFIG.AXI_SLICE_DEST 0
|
||||
ad_ip_parameter axi_ad9379_rx_os_dma CONFIG.ASYNC_CLK_DEST_REQ 1
|
||||
ad_ip_parameter axi_ad9379_rx_os_dma CONFIG.ASYNC_CLK_SRC_DEST 1
|
||||
ad_ip_parameter axi_ad9379_rx_os_dma CONFIG.ASYNC_CLK_REQ_SRC 1
|
||||
ad_ip_parameter axi_ad9379_rx_os_dma CONFIG.DMA_2D_TRANSFER 0
|
||||
ad_ip_parameter axi_ad9379_rx_os_dma CONFIG.DMA_DATA_WIDTH_SRC 64
|
||||
|
||||
# common cores
|
||||
|
||||
ad_ip_instance axi_ad9379 axi_ad9379_core
|
||||
|
||||
ad_ip_instance util_adxcvr util_ad9379_xcvr
|
||||
ad_ip_parameter util_ad9379_xcvr CONFIG.RX_NUM_OF_LANES 4
|
||||
ad_ip_parameter util_ad9379_xcvr CONFIG.TX_NUM_OF_LANES 4
|
||||
ad_ip_parameter util_ad9379_xcvr CONFIG.TX_OUT_DIV 1
|
||||
ad_ip_parameter util_ad9379_xcvr CONFIG.CPLL_FBDIV 4
|
||||
ad_ip_parameter util_ad9379_xcvr CONFIG.RX_CLK25_DIV 10
|
||||
ad_ip_parameter util_ad9379_xcvr CONFIG.TX_CLK25_DIV 10
|
||||
ad_ip_parameter util_ad9379_xcvr CONFIG.RX_PMA_CFG 0x001E7080
|
||||
ad_ip_parameter util_ad9379_xcvr CONFIG.RX_CDR_CFG 0x0b000023ff10400020
|
||||
ad_ip_parameter util_ad9379_xcvr CONFIG.QPLL_FBDIV 0x080
|
||||
|
||||
# xcvr interfaces
|
||||
|
||||
create_bd_port -dir I tx_ref_clk_0
|
||||
create_bd_port -dir I rx_ref_clk_0
|
||||
create_bd_port -dir I rx_ref_clk_2
|
||||
|
||||
ad_xcvrpll tx_ref_clk_0 util_ad9379_xcvr/qpll_ref_clk_0
|
||||
ad_xcvrpll rx_ref_clk_0 util_ad9379_xcvr/cpll_ref_clk_0
|
||||
ad_xcvrpll rx_ref_clk_0 util_ad9379_xcvr/cpll_ref_clk_1
|
||||
ad_xcvrpll rx_ref_clk_2 util_ad9379_xcvr/cpll_ref_clk_2
|
||||
ad_xcvrpll rx_ref_clk_2 util_ad9379_xcvr/cpll_ref_clk_3
|
||||
ad_xcvrpll axi_ad9379_tx_xcvr/up_pll_rst util_ad9379_xcvr/up_qpll_rst_0
|
||||
ad_xcvrpll axi_ad9379_rx_xcvr/up_pll_rst util_ad9379_xcvr/up_cpll_rst_0
|
||||
ad_xcvrpll axi_ad9379_rx_xcvr/up_pll_rst util_ad9379_xcvr/up_cpll_rst_1
|
||||
ad_xcvrpll axi_ad9379_rx_os_xcvr/up_pll_rst util_ad9379_xcvr/up_cpll_rst_2
|
||||
ad_xcvrpll axi_ad9379_rx_os_xcvr/up_pll_rst util_ad9379_xcvr/up_cpll_rst_3
|
||||
ad_connect sys_cpu_resetn util_ad9379_xcvr/up_rstn
|
||||
ad_connect sys_cpu_clk util_ad9379_xcvr/up_clk
|
||||
|
||||
ad_xcvrcon util_ad9379_xcvr axi_ad9379_tx_xcvr axi_ad9379_tx_jesd {0 3 2 1}
|
||||
ad_reconct util_ad9379_xcvr/tx_out_clk_0 axi_ad9379_tx_clkgen/clk
|
||||
ad_connect axi_ad9379_tx_clkgen/clk_0 util_ad9379_xcvr/tx_clk_0
|
||||
ad_connect axi_ad9379_tx_clkgen/clk_0 util_ad9379_xcvr/tx_clk_1
|
||||
ad_connect axi_ad9379_tx_clkgen/clk_0 util_ad9379_xcvr/tx_clk_2
|
||||
ad_connect axi_ad9379_tx_clkgen/clk_0 util_ad9379_xcvr/tx_clk_3
|
||||
ad_connect axi_ad9379_tx_clkgen/clk_0 axi_ad9379_tx_jesd/device_clk
|
||||
ad_connect axi_ad9379_tx_clkgen/clk_0 axi_ad9379_tx_jesd_rstgen/slowest_sync_clk
|
||||
ad_xcvrcon util_ad9379_xcvr axi_ad9379_rx_xcvr axi_ad9379_rx_jesd
|
||||
ad_reconct util_ad9379_xcvr/rx_out_clk_0 axi_ad9379_rx_clkgen/clk
|
||||
ad_connect axi_ad9379_rx_clkgen/clk_0 util_ad9379_xcvr/rx_clk_0
|
||||
ad_connect axi_ad9379_rx_clkgen/clk_0 util_ad9379_xcvr/rx_clk_1
|
||||
ad_connect axi_ad9379_rx_clkgen/clk_0 axi_ad9379_rx_jesd/device_clk
|
||||
ad_connect axi_ad9379_rx_clkgen/clk_0 axi_ad9379_rx_jesd_rstgen/slowest_sync_clk
|
||||
ad_xcvrcon util_ad9379_xcvr axi_ad9379_rx_os_xcvr axi_ad9379_rx_os_jesd
|
||||
ad_reconct util_ad9379_xcvr/rx_out_clk_2 axi_ad9379_rx_os_clkgen/clk
|
||||
ad_connect axi_ad9379_rx_os_clkgen/clk_0 util_ad9379_xcvr/rx_clk_2
|
||||
ad_connect axi_ad9379_rx_os_clkgen/clk_0 util_ad9379_xcvr/rx_clk_3
|
||||
ad_connect axi_ad9379_rx_os_clkgen/clk_0 axi_ad9379_rx_os_jesd/device_clk
|
||||
ad_connect axi_ad9379_rx_os_clkgen/clk_0 axi_ad9379_rx_os_jesd_rstgen/slowest_sync_clk
|
||||
|
||||
# dma clock & reset
|
||||
|
||||
ad_ip_instance proc_sys_reset sys_dma_rstgen
|
||||
ad_ip_parameter sys_dma_rstgen CONFIG.C_EXT_RST_WIDTH 1
|
||||
|
||||
ad_connect sys_dma_clk sys_dma_rstgen/slowest_sync_clk
|
||||
ad_connect sys_dma_resetn sys_dma_rstgen/peripheral_aresetn
|
||||
ad_connect sys_dma_reset sys_dma_rstgen/peripheral_reset
|
||||
ad_connect sys_dma_reset axi_ad9379_dacfifo/dma_rst
|
||||
|
||||
# connections (dac)
|
||||
|
||||
ad_connect axi_ad9379_tx_clkgen/clk_0 axi_ad9379_core/dac_clk
|
||||
ad_connect axi_ad9379_tx_jesd/tx_data_tdata axi_ad9379_core/dac_tx_data
|
||||
ad_connect axi_ad9379_tx_clkgen/clk_0 util_ad9379_tx_upack/dac_clk
|
||||
ad_connect axi_ad9379_core/dac_valid_i0 util_ad9379_tx_upack/dac_valid_0
|
||||
ad_connect axi_ad9379_core/dac_enable_i0 util_ad9379_tx_upack/dac_enable_0
|
||||
ad_connect axi_ad9379_core/dac_data_i0 util_ad9379_tx_upack/dac_data_0
|
||||
ad_connect axi_ad9379_core/dac_valid_q0 util_ad9379_tx_upack/dac_valid_1
|
||||
ad_connect axi_ad9379_core/dac_enable_q0 util_ad9379_tx_upack/dac_enable_1
|
||||
ad_connect axi_ad9379_core/dac_data_q0 util_ad9379_tx_upack/dac_data_1
|
||||
ad_connect axi_ad9379_core/dac_valid_i1 util_ad9379_tx_upack/dac_valid_2
|
||||
ad_connect axi_ad9379_core/dac_enable_i1 util_ad9379_tx_upack/dac_enable_2
|
||||
ad_connect axi_ad9379_core/dac_data_i1 util_ad9379_tx_upack/dac_data_2
|
||||
ad_connect axi_ad9379_core/dac_valid_q1 util_ad9379_tx_upack/dac_valid_3
|
||||
ad_connect axi_ad9379_core/dac_enable_q1 util_ad9379_tx_upack/dac_enable_3
|
||||
ad_connect axi_ad9379_core/dac_data_q1 util_ad9379_tx_upack/dac_data_3
|
||||
ad_connect axi_ad9379_tx_clkgen/clk_0 axi_ad9379_dacfifo/dac_clk
|
||||
ad_connect axi_ad9379_tx_jesd_rstgen/peripheral_reset axi_ad9379_dacfifo/dac_rst
|
||||
ad_connect util_ad9379_tx_upack/dac_valid axi_ad9379_dacfifo/dac_valid
|
||||
ad_connect util_ad9379_tx_upack/dac_data axi_ad9379_dacfifo/dac_data
|
||||
ad_connect sys_dma_clk axi_ad9379_dacfifo/dma_clk
|
||||
ad_connect sys_dma_clk axi_ad9379_tx_dma/m_axis_aclk
|
||||
ad_connect axi_ad9379_dacfifo/dma_valid axi_ad9379_tx_dma/m_axis_valid
|
||||
ad_connect axi_ad9379_dacfifo/dma_data axi_ad9379_tx_dma/m_axis_data
|
||||
ad_connect axi_ad9379_dacfifo/dma_ready axi_ad9379_tx_dma/m_axis_ready
|
||||
ad_connect axi_ad9379_dacfifo/dma_xfer_req axi_ad9379_tx_dma/m_axis_xfer_req
|
||||
ad_connect axi_ad9379_dacfifo/dma_xfer_last axi_ad9379_tx_dma/m_axis_last
|
||||
ad_connect axi_ad9379_dacfifo/dac_dunf axi_ad9379_core/dac_dunf
|
||||
ad_connect axi_ad9379_dacfifo/bypass dac_fifo_bypass
|
||||
ad_connect sys_dma_resetn axi_ad9379_tx_dma/m_src_axi_aresetn
|
||||
|
||||
# connections (adc)
|
||||
|
||||
ad_connect axi_ad9379_rx_clkgen/clk_0 axi_ad9379_core/adc_clk
|
||||
ad_connect axi_ad9379_rx_jesd/rx_sof axi_ad9379_core/adc_rx_sof
|
||||
ad_connect axi_ad9379_rx_jesd/rx_data_tdata axi_ad9379_core/adc_rx_data
|
||||
ad_connect axi_ad9379_rx_clkgen/clk_0 util_ad9379_rx_cpack/adc_clk
|
||||
ad_connect axi_ad9379_rx_jesd_rstgen/peripheral_reset util_ad9379_rx_cpack/adc_rst
|
||||
ad_connect axi_ad9379_core/adc_enable_i0 util_ad9379_rx_cpack/adc_enable_0
|
||||
ad_connect axi_ad9379_core/adc_valid_i0 util_ad9379_rx_cpack/adc_valid_0
|
||||
ad_connect axi_ad9379_core/adc_data_i0 util_ad9379_rx_cpack/adc_data_0
|
||||
ad_connect axi_ad9379_core/adc_enable_q0 util_ad9379_rx_cpack/adc_enable_1
|
||||
ad_connect axi_ad9379_core/adc_valid_q0 util_ad9379_rx_cpack/adc_valid_1
|
||||
ad_connect axi_ad9379_core/adc_data_q0 util_ad9379_rx_cpack/adc_data_1
|
||||
ad_connect axi_ad9379_core/adc_enable_i1 util_ad9379_rx_cpack/adc_enable_2
|
||||
ad_connect axi_ad9379_core/adc_valid_i1 util_ad9379_rx_cpack/adc_valid_2
|
||||
ad_connect axi_ad9379_core/adc_data_i1 util_ad9379_rx_cpack/adc_data_2
|
||||
ad_connect axi_ad9379_core/adc_enable_q1 util_ad9379_rx_cpack/adc_enable_3
|
||||
ad_connect axi_ad9379_core/adc_valid_q1 util_ad9379_rx_cpack/adc_valid_3
|
||||
ad_connect axi_ad9379_core/adc_data_q1 util_ad9379_rx_cpack/adc_data_3
|
||||
ad_connect axi_ad9379_rx_clkgen/clk_0 axi_ad9379_rx_dma/fifo_wr_clk
|
||||
ad_connect util_ad9379_rx_cpack/adc_valid axi_ad9379_rx_dma/fifo_wr_en
|
||||
ad_connect util_ad9379_rx_cpack/adc_sync axi_ad9379_rx_dma/fifo_wr_sync
|
||||
ad_connect util_ad9379_rx_cpack/adc_data axi_ad9379_rx_dma/fifo_wr_din
|
||||
ad_connect axi_ad9379_rx_dma/fifo_wr_overflow axi_ad9379_core/adc_dovf
|
||||
ad_connect sys_dma_resetn axi_ad9379_rx_dma/m_dest_axi_aresetn
|
||||
|
||||
# connections (adc-os)
|
||||
|
||||
ad_connect axi_ad9379_rx_os_clkgen/clk_0 axi_ad9379_core/adc_os_clk
|
||||
ad_connect axi_ad9379_rx_os_jesd/rx_sof axi_ad9379_core/adc_rx_os_sof
|
||||
ad_connect axi_ad9379_rx_os_jesd/rx_data_tdata axi_ad9379_core/adc_rx_os_data
|
||||
ad_connect axi_ad9379_rx_os_clkgen/clk_0 util_ad9379_rx_os_cpack/adc_clk
|
||||
ad_connect axi_ad9379_rx_os_jesd_rstgen/peripheral_reset util_ad9379_rx_os_cpack/adc_rst
|
||||
ad_connect axi_ad9379_core/adc_os_enable_i0 util_ad9379_rx_os_cpack/adc_enable_0
|
||||
ad_connect axi_ad9379_core/adc_os_valid_i0 util_ad9379_rx_os_cpack/adc_valid_0
|
||||
ad_connect axi_ad9379_core/adc_os_data_i0 util_ad9379_rx_os_cpack/adc_data_0
|
||||
ad_connect axi_ad9379_core/adc_os_enable_q0 util_ad9379_rx_os_cpack/adc_enable_1
|
||||
ad_connect axi_ad9379_core/adc_os_valid_q0 util_ad9379_rx_os_cpack/adc_valid_1
|
||||
ad_connect axi_ad9379_core/adc_os_data_q0 util_ad9379_rx_os_cpack/adc_data_1
|
||||
ad_connect axi_ad9379_rx_os_clkgen/clk_0 axi_ad9379_rx_os_dma/fifo_wr_clk
|
||||
ad_connect util_ad9379_rx_os_cpack/adc_valid axi_ad9379_rx_os_dma/fifo_wr_en
|
||||
ad_connect util_ad9379_rx_os_cpack/adc_sync axi_ad9379_rx_os_dma/fifo_wr_sync
|
||||
ad_connect util_ad9379_rx_os_cpack/adc_data axi_ad9379_rx_os_dma/fifo_wr_din
|
||||
ad_connect axi_ad9379_rx_os_dma/fifo_wr_overflow axi_ad9379_core/adc_os_dovf
|
||||
ad_connect sys_dma_resetn axi_ad9379_rx_os_dma/m_dest_axi_aresetn
|
||||
|
||||
# interconnect (cpu)
|
||||
|
||||
ad_cpu_interconnect 0x44A00000 axi_ad9379_core
|
||||
ad_cpu_interconnect 0x44A80000 axi_ad9379_tx_xcvr
|
||||
ad_cpu_interconnect 0x43C00000 axi_ad9379_tx_clkgen
|
||||
ad_cpu_interconnect 0x44A90000 axi_ad9379_tx_jesd
|
||||
ad_cpu_interconnect 0x7c420000 axi_ad9379_tx_dma
|
||||
ad_cpu_interconnect 0x44A60000 axi_ad9379_rx_xcvr
|
||||
ad_cpu_interconnect 0x43C10000 axi_ad9379_rx_clkgen
|
||||
ad_cpu_interconnect 0x44AA0000 axi_ad9379_rx_jesd
|
||||
ad_cpu_interconnect 0x7c400000 axi_ad9379_rx_dma
|
||||
ad_cpu_interconnect 0x44A50000 axi_ad9379_rx_os_xcvr
|
||||
ad_cpu_interconnect 0x43C20000 axi_ad9379_rx_os_clkgen
|
||||
ad_cpu_interconnect 0x44AB0000 axi_ad9379_rx_os_jesd
|
||||
ad_cpu_interconnect 0x7c440000 axi_ad9379_rx_os_dma
|
||||
|
||||
# gt uses hp3, and 100MHz clock for both DRP and AXI4
|
||||
|
||||
ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3
|
||||
ad_mem_hp3_interconnect sys_cpu_clk axi_ad9379_rx_xcvr/m_axi
|
||||
ad_mem_hp3_interconnect sys_cpu_clk axi_ad9379_rx_os_xcvr/m_axi
|
||||
|
||||
# interconnect (mem/dac)
|
||||
|
||||
ad_mem_hp1_interconnect sys_dma_clk sys_ps7/S_AXI_HP1
|
||||
ad_mem_hp1_interconnect sys_dma_clk axi_ad9379_tx_dma/m_src_axi
|
||||
ad_mem_hp2_interconnect sys_dma_clk sys_ps7/S_AXI_HP2
|
||||
ad_mem_hp2_interconnect sys_dma_clk axi_ad9379_rx_dma/m_dest_axi
|
||||
ad_mem_hp2_interconnect sys_dma_clk axi_ad9379_rx_os_dma/m_dest_axi
|
||||
|
||||
# interrupts
|
||||
|
||||
ad_cpu_interrupt ps-8 mb-8 axi_ad9379_rx_os_jesd/irq
|
||||
ad_cpu_interrupt ps-9 mb-7 axi_ad9379_tx_jesd/irq
|
||||
ad_cpu_interrupt ps-10 mb-15 axi_ad9379_rx_jesd/irq
|
||||
ad_cpu_interrupt ps-11 mb-14 axi_ad9379_rx_os_dma/irq
|
||||
ad_cpu_interrupt ps-12 mb-13- axi_ad9379_tx_dma/irq
|
||||
ad_cpu_interrupt ps-13 mb-12 axi_ad9379_rx_dma/irq
|
||||
|
|
@ -1,29 +0,0 @@
|
|||
|
||||
set dac_fifo_name axi_ad9379_dacfifo
|
||||
set dac_fifo_address_width 10
|
||||
set dac_data_width 128
|
||||
set dac_dma_data_width 128
|
||||
|
||||
source $ad_hdl_dir/projects/common/zcu102/zcu102_system_bd.tcl
|
||||
source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl
|
||||
|
||||
ad_ip_parameter sys_ps8 CONFIG.PSU__FPGA_PL2_ENABLE 1
|
||||
ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL2_REF_CTRL__SRCSEL {IOPLL}
|
||||
ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ 200
|
||||
|
||||
source ../common/adrv9379_bd.tcl
|
||||
|
||||
ad_connect sys_dma_clk sys_ps8/pl_clk2
|
||||
ad_connect sys_dma_rstgen/ext_reset_in sys_rstgen/peripheral_reset
|
||||
|
||||
ad_ip_parameter axi_ad9379_tx_xcvr CONFIG.XCVR_TYPE 2
|
||||
ad_ip_parameter axi_ad9379_rx_xcvr CONFIG.XCVR_TYPE 2
|
||||
ad_ip_parameter axi_ad9379_rx_os_xcvr CONFIG.XCVR_TYPE 2
|
||||
|
||||
ad_ip_parameter util_ad9379_xcvr CONFIG.XCVR_TYPE 2
|
||||
ad_ip_parameter util_ad9379_xcvr CONFIG.QPLL_FBDIV 80
|
||||
ad_ip_parameter util_ad9379_xcvr CONFIG.QPLL_REFCLK_DIV 1
|
||||
|
||||
ad_ip_parameter axi_ad9379_rx_clkgen CONFIG.DEVICE_TYPE 2
|
||||
ad_ip_parameter axi_ad9379_tx_clkgen CONFIG.DEVICE_TYPE 2
|
||||
|
||||
Loading…
Reference in New Issue