a5soc- remove hdmi core
Rejeesh Kutty
parent
0c5958091e
commit
e488ba0287
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@ -39,10 +39,6 @@
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module system_top (
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// clock and resets
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sys_clk,
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// hps
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ddr3_a,
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@ -104,17 +100,12 @@ module system_top (
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// board gpio
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led,
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push_buttons,
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dip_switches,
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gpio_bd,
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// hdmi
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// i2c
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hdmi_out_clk,
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hdmi_data,
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hdmi_scl,
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hdmi_sda,
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hdmi_rstn,
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fmc_a_scl,
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fmc_a_sda,
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// lane interface
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@ -129,10 +120,6 @@ module system_top (
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spi_clk,
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spi_sdio);
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// clock and resets
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input sys_clk;
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// hps
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output [ 14:0] ddr3_a;
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@ -194,17 +181,12 @@ module system_top (
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// board gpio
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output [ 3:0] led;
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input [ 3:0] push_buttons;
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input [ 3:0] dip_switches;
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inout [ 11:0] gpio_bd;
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// hdmi
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// i2c
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output hdmi_out_clk;
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output [ 15:0] hdmi_data;
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inout hdmi_scl;
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inout hdmi_sda;
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output hdmi_rstn;
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inout fmc_a_scl;
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inout fmc_a_sda;
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// lane interface
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@ -219,137 +201,22 @@ module system_top (
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output spi_clk;
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inout spi_sdio;
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// internal registers
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reg rx_sysref_m1 = 'd0;
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reg rx_sysref_m2 = 'd0;
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reg rx_sysref_m3 = 'd0;
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reg rx_sysref = 'd0;
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reg dma0_wr = 'd0;
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reg [ 63:0] dma0_wdata = 'd0;
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reg dma1_wr = 'd0;
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reg [ 63:0] dma1_wdata = 'd0;
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// internal clocks and resets
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wire sys_resetn;
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wire rx_clk;
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wire adc0_clk;
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wire adc1_clk;
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// internal signals
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wire [ 63:0] gpio_i;
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wire [ 63:0] gpio_o;
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wire spi_mosi;
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wire spi_miso;
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wire hdmi_scl_oe;
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wire hdmi_sda_oe;
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wire adc0_enable_a_s;
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wire [ 31:0] adc0_data_a_s;
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wire adc0_enable_b_s;
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wire [ 31:0] adc0_data_b_s;
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wire adc0_dovf_s;
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wire adc1_enable_a_s;
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wire [ 31:0] adc1_data_a_s;
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wire adc1_enable_b_s;
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wire [ 31:0] adc1_data_b_s;
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wire adc1_dovf_s;
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wire [ 3:0] rx_ip_sof_s;
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wire [127:0] rx_ip_data_s;
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wire [127:0] rx_data_s;
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wire rx_sw_rstn_s;
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wire rx_sysref_s;
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wire rx_err_s;
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wire rx_ready_s;
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wire [ 3:0] rx_rst_state_s;
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wire rx_lane_aligned_s;
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wire [ 3:0] rx_analog_reset_s;
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wire [ 3:0] rx_digital_reset_s;
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wire [ 3:0] rx_cdr_locked_s;
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wire [ 3:0] rx_cal_busy_s;
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wire rx_pll_locked_s;
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wire [ 15:0] rx_xcvr_status_s;
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wire fmc_a_scl_oe;
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wire fmc_a_sda_oe;
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// i2c
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assign fmc_a_scl = (fmc_a_scl_oe == 1'b1) ? 1'b0 : 1'bz;
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assign fmc_a_sda = (fmc_a_sda_oe == 1'b1) ? 1'b0 : 1'bz;
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// instantiations
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always @(posedge rx_clk) begin
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rx_sysref_m1 <= rx_sysref_s;
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rx_sysref_m2 <= rx_sysref_m1;
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rx_sysref_m3 <= rx_sysref_m2;
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rx_sysref <= rx_sysref_m2 & ~rx_sysref_m3;
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end
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always @(posedge rx_clk) begin
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dma0_wr <= adc0_enable_a_s & adc0_enable_b_s;
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dma0_wdata <= { adc0_data_b_s[31:16],
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adc0_data_a_s[31:16],
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adc0_data_b_s[15: 0],
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adc0_data_a_s[15: 0]};
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dma1_wr <= adc1_enable_a_s & adc1_enable_b_s;
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dma1_wdata <= { adc1_data_b_s[31:16],
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adc1_data_a_s[31:16],
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adc1_data_b_s[15: 0],
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adc1_data_a_s[15: 0]};
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end
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sld_signaltap #(
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.sld_advanced_trigger_entity ("basic,1,"),
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.sld_data_bits (130),
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.sld_data_bit_cntr_bits (8),
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.sld_enable_advanced_trigger (0),
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.sld_mem_address_bits (10),
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.sld_node_crc_bits (32),
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.sld_node_crc_hiword (10311),
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.sld_node_crc_loword (14297),
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.sld_node_info (1076736),
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.sld_ram_block_type ("AUTO"),
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.sld_sample_depth (1024),
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.sld_storage_qualifier_gap_record (0),
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.sld_storage_qualifier_mode ("OFF"),
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.sld_trigger_bits (2),
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.sld_trigger_in_enabled (0),
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.sld_trigger_level (1),
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.sld_trigger_level_pipeline (1))
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i_signaltap (
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.acq_clk (rx_clk),
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.acq_data_in ({ rx_sysref,
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rx_sync,
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adc1_data_b_s,
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adc1_data_a_s,
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adc0_data_b_s,
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adc0_data_a_s}),
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.acq_trigger_in ({rx_sysref, rx_sync}));
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genvar n;
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generate
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for (n = 0; n < 4; n = n + 1) begin: g_align_1
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ad_jesd_align i_jesd_align (
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.rx_clk (rx_clk),
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.rx_sof (rx_ip_sof_s),
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.rx_ip_data (rx_ip_data_s[n*32+31:n*32]),
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.rx_data (rx_data_s[n*32+31:n*32]));
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end
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endgenerate
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assign rx_xcvr_status_s[15:15] = 1'd0;
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assign rx_xcvr_status_s[14:14] = rx_sync;
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assign rx_xcvr_status_s[13:13] = rx_ready_s;
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assign rx_xcvr_status_s[12:12] = rx_pll_locked_s;
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assign rx_xcvr_status_s[11: 8] = rx_rst_state_s;
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assign rx_xcvr_status_s[ 7: 4] = rx_cdr_locked_s;
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assign rx_xcvr_status_s[ 3: 0] = rx_cal_busy_s;
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ad_xcvr_rx_rst #(.NUM_OF_LANES (4)) i_xcvr_rx_rst (
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.rx_clk (rx_clk),
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.rx_rstn (sys_resetn),
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.rx_sw_rstn (rx_sw_rstn_s),
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.rx_pll_locked (rx_pll_locked_s),
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.rx_cal_busy (rx_cal_busy_s),
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.rx_cdr_locked (rx_cdr_locked_s),
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.rx_analog_reset (rx_analog_reset_s),
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.rx_digital_reset (rx_digital_reset_s),
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.rx_ready (rx_ready_s),
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.rx_rst_state (rx_rst_state_s));
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fmcjesdadc1_spi i_fmcjesdadc1_spi (
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.spi_csn (spi_csn),
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.spi_clk (spi_clk),
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@ -357,148 +224,90 @@ module system_top (
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.spi_miso (spi_miso),
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.spi_sdio (spi_sdio));
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assign hdmi_rstn = 1'b1;
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assign hdmi_scl = (hdmi_scl_oe == 1'b1) ? 1'b0 : 1'bz;
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assign hdmi_sda = (hdmi_sda_oe == 1'b1) ? 1'b0 : 1'bz;
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ad_iobuf #(.DATA_WIDTH(12)) i_iobuf_bd (
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.dio_t ({8'hff, 4'h0}),
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.dio_i (gpio_o[11:0]),
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.dio_o (gpio_i[11:0]),
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.dio_p (gpio_bd));
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system_bd i_system_bd (
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.sys_hps_memory_mem_a (ddr3_a),
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.sys_hps_memory_mem_ba (ddr3_ba),
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.sys_hps_memory_mem_ck (ddr3_ck_p),
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.sys_hps_memory_mem_ck_n (ddr3_ck_n),
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.sys_hps_memory_mem_cke (ddr3_cke),
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.sys_hps_memory_mem_cs_n (ddr3_cs_n),
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.sys_hps_memory_mem_ras_n (ddr3_ras_n),
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.sys_hps_memory_mem_cas_n (ddr3_cas_n),
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.sys_hps_memory_mem_we_n (ddr3_we_n),
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.sys_hps_memory_mem_reset_n (ddr3_reset_n),
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.sys_hps_memory_mem_dq (ddr3_dq),
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.sys_hps_memory_mem_dqs (ddr3_dqs_p),
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.sys_hps_memory_mem_dqs_n (ddr3_dqs_n),
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.sys_hps_memory_mem_odt (ddr3_odt),
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.sys_hps_memory_mem_dm (ddr3_dm),
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.sys_hps_memory_oct_rzqin (ddr3_oct_rzqin),
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.clk_clk (sys_clk),
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.reset_reset_n (sys_resetn),
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.axi_ad9250_0_xcvr_clk_clk (rx_clk),
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.axi_ad9250_0_xcvr_data_data (rx_data_s[63:0]),
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.axi_ad9250_0_adc_clock_clk (adc0_clk),
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.axi_ad9250_0_adc_dma_if_adc_valid_a (),
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.axi_ad9250_0_adc_dma_if_adc_enable_a (adc0_enable_a_s),
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.axi_ad9250_0_adc_dma_if_adc_data_a (adc0_data_a_s),
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.axi_ad9250_0_adc_dma_if_adc_valid_b (),
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.axi_ad9250_0_adc_dma_if_adc_enable_b (adc0_enable_b_s),
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.axi_ad9250_0_adc_dma_if_adc_data_b (adc0_data_b_s),
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.axi_ad9250_0_adc_dma_if_adc_dovf (adc0_dovf_s),
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.axi_ad9250_0_adc_dma_if_adc_dunf (1'b0),
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.axi_dmac_0_fifo_wr_clock_clk (adc0_clk),
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.axi_dmac_0_fifo_wr_if_ovf (adc0_dovf_s),
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.axi_dmac_0_fifo_wr_if_wren (dma0_wr),
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.axi_dmac_0_fifo_wr_if_data (dma0_wdata),
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.axi_dmac_0_fifo_wr_if_sync (1'b1),
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.axi_ad9250_1_xcvr_clk_clk (rx_clk),
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.axi_ad9250_1_xcvr_data_data (rx_data_s[127:64]),
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.axi_ad9250_1_adc_clock_clk (adc1_clk),
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.axi_ad9250_1_adc_dma_if_adc_valid_a (),
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.axi_ad9250_1_adc_dma_if_adc_enable_a (adc1_enable_a_s),
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.axi_ad9250_1_adc_dma_if_adc_data_a (adc1_data_a_s),
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.axi_ad9250_1_adc_dma_if_adc_valid_b (),
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.axi_ad9250_1_adc_dma_if_adc_enable_b (adc1_enable_b_s),
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.axi_ad9250_1_adc_dma_if_adc_data_b (adc1_data_b_s),
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.axi_ad9250_1_adc_dma_if_adc_dovf (adc1_dovf_s),
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.axi_ad9250_1_adc_dma_if_adc_dunf (1'b0),
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.axi_dmac_1_fifo_wr_clock_clk (adc1_clk),
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.axi_dmac_1_fifo_wr_if_ovf (adc1_dovf_s),
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.axi_dmac_1_fifo_wr_if_wren (dma1_wr),
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.axi_dmac_1_fifo_wr_if_data (dma1_wdata),
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.axi_dmac_1_fifo_wr_if_sync (1'b1),
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.sys_jesd204b_s1_ref_clk_in_clk_clk (ref_clk),
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.sys_jesd204b_s1_rx_clk_out_clk_clk (rx_clk),
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.sys_jesd204b_s1_jesd204_rx_link_data (rx_ip_data_s),
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.sys_jesd204b_s1_jesd204_rx_link_valid (),
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.sys_jesd204b_s1_jesd204_rx_link_ready (1'b1),
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.sys_jesd204b_s1_alldev_lane_aligned_export (rx_lane_aligned_s),
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.sys_jesd204b_s1_sysref_export (rx_sysref),
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.sys_jesd204b_s1_jesd204_rx_frame_error_export (rx_err_s),
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.sys_jesd204b_s1_dev_lane_aligned_export (rx_lane_aligned_s),
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.sys_jesd204b_s1_dev_sync_n_export (rx_sync),
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.sys_jesd204b_s1_sof_export (rx_ip_sof_s),
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.sys_jesd204b_s1_rx_serial_data_rx_serial_data (rx_data),
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.sys_jesd204b_s1_rx_analogreset_rx_analogreset (rx_analog_reset_s),
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.sys_jesd204b_s1_rx_digitalreset_rx_digitalreset (rx_digital_reset_s),
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.sys_jesd204b_s1_rx_islockedtodata_export (rx_cdr_locked_s),
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.sys_jesd204b_s1_rx_cal_busy_export (rx_cal_busy_s),
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.sys_hps_spim0_txd (spi_mosi),
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.sys_hps_spim0_rxd (spi_miso),
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.sys_hps_spim0_ss_in_n (1'b1),
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.sys_hps_spim0_ssi_oe_n (spi_csn),
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.sys_hps_spim0_ss_0_n (),
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.sys_hps_spim0_ss_1_n (),
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.sys_hps_spim0_ss_2_n (),
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.sys_hps_spim0_ss_3_n (),
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.sys_jesd204b_s1_pll_locked_export (rx_pll_locked_s),
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.sys_hps_spim0_sclk_out_clk (spi_clk),
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.sys_hps_io_hps_io_emac1_inst_TX_CLK (eth1_tx_clk),
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.sys_hps_io_hps_io_emac1_inst_TXD0 (eth1_txd0),
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.sys_hps_io_hps_io_emac1_inst_TXD1 (eth1_txd1),
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.sys_hps_io_hps_io_emac1_inst_TX_CTL (eth1_tx_ctl),
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.sys_hps_io_hps_io_emac1_inst_RXD0 (eth1_rxd0),
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.sys_hps_io_hps_io_emac1_inst_RXD1 (eth1_rxd1),
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.sys_hps_io_hps_io_emac1_inst_TXD2 (eth1_txd2),
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.sys_hps_io_hps_io_emac1_inst_TXD3 (eth1_txd3),
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.sys_hps_io_hps_io_emac1_inst_MDIO (eth1_mdio),
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.sys_hps_io_hps_io_emac1_inst_MDC (eth1_mdc),
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.sys_hps_io_hps_io_emac1_inst_RX_CTL (eth1_rx_ctl),
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.sys_hps_io_hps_io_emac1_inst_RX_CLK (eth1_rx_clk),
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.sys_hps_io_hps_io_emac1_inst_RXD2 (eth1_rxd2),
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.sys_hps_io_hps_io_emac1_inst_RXD3 (eth1_rxd3),
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.sys_hps_io_hps_io_qspi_inst_IO0 (qspi_io0),
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.sys_hps_io_hps_io_qspi_inst_IO1 (qspi_io1),
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.sys_hps_io_hps_io_qspi_inst_IO2 (qspi_io2),
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.sys_hps_io_hps_io_qspi_inst_IO3 (qspi_io3),
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.sys_hps_io_hps_io_qspi_inst_SS0 (qspi_ss0),
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.sys_hps_io_hps_io_qspi_inst_CLK (qspi_clk),
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.sys_hps_io_hps_io_sdio_inst_CMD (sdio_cmd),
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.sys_hps_io_hps_io_sdio_inst_D0 (sdio_d0),
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.sys_hps_io_hps_io_sdio_inst_D1 (sdio_d1),
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.sys_hps_io_hps_io_sdio_inst_CLK (sdio_clk),
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.sys_hps_io_hps_io_sdio_inst_D2 (sdio_d2),
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.sys_hps_io_hps_io_sdio_inst_D3 (sdio_d3),
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.sys_hps_io_hps_io_usb1_inst_D0 (usb1_d0),
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.sys_hps_io_hps_io_usb1_inst_D1 (usb1_d1),
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.sys_hps_io_hps_io_usb1_inst_D2 (usb1_d2),
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.sys_hps_io_hps_io_usb1_inst_D3 (usb1_d3),
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.sys_hps_io_hps_io_usb1_inst_D4 (usb1_d4),
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.sys_hps_io_hps_io_usb1_inst_D5 (usb1_d5),
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.sys_hps_io_hps_io_usb1_inst_D6 (usb1_d6),
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.sys_hps_io_hps_io_usb1_inst_D7 (usb1_d7),
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.sys_hps_io_hps_io_usb1_inst_CLK (usb1_clk),
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.sys_hps_io_hps_io_usb1_inst_STP (usb1_stp),
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.sys_hps_io_hps_io_usb1_inst_DIR (usb1_dir),
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.sys_hps_io_hps_io_usb1_inst_NXT (usb1_nxt),
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.sys_hps_io_hps_io_uart0_inst_RX (uart0_rx),
|
||||
.sys_hps_io_hps_io_uart0_inst_TX (uart0_tx),
|
||||
.sys_hps_h2f_reset_reset_n (sys_resetn),
|
||||
.sys_gpio_external_connection_in_port ({rx_xcvr_status_s, 4'd0, push_buttons, 4'd0, dip_switches}),
|
||||
.sys_gpio_external_connection_out_port ({14'd0, rx_sw_rstn_s, rx_sysref_s, 12'd0, led}),
|
||||
.axi_hdmi_tx_0_hdmi_if_h_clk (hdmi_out_clk),
|
||||
.axi_hdmi_tx_0_hdmi_if_h16_hsync (),
|
||||
.axi_hdmi_tx_0_hdmi_if_h16_vsync (),
|
||||
.axi_hdmi_tx_0_hdmi_if_h16_data_e (),
|
||||
.axi_hdmi_tx_0_hdmi_if_h16_data (),
|
||||
.axi_hdmi_tx_0_hdmi_if_h16_es_data (hdmi_data),
|
||||
.axi_hdmi_tx_0_hdmi_if_h24_hsync (),
|
||||
.axi_hdmi_tx_0_hdmi_if_h24_vsync (),
|
||||
.axi_hdmi_tx_0_hdmi_if_h24_data_e (),
|
||||
.axi_hdmi_tx_0_hdmi_if_h24_data (),
|
||||
.axi_hdmi_tx_0_hdmi_if_h36_hsync (),
|
||||
.axi_hdmi_tx_0_hdmi_if_h36_vsync (),
|
||||
.axi_hdmi_tx_0_hdmi_if_h36_data_e (),
|
||||
.axi_hdmi_tx_0_hdmi_if_h36_data (),
|
||||
.sys_hps_i2c0_scl_in_clk (hdmi_scl),
|
||||
.sys_hps_i2c0_clk_clk (hdmi_scl_oe),
|
||||
.sys_hps_i2c0_out_data (hdmi_sda_oe),
|
||||
.sys_hps_i2c0_sda (hdmi_sda));
|
||||
.a5soc_base_sys_gpio_bd_external_connection_in_port (gpio_i[63:32]),
|
||||
.a5soc_base_sys_gpio_bd_external_connection_out_port (gpio_o[63:32]),
|
||||
.a5soc_base_sys_gpio_external_connection_in_port (gpio_i[31:0]),
|
||||
.a5soc_base_sys_gpio_external_connection_out_port (gpio_o[31:0]),
|
||||
.a5soc_base_sys_hps_i2c0_out_data (fmc_a_sda_oe),
|
||||
.a5soc_base_sys_hps_i2c0_sda (fmc_a_sda),
|
||||
.a5soc_base_sys_hps_i2c0_clk_clk (fmc_a_scl_oe),
|
||||
.a5soc_base_sys_hps_i2c0_scl_in_clk (fmc_a_scl),
|
||||
.a5soc_base_sys_hps_io_hps_io_emac1_inst_TX_CLK (eth1_tx_clk),
|
||||
.a5soc_base_sys_hps_io_hps_io_emac1_inst_TXD0 (eth1_txd0),
|
||||
.a5soc_base_sys_hps_io_hps_io_emac1_inst_TXD1 (eth1_txd1),
|
||||
.a5soc_base_sys_hps_io_hps_io_emac1_inst_TX_CTL (eth1_tx_ctl),
|
||||
.a5soc_base_sys_hps_io_hps_io_emac1_inst_RXD0 (eth1_rxd0),
|
||||
.a5soc_base_sys_hps_io_hps_io_emac1_inst_RXD1 (eth1_rxd1),
|
||||
.a5soc_base_sys_hps_io_hps_io_emac1_inst_TXD2 (eth1_txd2),
|
||||
.a5soc_base_sys_hps_io_hps_io_emac1_inst_TXD3 (eth1_txd3),
|
||||
.a5soc_base_sys_hps_io_hps_io_emac1_inst_MDIO (eth1_mdio),
|
||||
.a5soc_base_sys_hps_io_hps_io_emac1_inst_MDC (eth1_mdc),
|
||||
.a5soc_base_sys_hps_io_hps_io_emac1_inst_RX_CTL (eth1_rx_ctl),
|
||||
.a5soc_base_sys_hps_io_hps_io_emac1_inst_RX_CLK (eth1_rx_clk),
|
||||
.a5soc_base_sys_hps_io_hps_io_emac1_inst_RXD2 (eth1_rxd2),
|
||||
.a5soc_base_sys_hps_io_hps_io_emac1_inst_RXD3 (eth1_rxd3),
|
||||
.a5soc_base_sys_hps_io_hps_io_qspi_inst_IO0 (qspi_io0),
|
||||
.a5soc_base_sys_hps_io_hps_io_qspi_inst_IO1 (qspi_io1),
|
||||
.a5soc_base_sys_hps_io_hps_io_qspi_inst_IO2 (qspi_io2),
|
||||
.a5soc_base_sys_hps_io_hps_io_qspi_inst_IO3 (qspi_io3),
|
||||
.a5soc_base_sys_hps_io_hps_io_qspi_inst_SS0 (qspi_ss0),
|
||||
.a5soc_base_sys_hps_io_hps_io_qspi_inst_CLK (qspi_clk),
|
||||
.a5soc_base_sys_hps_io_hps_io_sdio_inst_CMD (sdio_cmd),
|
||||
.a5soc_base_sys_hps_io_hps_io_sdio_inst_D0 (sdio_d0),
|
||||
.a5soc_base_sys_hps_io_hps_io_sdio_inst_D1 (sdio_d1),
|
||||
.a5soc_base_sys_hps_io_hps_io_sdio_inst_CLK (sdio_clk),
|
||||
.a5soc_base_sys_hps_io_hps_io_sdio_inst_D2 (sdio_d2),
|
||||
.a5soc_base_sys_hps_io_hps_io_sdio_inst_D3 (sdio_d3),
|
||||
.a5soc_base_sys_hps_io_hps_io_usb1_inst_D0 (usb1_d0),
|
||||
.a5soc_base_sys_hps_io_hps_io_usb1_inst_D1 (usb1_d1),
|
||||
.a5soc_base_sys_hps_io_hps_io_usb1_inst_D2 (usb1_d2),
|
||||
.a5soc_base_sys_hps_io_hps_io_usb1_inst_D3 (usb1_d3),
|
||||
.a5soc_base_sys_hps_io_hps_io_usb1_inst_D4 (usb1_d4),
|
||||
.a5soc_base_sys_hps_io_hps_io_usb1_inst_D5 (usb1_d5),
|
||||
.a5soc_base_sys_hps_io_hps_io_usb1_inst_D6 (usb1_d6),
|
||||
.a5soc_base_sys_hps_io_hps_io_usb1_inst_D7 (usb1_d7),
|
||||
.a5soc_base_sys_hps_io_hps_io_usb1_inst_CLK (usb1_clk),
|
||||
.a5soc_base_sys_hps_io_hps_io_usb1_inst_STP (usb1_stp),
|
||||
.a5soc_base_sys_hps_io_hps_io_usb1_inst_DIR (usb1_dir),
|
||||
.a5soc_base_sys_hps_io_hps_io_usb1_inst_NXT (usb1_nxt),
|
||||
.a5soc_base_sys_hps_io_hps_io_uart0_inst_RX (uart0_rx),
|
||||
.a5soc_base_sys_hps_io_hps_io_uart0_inst_TX (uart0_tx),
|
||||
.a5soc_base_sys_hps_memory_mem_a (ddr3_a),
|
||||
.a5soc_base_sys_hps_memory_mem_ba (ddr3_ba),
|
||||
.a5soc_base_sys_hps_memory_mem_ck (ddr3_ck_p),
|
||||
.a5soc_base_sys_hps_memory_mem_ck_n (ddr3_ck_n),
|
||||
.a5soc_base_sys_hps_memory_mem_cke (ddr3_cke),
|
||||
.a5soc_base_sys_hps_memory_mem_cs_n (ddr3_cs_n),
|
||||
.a5soc_base_sys_hps_memory_mem_ras_n (ddr3_ras_n),
|
||||
.a5soc_base_sys_hps_memory_mem_cas_n (ddr3_cas_n),
|
||||
.a5soc_base_sys_hps_memory_mem_we_n (ddr3_we_n),
|
||||
.a5soc_base_sys_hps_memory_mem_reset_n (ddr3_reset_n),
|
||||
.a5soc_base_sys_hps_memory_mem_dq (ddr3_dq),
|
||||
.a5soc_base_sys_hps_memory_mem_dqs (ddr3_dqs_p),
|
||||
.a5soc_base_sys_hps_memory_mem_dqs_n (ddr3_dqs_n),
|
||||
.a5soc_base_sys_hps_memory_mem_odt (ddr3_odt),
|
||||
.a5soc_base_sys_hps_memory_mem_dm (ddr3_dm),
|
||||
.a5soc_base_sys_hps_memory_oct_rzqin (ddr3_oct_rzqin),
|
||||
.a5soc_base_sys_hps_spim0_txd (spi_mosi),
|
||||
.a5soc_base_sys_hps_spim0_rxd (spi_miso),
|
||||
.a5soc_base_sys_hps_spim0_ss_in_n (1'b1),
|
||||
.a5soc_base_sys_hps_spim0_ssi_oe_n (spi_csn),
|
||||
.a5soc_base_sys_hps_spim0_ss_0_n (),
|
||||
.a5soc_base_sys_hps_spim0_ss_1_n (),
|
||||
.a5soc_base_sys_hps_spim0_ss_2_n (),
|
||||
.a5soc_base_sys_hps_spim0_ss_3_n (),
|
||||
.a5soc_base_sys_hps_spim0_sclk_out_clk (spi_clk),
|
||||
.fmcjesdadc1_rx_data_rx_serial_data (rx_data),
|
||||
.fmcjesdadc1_rx_ref_clk_clk (ref_clk),
|
||||
.fmcjesdadc1_rx_sync_rx_sync (rx_sync),
|
||||
.fmcjesdadc1_rx_sysref_rx_ext_sysref_out (rx_sysref));
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue