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jesd204:up_common: Add a synthesis register for NUM_LINKS

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Istvan Csomortani 2018-04-04 12:34:22 +01:00 committed by István Csomortáni
parent d18eb85e41
commit e432e77f1e
1 changed files with 1 additions and 0 deletions
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library/jesd204/tb/axi_jesd204_tx_regmap_tb.v
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@ -161,6 +161,7 @@ module axi_jesd204_tx_tb;
set_reset_reg_value('h0c, 32'h32303454); /* PCORE magic register */
set_reset_reg_value('h10, NUM_LANES); /* Number of lanes */
set_reset_reg_value('h14, 'h2); /* Datapath width */
set_reset_reg_value('h18, NUM_LINKS); /* Number of links */
set_reset_reg_value('hc0, 'h1); /* Link disable */
set_reset_reg_value('hc4, 'h1); /* Core state */
// set_reset_reg_value('hc8, 'h80000); /* clock monitor */