daq2: Update A10GX project, with the latest changes.
Works with up to 64k samplesmain
Adrian Costina
parent
83399ef6ee
commit
e36f27b061
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@ -374,16 +374,22 @@
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internal="a10gx_base.sys_ethernet_sgmii"
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type="conduit"
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dir="end" />
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<interface
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name="a10gx_base_sys_gpio"
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internal="a10gx_base.sys_gpio"
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type="conduit"
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dir="end" />
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<interface name="a10gx_base_sys_gpio" internal="a10gx_base.sys_gpio" />
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<interface
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name="a10gx_base_sys_gpio_bd"
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internal="a10gx_base.sys_gpio_bd"
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type="conduit"
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dir="end" />
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<interface
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name="a10gx_base_sys_gpio_in"
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internal="a10gx_base.sys_gpio_in"
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type="conduit"
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dir="end" />
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<interface
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name="a10gx_base_sys_gpio_out"
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internal="a10gx_base.sys_gpio_out"
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type="conduit"
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dir="end" />
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<interface
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name="a10gx_base_sys_spi"
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internal="a10gx_base.sys_spi"
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@ -452,7 +458,7 @@
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<parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
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<parameter name="AUTO_GENERATION_ID" value="0" />
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<parameter name="AUTO_MEM_CLK_CLOCK_DOMAIN" value="8" />
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<parameter name="AUTO_MEM_CLK_CLOCK_RATE" value="133332500" />
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<parameter name="AUTO_MEM_CLK_CLOCK_RATE" value="133333250" />
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<parameter name="AUTO_MEM_CLK_RESET_DOMAIN" value="8" />
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<parameter name="AUTO_RX_REF_CLK_CLOCK_DOMAIN" value="4" />
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<parameter name="AUTO_RX_REF_CLK_CLOCK_RATE" value="0" />
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@ -1,9 +1,9 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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//
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// All rights reserved.
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//
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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@ -21,16 +21,16 @@
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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@ -163,14 +163,14 @@ module system_top (
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// gpio
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input trig;
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inout adc_fdb;
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inout adc_fda;
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inout dac_irq;
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inout [ 1:0] clkd_status;
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inout adc_pd;
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inout dac_txen;
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inout dac_reset;
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inout clkd_sync;
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input adc_fdb;
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input adc_fda;
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input dac_irq;
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input [ 1:0] clkd_status;
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output adc_pd;
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output dac_txen;
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output dac_reset;
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output clkd_sync;
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// spi
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@ -187,8 +187,8 @@ module system_top (
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wire eth_mdio_i;
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wire eth_mdio_o;
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wire eth_mdio_t;
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wire [ 63:0] gpio_i;
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wire [ 63:0] gpio_o;
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wire [ 31:0] gpio_i;
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wire [ 31:0] gpio_o;
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wire spi_miso_s;
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wire spi_mosi_s;
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wire [ 7:0] spi_csn_s;
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@ -207,24 +207,6 @@ module system_top (
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.spi_sdio (spi_sdio),
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.spi_dir (spi_dir));
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assign gpio_i[63:44] = gpio_o[63:44];
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assign gpio_i[43:43] = trig;
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assign gpio_i[39:39] = gpio_o[39:39];
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assign gpio_i[37:37] = gpio_o[37:37];
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ad_iobuf #(.DATA_WIDTH(9)) i_iobuf (
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.dio_t ({3'h0, 1'h0, 5'h1f}),
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.dio_i ({gpio_o[42:40], gpio_o[38], gpio_o[36:32]}),
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.dio_o ({gpio_i[42:40], gpio_i[38], gpio_i[36:32]}),
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.dio_p ({ adc_pd, // 42
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dac_txen, // 41
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dac_reset, // 40
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clkd_sync, // 38
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adc_fdb, // 36
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adc_fda, // 35
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dac_irq, // 34
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clkd_status})); // 32
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// board stuff
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assign eth_resetn = ~eth_reset;
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@ -264,11 +246,11 @@ module system_top (
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.a10gx_base_sys_ethernet_mdio_mdio_out (eth_mdio_o),
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.a10gx_base_sys_ethernet_mdio_mdio_oen (eth_mdio_t),
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.a10gx_base_sys_ethernet_ref_clk_clk (eth_ref_clk),
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.a10gx_base_sys_ethernet_reset_reset (eth_reset),
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.a10gx_base_sys_ethernet_reset_reset (eth_reset),
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.a10gx_base_sys_ethernet_sgmii_rxp_0 (eth_rxd),
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.a10gx_base_sys_ethernet_sgmii_txp_0 (eth_txd),
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.a10gx_base_sys_gpio_in_port (gpio_i[63:32]),
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.a10gx_base_sys_gpio_out_port (gpio_o[63:32]),
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.a10gx_base_sys_gpio_in_export ({trig, adc_fdb, adc_fda, dac_irq, clkd_status[1], clkd_status[0]}),
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.a10gx_base_sys_gpio_out_export ({adc_pd, dac_txen, dac_reset, clkd_sync}),
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.a10gx_base_sys_gpio_bd_in_port (gpio_i[31:0]),
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.a10gx_base_sys_gpio_bd_out_port (gpio_o[31:0]),
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.a10gx_base_sys_spi_MISO (spi_miso_s),
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@ -17,11 +17,19 @@
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type = "String";
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}
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}
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element ad9680_adcfifo
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{
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datum _sortIndex
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{
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value = "9";
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type = "int";
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}
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}
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element axi_ad9144_core
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{
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datum _sortIndex
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{
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value = "13";
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value = "14";
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type = "int";
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}
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}
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@ -37,7 +45,7 @@
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{
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datum _sortIndex
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{
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value = "11";
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value = "12";
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type = "int";
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}
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}
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@ -53,7 +61,7 @@
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{
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datum _sortIndex
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{
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value = "10";
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value = "11";
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type = "int";
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}
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}
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@ -90,7 +98,7 @@
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{
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datum _sortIndex
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{
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value = "14";
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value = "15";
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type = "int";
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}
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}
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@ -222,6 +230,126 @@
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type = "String";
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}
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}
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element daq2_bd
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{
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datum _originalDeviceFamily
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{
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value = "Arria 10";
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type = "String";
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}
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}
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element daq2_bd
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{
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datum _originalDeviceFamily
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{
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value = "Arria 10";
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type = "String";
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}
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}
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element daq2_bd
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{
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datum _originalDeviceFamily
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{
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value = "Arria 10";
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type = "String";
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}
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}
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element daq2_bd
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{
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datum _originalDeviceFamily
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{
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value = "Arria 10";
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type = "String";
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}
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}
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element daq2_bd
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{
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datum _originalDeviceFamily
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{
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value = "Arria 10";
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type = "String";
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}
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}
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element daq2_bd
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{
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datum _originalDeviceFamily
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{
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value = "Arria 10";
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type = "String";
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}
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}
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element daq2_bd
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{
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datum _originalDeviceFamily
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{
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value = "Arria 10";
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type = "String";
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}
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}
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element daq2_bd
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{
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datum _originalDeviceFamily
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{
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value = "Arria 10";
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type = "String";
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}
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}
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element daq2_bd
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{
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datum _originalDeviceFamily
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{
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value = "Arria 10";
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type = "String";
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}
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}
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element daq2_bd
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{
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datum _originalDeviceFamily
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{
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value = "Arria 10";
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type = "String";
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}
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}
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element daq2_bd
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{
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datum _originalDeviceFamily
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{
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value = "Arria 10";
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type = "String";
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}
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}
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element daq2_bd
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{
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datum _originalDeviceFamily
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{
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value = "Arria 10";
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type = "String";
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}
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}
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element daq2_bd
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{
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datum _originalDeviceFamily
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{
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value = "Arria 10";
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type = "String";
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}
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}
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element daq2_bd
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{
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datum _originalDeviceFamily
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{
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value = "Arria 10";
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type = "String";
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}
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}
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element daq2_bd
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{
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datum _originalDeviceFamily
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{
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value = "Arria 10";
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type = "String";
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}
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}
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element mem_clk
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{
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datum _sortIndex
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@ -458,7 +586,7 @@
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{
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datum _sortIndex
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{
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value = "9";
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value = "10";
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type = "int";
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}
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}
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@ -466,7 +594,7 @@
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{
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datum _sortIndex
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{
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value = "12";
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value = "13";
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type = "int";
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}
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}
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@ -474,7 +602,7 @@
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{
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datum _sortIndex
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{
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value = "17";
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value = "18";
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type = "int";
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}
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}
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@ -482,7 +610,7 @@
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{
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datum _sortIndex
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{
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value = "15";
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value = "16";
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type = "int";
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}
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}
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@ -506,7 +634,7 @@
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{
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datum _sortIndex
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{
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value = "16";
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value = "17";
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type = "int";
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}
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}
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@ -540,7 +668,7 @@
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<parameter name="hideFromIPCatalog" value="false" />
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<parameter name="lockedInterfaceDefinition" value="" />
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<parameter name="maxAdditionalLatency" value="2" />
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<parameter name="projectName" value="" />
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<parameter name="projectName" value="daq2_a10gx.qpf" />
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<parameter name="sopcBorderPoints" value="false" />
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<parameter name="systemHash" value="0" />
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<parameter name="testBenchDutName" value="" />
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@ -637,6 +765,12 @@
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internal="axi_jesd_xcvr.if_tx_ext_sysref_in"
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type="conduit"
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dir="end" />
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<module name="ad9680_adcfifo" kind="util_adcfifo" version="1.0" enabled="1">
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<parameter name="ADC_DATA_WIDTH" value="128" />
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<parameter name="DMA_ADDRESS_WIDTH" value="16" />
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<parameter name="DMA_DATA_WIDTH" value="128" />
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<parameter name="DMA_READY_ENABLE" value="1" />
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</module>
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<module name="axi_ad9144_core" kind="axi_ad9144" version="1.0" enabled="1">
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<parameter name="ID" value="0" />
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<parameter name="QUAD_OR_DUAL_N" value="0" />
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@ -668,15 +802,15 @@
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<parameter name="AXI_SLICE_DEST" value="0" />
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<parameter name="AXI_SLICE_SRC" value="0" />
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<parameter name="CYCLIC" value="0" />
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<parameter name="DMA_2D_TRANSFER" value="1" />
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<parameter name="DMA_2D_TRANSFER" value="0" />
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<parameter name="DMA_DATA_WIDTH_DEST" value="128" />
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<parameter name="DMA_DATA_WIDTH_SRC" value="128" />
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<parameter name="DMA_LENGTH_WIDTH" value="14" />
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<parameter name="DMA_LENGTH_WIDTH" value="24" />
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<parameter name="DMA_TYPE_DEST" value="0" />
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<parameter name="DMA_TYPE_SRC" value="2" />
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<parameter name="DMA_TYPE_SRC" value="1" />
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<parameter name="FIFO_SIZE" value="4" />
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<parameter name="ID" value="0" />
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<parameter name="SYNC_TRANSFER_START" value="0" />
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<parameter name="SYNC_TRANSFER_START" value="1" />
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</module>
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<module name="axi_jesd_xcvr" kind="axi_jesd_xcvr" version="1.0" enabled="1">
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<parameter name="DEVICE_TYPE" value="0" />
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@ -1463,6 +1597,16 @@
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version="15.0"
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start="sys_clk.out_clk"
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end="xcvr_rst_cntrl.clock" />
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<connection
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kind="clock"
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version="15.0"
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start="mem_clk.out_clk"
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end="ad9680_adcfifo.if_dma_clk" />
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<connection
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kind="clock"
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version="15.0"
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start="mem_clk.out_clk"
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end="axi_ad9680_dma.if_s_axis_aclk" />
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<connection
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kind="clock"
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version="15.0"
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@ -1533,6 +1677,11 @@
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version="15.0"
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start="xcvr_rx_pll.outclk0"
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end="util_cpack_0.if_adc_clk" />
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<connection
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kind="clock"
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version="15.0"
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start="xcvr_rx_pll.outclk0"
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end="ad9680_adcfifo.if_adc_clk" />
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<connection
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kind="clock"
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version="15.0"
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@ -1543,11 +1692,6 @@
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version="15.0"
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start="xcvr_tx_pll.outclk0"
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end="axi_ad9144_dma.if_fifo_rd_clk" />
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<connection
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kind="clock"
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version="15.0"
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start="xcvr_rx_pll.outclk0"
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end="axi_ad9680_dma.if_fifo_wr_clk" />
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<connection
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kind="clock"
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version="15.0"
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@ -1589,6 +1733,17 @@
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<parameter name="startPortLSB" value="0" />
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<parameter name="width" value="0" />
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</connection>
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<connection
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kind="conduit"
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version="15.0"
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start="util_cpack_0.if_adc_data"
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end="ad9680_adcfifo.if_adc_wdata">
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<parameter name="endPort" value="" />
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<parameter name="endPortLSB" value="0" />
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<parameter name="startPort" value="" />
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<parameter name="startPortLSB" value="0" />
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<parameter name="width" value="0" />
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</connection>
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<connection
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kind="conduit"
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version="15.0"
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|
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@ -1611,17 +1766,6 @@
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<parameter name="startPortLSB" value="0" />
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<parameter name="width" value="0" />
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</connection>
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<connection
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kind="conduit"
|
||||
version="15.0"
|
||||
start="axi_ad9680_core.if_adc_dovf"
|
||||
end="axi_ad9680_dma.if_fifo_wr_overflow">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.0"
|
||||
|
|
@ -1644,22 +1788,11 @@
|
|||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.0"
|
||||
start="util_cpack_0.if_adc_sync"
|
||||
end="axi_ad9680_dma.if_fifo_wr_sync">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.0"
|
||||
start="util_cpack_0.if_adc_valid"
|
||||
end="axi_ad9680_dma.if_fifo_wr_en">
|
||||
end="ad9680_adcfifo.if_adc_wr">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
|
|
@ -1765,6 +1898,50 @@
|
|||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.0"
|
||||
start="ad9680_adcfifo.if_dma_wdata"
|
||||
end="axi_ad9680_dma.if_s_axis_data">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.0"
|
||||
start="ad9680_adcfifo.if_dma_wr"
|
||||
end="axi_ad9680_dma.if_s_axis_valid">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.0"
|
||||
start="ad9680_adcfifo.if_dma_wready"
|
||||
end="axi_ad9680_dma.if_s_axis_ready">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.0"
|
||||
start="ad9680_adcfifo.if_dma_xfer_req"
|
||||
end="axi_ad9680_dma.if_s_axis_xfer_req">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.0"
|
||||
|
|
@ -1787,17 +1964,6 @@
|
|||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.0"
|
||||
start="axi_ad9680_dma.if_fifo_wr_din"
|
||||
end="util_cpack_0.if_adc_data">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.0"
|
||||
|
|
@ -2073,6 +2239,16 @@
|
|||
version="15.0"
|
||||
start="mem_rst.out_reset"
|
||||
end="util_cpack_0.if_adc_rst" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="15.0"
|
||||
start="sys_rst.out_reset"
|
||||
end="ad9680_adcfifo.if_adc_rst" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="15.0"
|
||||
start="mem_rst.out_reset"
|
||||
end="ad9680_adcfifo.if_adc_rst" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="15.0"
|
||||
|
|
|
|||
Loading…
Reference in New Issue