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axi/util_adxcvr: Add register to control eyescan reset

main
Adrian Costina 2018-11-08 13:54:15 +00:00
parent b4ea058085
commit e1f15f946b
6 changed files with 78 additions and 1 deletions
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35
library/xilinx/axi_adxcvr/axi_adxcvr.v
View File

@ -63,6 +63,7 @@ module axi_adxcvr #(
output up_es_enb_0, output up_es_enb_0,
output [11:0] up_es_addr_0, output [11:0] up_es_addr_0,
output up_es_wr_0, output up_es_wr_0,
output up_es_reset_0,
output [15:0] up_es_wdata_0, output [15:0] up_es_wdata_0,
input [15:0] up_es_rdata_0, input [15:0] up_es_rdata_0,
input up_es_ready_0, input up_es_ready_0,
@ -88,6 +89,7 @@ module axi_adxcvr #(
output up_es_enb_1, output up_es_enb_1,
output [11:0] up_es_addr_1, output [11:0] up_es_addr_1,
output up_es_wr_1, output up_es_wr_1,
output up_es_reset_1,
output [15:0] up_es_wdata_1, output [15:0] up_es_wdata_1,
input [15:0] up_es_rdata_1, input [15:0] up_es_rdata_1,
input up_es_ready_1, input up_es_ready_1,
@ -113,6 +115,7 @@ module axi_adxcvr #(
output up_es_enb_2, output up_es_enb_2,
output [11:0] up_es_addr_2, output [11:0] up_es_addr_2,
output up_es_wr_2, output up_es_wr_2,
output up_es_reset_2,
output [15:0] up_es_wdata_2, output [15:0] up_es_wdata_2,
input [15:0] up_es_rdata_2, input [15:0] up_es_rdata_2,
input up_es_ready_2, input up_es_ready_2,
@ -138,6 +141,7 @@ module axi_adxcvr #(
output up_es_enb_3, output up_es_enb_3,
output [11:0] up_es_addr_3, output [11:0] up_es_addr_3,
output up_es_wr_3, output up_es_wr_3,
output up_es_reset_3,
output [15:0] up_es_wdata_3, output [15:0] up_es_wdata_3,
input [15:0] up_es_rdata_3, input [15:0] up_es_rdata_3,
input up_es_ready_3, input up_es_ready_3,
@ -170,6 +174,7 @@ module axi_adxcvr #(
output up_es_enb_4, output up_es_enb_4,
output [11:0] up_es_addr_4, output [11:0] up_es_addr_4,
output up_es_wr_4, output up_es_wr_4,
output up_es_reset_4,
output [15:0] up_es_wdata_4, output [15:0] up_es_wdata_4,
input [15:0] up_es_rdata_4, input [15:0] up_es_rdata_4,
input up_es_ready_4, input up_es_ready_4,
@ -195,6 +200,7 @@ module axi_adxcvr #(
output up_es_enb_5, output up_es_enb_5,
output [11:0] up_es_addr_5, output [11:0] up_es_addr_5,
output up_es_wr_5, output up_es_wr_5,
output up_es_reset_5,
output [15:0] up_es_wdata_5, output [15:0] up_es_wdata_5,
input [15:0] up_es_rdata_5, input [15:0] up_es_rdata_5,
input up_es_ready_5, input up_es_ready_5,
@ -220,6 +226,7 @@ module axi_adxcvr #(
output up_es_enb_6, output up_es_enb_6,
output [11:0] up_es_addr_6, output [11:0] up_es_addr_6,
output up_es_wr_6, output up_es_wr_6,
output up_es_reset_6,
output [15:0] up_es_wdata_6, output [15:0] up_es_wdata_6,
input [15:0] up_es_rdata_6, input [15:0] up_es_rdata_6,
input up_es_ready_6, input up_es_ready_6,
@ -245,6 +252,7 @@ module axi_adxcvr #(
output up_es_enb_7, output up_es_enb_7,
output [11:0] up_es_addr_7, output [11:0] up_es_addr_7,
output up_es_wr_7, output up_es_wr_7,
output up_es_reset_7,
output [15:0] up_es_wdata_7, output [15:0] up_es_wdata_7,
input [15:0] up_es_rdata_7, input [15:0] up_es_rdata_7,
input up_es_ready_7, input up_es_ready_7,
@ -277,6 +285,7 @@ module axi_adxcvr #(
output up_es_enb_8, output up_es_enb_8,
output [11:0] up_es_addr_8, output [11:0] up_es_addr_8,
output up_es_wr_8, output up_es_wr_8,
output up_es_reset_8,
output [15:0] up_es_wdata_8, output [15:0] up_es_wdata_8,
input [15:0] up_es_rdata_8, input [15:0] up_es_rdata_8,
input up_es_ready_8, input up_es_ready_8,
@ -302,6 +311,7 @@ module axi_adxcvr #(
output up_es_enb_9, output up_es_enb_9,
output [11:0] up_es_addr_9, output [11:0] up_es_addr_9,
output up_es_wr_9, output up_es_wr_9,
output up_es_reset_9,
output [15:0] up_es_wdata_9, output [15:0] up_es_wdata_9,
input [15:0] up_es_rdata_9, input [15:0] up_es_rdata_9,
input up_es_ready_9, input up_es_ready_9,
@ -327,6 +337,7 @@ module axi_adxcvr #(
output up_es_enb_10, output up_es_enb_10,
output [11:0] up_es_addr_10, output [11:0] up_es_addr_10,
output up_es_wr_10, output up_es_wr_10,
output up_es_reset_10,
output [15:0] up_es_wdata_10, output [15:0] up_es_wdata_10,
input [15:0] up_es_rdata_10, input [15:0] up_es_rdata_10,
input up_es_ready_10, input up_es_ready_10,
@ -352,6 +363,7 @@ module axi_adxcvr #(
output up_es_enb_11, output up_es_enb_11,
output [11:0] up_es_addr_11, output [11:0] up_es_addr_11,
output up_es_wr_11, output up_es_wr_11,
output up_es_reset_11,
output [15:0] up_es_wdata_11, output [15:0] up_es_wdata_11,
input [15:0] up_es_rdata_11, input [15:0] up_es_rdata_11,
input up_es_ready_11, input up_es_ready_11,
@ -384,6 +396,7 @@ module axi_adxcvr #(
output up_es_enb_12, output up_es_enb_12,
output [11:0] up_es_addr_12, output [11:0] up_es_addr_12,
output up_es_wr_12, output up_es_wr_12,
output up_es_reset_12,
output [15:0] up_es_wdata_12, output [15:0] up_es_wdata_12,
input [15:0] up_es_rdata_12, input [15:0] up_es_rdata_12,
input up_es_ready_12, input up_es_ready_12,
@ -409,6 +422,7 @@ module axi_adxcvr #(
output up_es_enb_13, output up_es_enb_13,
output [11:0] up_es_addr_13, output [11:0] up_es_addr_13,
output up_es_wr_13, output up_es_wr_13,
output up_es_reset_13,
output [15:0] up_es_wdata_13, output [15:0] up_es_wdata_13,
input [15:0] up_es_rdata_13, input [15:0] up_es_rdata_13,
input up_es_ready_13, input up_es_ready_13,
@ -434,6 +448,7 @@ module axi_adxcvr #(
output up_es_enb_14, output up_es_enb_14,
output [11:0] up_es_addr_14, output [11:0] up_es_addr_14,
output up_es_wr_14, output up_es_wr_14,
output up_es_reset_14,
output [15:0] up_es_wdata_14, output [15:0] up_es_wdata_14,
input [15:0] up_es_rdata_14, input [15:0] up_es_rdata_14,
input up_es_ready_14, input up_es_ready_14,
@ -459,6 +474,7 @@ module axi_adxcvr #(
output up_es_enb_15, output up_es_enb_15,
output [11:0] up_es_addr_15, output [11:0] up_es_addr_15,
output up_es_wr_15, output up_es_wr_15,
output up_es_reset_15,
output [15:0] up_es_wdata_15, output [15:0] up_es_wdata_15,
input [15:0] up_es_rdata_15, input [15:0] up_es_rdata_15,
input up_es_ready_15, input up_es_ready_15,
@ -678,6 +694,24 @@ module axi_adxcvr #(
wire [ 9:0] up_raddr; wire [ 9:0] up_raddr;
wire [31:0] up_rdata; wire [31:0] up_rdata;
wire up_rack; wire up_rack;
wire [15:0] up_es_reset;
assign up_es_reset_0 = up_es_reset[0];
assign up_es_reset_1 = up_es_reset[1];
assign up_es_reset_2 = up_es_reset[2];
assign up_es_reset_3 = up_es_reset[3];
assign up_es_reset_4 = up_es_reset[4];
assign up_es_reset_5 = up_es_reset[5];
assign up_es_reset_6 = up_es_reset[6];
assign up_es_reset_7 = up_es_reset[7];
assign up_es_reset_8 = up_es_reset[8];
assign up_es_reset_9 = up_es_reset[9];
assign up_es_reset_10 = up_es_reset[10];
assign up_es_reset_11 = up_es_reset[11];
assign up_es_reset_12 = up_es_reset[12];
assign up_es_reset_13 = up_es_reset[13];
assign up_es_reset_14 = up_es_reset[14];
assign up_es_reset_15 = up_es_reset[15];
// channel broadcast // channel broadcast
@ -1859,6 +1893,7 @@ module axi_adxcvr #(
.up_es_sel (up_es_sel), .up_es_sel (up_es_sel),
.up_es_req (up_es_req), .up_es_req (up_es_req),
.up_es_ack (up_es_ack), .up_es_ack (up_es_ack),
.up_es_reset (up_es_reset),
.up_es_pscale (up_es_pscale), .up_es_pscale (up_es_pscale),
.up_es_vrange (up_es_vrange), .up_es_vrange (up_es_vrange),
.up_es_vstep (up_es_vstep), .up_es_vstep (up_es_vstep),

1
library/xilinx/axi_adxcvr/axi_adxcvr_ip.tcl
View File

@ -37,6 +37,7 @@ for {set n 0} {$n < 16} {incr n} {
"enb up_es_enb_${n} "\ "enb up_es_enb_${n} "\
"addr up_es_addr_${n} "\ "addr up_es_addr_${n} "\
"wr up_es_wr_${n} "\ "wr up_es_wr_${n} "\
"reset up_es_reset_${n} "\
"wdata up_es_wdata_${n} "\ "wdata up_es_wdata_${n} "\
"rdata up_es_rdata_${n} "\ "rdata up_es_rdata_${n} "\
"ready up_es_ready_${n} "] "ready up_es_ready_${n} "]

7
library/xilinx/axi_adxcvr/axi_adxcvr_up.v
View File

@ -87,6 +87,7 @@ module axi_adxcvr_up #(
output [ 7:0] up_es_sel, output [ 7:0] up_es_sel,
output up_es_req, output up_es_req,
output [15:0] up_es_reset,
input up_es_ack, input up_es_ack,
output [ 4:0] up_es_pscale, output [ 4:0] up_es_pscale,
output [ 1:0] up_es_vrange, output [ 1:0] up_es_vrange,
@ -163,6 +164,7 @@ module axi_adxcvr_up #(
reg up_ies_status = 'd0; reg up_ies_status = 'd0;
reg up_rreq_d = 'd0; reg up_rreq_d = 'd0;
reg [31:0] up_rdata_d = 'd0; reg [31:0] up_rdata_d = 'd0;
reg [15:0] up_es_reset = 'd0;
// internal signals // internal signals
@ -423,6 +425,7 @@ module axi_adxcvr_up #(
up_ies_hoffset_step <= 'd0; up_ies_hoffset_step <= 'd0;
up_ies_start_addr <= 'd0; up_ies_start_addr <= 'd0;
up_ies_status <= 'd0; up_ies_status <= 'd0;
up_es_reset <= 'd0;
end else begin end else begin
if ((up_wreq == 1'b1) && (up_waddr == 10'h020)) begin if ((up_wreq == 1'b1) && (up_waddr == 10'h020)) begin
up_ies_sel <= up_wdata[7:0]; up_ies_sel <= up_wdata[7:0];
@ -456,6 +459,9 @@ module axi_adxcvr_up #(
end else if ((up_wreq == 1'b1) && (up_waddr == 10'h02e)) begin end else if ((up_wreq == 1'b1) && (up_waddr == 10'h02e)) begin
up_ies_status <= up_ies_status & ~up_wdata[0]; up_ies_status <= up_ies_status & ~up_wdata[0];
end end
if ((up_wreq == 1'b1) && (up_waddr == 10'h02f)) begin
up_es_reset <= up_wdata[15:0];
end
end end
end end
end end
@ -512,6 +518,7 @@ module axi_adxcvr_up #(
10'h02c: up_rdata_d <= {20'd0, up_ies_hoffset_step}; 10'h02c: up_rdata_d <= {20'd0, up_ies_hoffset_step};
10'h02d: up_rdata_d <= up_ies_start_addr; 10'h02d: up_rdata_d <= up_ies_start_addr;
10'h02e: up_rdata_d <= {31'd0, up_es_status}; 10'h02e: up_rdata_d <= {31'd0, up_es_status};
10'h02f: up_rdata_d <= {16'd0, up_es_reset};
10'h030: up_rdata_d <= up_tx_diffctrl; 10'h030: up_rdata_d <= up_tx_diffctrl;
10'h031: up_rdata_d <= up_tx_postcursor; 10'h031: up_rdata_d <= up_tx_postcursor;
10'h032: up_rdata_d <= up_tx_precursor; 10'h032: up_rdata_d <= up_tx_precursor;

32
library/xilinx/util_adxcvr/util_adxcvr.v
View File

@ -119,6 +119,7 @@ module util_adxcvr #(
input [15:0] up_es_wdata_0, input [15:0] up_es_wdata_0,
output [15:0] up_es_rdata_0, output [15:0] up_es_rdata_0,
output up_es_ready_0, output up_es_ready_0,
input up_es_reset_0,
output up_rx_pll_locked_0, output up_rx_pll_locked_0,
input up_rx_rst_0, input up_rx_rst_0,
input up_rx_user_ready_0, input up_rx_user_ready_0,
@ -177,6 +178,7 @@ module util_adxcvr #(
input [15:0] up_es_wdata_1, input [15:0] up_es_wdata_1,
output [15:0] up_es_rdata_1, output [15:0] up_es_rdata_1,
output up_es_ready_1, output up_es_ready_1,
input up_es_reset_1,
output up_rx_pll_locked_1, output up_rx_pll_locked_1,
input up_rx_rst_1, input up_rx_rst_1,
input up_rx_user_ready_1, input up_rx_user_ready_1,
@ -235,6 +237,7 @@ module util_adxcvr #(
input [15:0] up_es_wdata_2, input [15:0] up_es_wdata_2,
output [15:0] up_es_rdata_2, output [15:0] up_es_rdata_2,
output up_es_ready_2, output up_es_ready_2,
input up_es_reset_2,
output up_rx_pll_locked_2, output up_rx_pll_locked_2,
input up_rx_rst_2, input up_rx_rst_2,
input up_rx_user_ready_2, input up_rx_user_ready_2,
@ -293,6 +296,7 @@ module util_adxcvr #(
input [15:0] up_es_wdata_3, input [15:0] up_es_wdata_3,
output [15:0] up_es_rdata_3, output [15:0] up_es_rdata_3,
output up_es_ready_3, output up_es_ready_3,
input up_es_reset_3,
output up_rx_pll_locked_3, output up_rx_pll_locked_3,
input up_rx_rst_3, input up_rx_rst_3,
input up_rx_user_ready_3, input up_rx_user_ready_3,
@ -359,6 +363,7 @@ module util_adxcvr #(
input [15:0] up_es_wdata_4, input [15:0] up_es_wdata_4,
output [15:0] up_es_rdata_4, output [15:0] up_es_rdata_4,
output up_es_ready_4, output up_es_ready_4,
input up_es_reset_4,
output up_rx_pll_locked_4, output up_rx_pll_locked_4,
input up_rx_rst_4, input up_rx_rst_4,
input up_rx_user_ready_4, input up_rx_user_ready_4,
@ -417,6 +422,7 @@ module util_adxcvr #(
input [15:0] up_es_wdata_5, input [15:0] up_es_wdata_5,
output [15:0] up_es_rdata_5, output [15:0] up_es_rdata_5,
output up_es_ready_5, output up_es_ready_5,
input up_es_reset_5,
output up_rx_pll_locked_5, output up_rx_pll_locked_5,
input up_rx_rst_5, input up_rx_rst_5,
input up_rx_user_ready_5, input up_rx_user_ready_5,
@ -475,6 +481,7 @@ module util_adxcvr #(
input [15:0] up_es_wdata_6, input [15:0] up_es_wdata_6,
output [15:0] up_es_rdata_6, output [15:0] up_es_rdata_6,
output up_es_ready_6, output up_es_ready_6,
input up_es_reset_6,
output up_rx_pll_locked_6, output up_rx_pll_locked_6,
input up_rx_rst_6, input up_rx_rst_6,
input up_rx_user_ready_6, input up_rx_user_ready_6,
@ -533,6 +540,7 @@ module util_adxcvr #(
input [15:0] up_es_wdata_7, input [15:0] up_es_wdata_7,
output [15:0] up_es_rdata_7, output [15:0] up_es_rdata_7,
output up_es_ready_7, output up_es_ready_7,
input up_es_reset_7,
output up_rx_pll_locked_7, output up_rx_pll_locked_7,
input up_rx_rst_7, input up_rx_rst_7,
input up_rx_user_ready_7, input up_rx_user_ready_7,
@ -599,6 +607,7 @@ module util_adxcvr #(
input [15:0] up_es_wdata_8, input [15:0] up_es_wdata_8,
output [15:0] up_es_rdata_8, output [15:0] up_es_rdata_8,
output up_es_ready_8, output up_es_ready_8,
input up_es_reset_8,
output up_rx_pll_locked_8, output up_rx_pll_locked_8,
input up_rx_rst_8, input up_rx_rst_8,
input up_rx_user_ready_8, input up_rx_user_ready_8,
@ -657,6 +666,7 @@ module util_adxcvr #(
input [15:0] up_es_wdata_9, input [15:0] up_es_wdata_9,
output [15:0] up_es_rdata_9, output [15:0] up_es_rdata_9,
output up_es_ready_9, output up_es_ready_9,
input up_es_reset_9,
output up_rx_pll_locked_9, output up_rx_pll_locked_9,
input up_rx_rst_9, input up_rx_rst_9,
input up_rx_user_ready_9, input up_rx_user_ready_9,
@ -715,6 +725,7 @@ module util_adxcvr #(
input [15:0] up_es_wdata_10, input [15:0] up_es_wdata_10,
output [15:0] up_es_rdata_10, output [15:0] up_es_rdata_10,
output up_es_ready_10, output up_es_ready_10,
input up_es_reset_10,
output up_rx_pll_locked_10, output up_rx_pll_locked_10,
input up_rx_rst_10, input up_rx_rst_10,
input up_rx_user_ready_10, input up_rx_user_ready_10,
@ -773,6 +784,7 @@ module util_adxcvr #(
input [15:0] up_es_wdata_11, input [15:0] up_es_wdata_11,
output [15:0] up_es_rdata_11, output [15:0] up_es_rdata_11,
output up_es_ready_11, output up_es_ready_11,
input up_es_reset_11,
output up_rx_pll_locked_11, output up_rx_pll_locked_11,
input up_rx_rst_11, input up_rx_rst_11,
input up_rx_user_ready_11, input up_rx_user_ready_11,
@ -839,6 +851,7 @@ module util_adxcvr #(
input [15:0] up_es_wdata_12, input [15:0] up_es_wdata_12,
output [15:0] up_es_rdata_12, output [15:0] up_es_rdata_12,
output up_es_ready_12, output up_es_ready_12,
input up_es_reset_12,
output up_rx_pll_locked_12, output up_rx_pll_locked_12,
input up_rx_rst_12, input up_rx_rst_12,
input up_rx_user_ready_12, input up_rx_user_ready_12,
@ -897,6 +910,7 @@ module util_adxcvr #(
input [15:0] up_es_wdata_13, input [15:0] up_es_wdata_13,
output [15:0] up_es_rdata_13, output [15:0] up_es_rdata_13,
output up_es_ready_13, output up_es_ready_13,
input up_es_reset_13,
output up_rx_pll_locked_13, output up_rx_pll_locked_13,
input up_rx_rst_13, input up_rx_rst_13,
input up_rx_user_ready_13, input up_rx_user_ready_13,
@ -955,6 +969,7 @@ module util_adxcvr #(
input [15:0] up_es_wdata_14, input [15:0] up_es_wdata_14,
output [15:0] up_es_rdata_14, output [15:0] up_es_rdata_14,
output up_es_ready_14, output up_es_ready_14,
input up_es_reset_14,
output up_rx_pll_locked_14, output up_rx_pll_locked_14,
input up_rx_rst_14, input up_rx_rst_14,
input up_rx_user_ready_14, input up_rx_user_ready_14,
@ -1013,6 +1028,7 @@ module util_adxcvr #(
input [15:0] up_es_wdata_15, input [15:0] up_es_wdata_15,
output [15:0] up_es_rdata_15, output [15:0] up_es_rdata_15,
output up_es_ready_15, output up_es_ready_15,
input up_es_reset_15,
output up_rx_pll_locked_15, output up_rx_pll_locked_15,
input up_rx_rst_15, input up_rx_rst_15,
input up_rx_user_ready_15, input up_rx_user_ready_15,
@ -1153,6 +1169,7 @@ module util_adxcvr #(
.up_es_wdata (up_es_wdata_0), .up_es_wdata (up_es_wdata_0),
.up_es_rdata (up_es_rdata_0), .up_es_rdata (up_es_rdata_0),
.up_es_ready (up_es_ready_0), .up_es_ready (up_es_ready_0),
.up_es_reset (up_es_reset_0),
.up_rx_pll_locked (up_rx_pll_locked_0), .up_rx_pll_locked (up_rx_pll_locked_0),
.up_rx_rst (up_rx_rst_0), .up_rx_rst (up_rx_rst_0),
.up_rx_user_ready (up_rx_user_ready_0), .up_rx_user_ready (up_rx_user_ready_0),
@ -1255,6 +1272,7 @@ module util_adxcvr #(
.up_es_wdata (up_es_wdata_1), .up_es_wdata (up_es_wdata_1),
.up_es_rdata (up_es_rdata_1), .up_es_rdata (up_es_rdata_1),
.up_es_ready (up_es_ready_1), .up_es_ready (up_es_ready_1),
.up_es_reset (up_es_reset_1),
.up_rx_pll_locked (up_rx_pll_locked_1), .up_rx_pll_locked (up_rx_pll_locked_1),
.up_rx_rst (up_rx_rst_1), .up_rx_rst (up_rx_rst_1),
.up_rx_user_ready (up_rx_user_ready_1), .up_rx_user_ready (up_rx_user_ready_1),
@ -1357,6 +1375,7 @@ module util_adxcvr #(
.up_es_wdata (up_es_wdata_2), .up_es_wdata (up_es_wdata_2),
.up_es_rdata (up_es_rdata_2), .up_es_rdata (up_es_rdata_2),
.up_es_ready (up_es_ready_2), .up_es_ready (up_es_ready_2),
.up_es_reset (up_es_reset_2),
.up_rx_pll_locked (up_rx_pll_locked_2), .up_rx_pll_locked (up_rx_pll_locked_2),
.up_rx_rst (up_rx_rst_2), .up_rx_rst (up_rx_rst_2),
.up_rx_user_ready (up_rx_user_ready_2), .up_rx_user_ready (up_rx_user_ready_2),
@ -1459,6 +1478,7 @@ module util_adxcvr #(
.up_es_wdata (up_es_wdata_3), .up_es_wdata (up_es_wdata_3),
.up_es_rdata (up_es_rdata_3), .up_es_rdata (up_es_rdata_3),
.up_es_ready (up_es_ready_3), .up_es_ready (up_es_ready_3),
.up_es_reset (up_es_reset_3),
.up_rx_pll_locked (up_rx_pll_locked_3), .up_rx_pll_locked (up_rx_pll_locked_3),
.up_rx_rst (up_rx_rst_3), .up_rx_rst (up_rx_rst_3),
.up_rx_user_ready (up_rx_user_ready_3), .up_rx_user_ready (up_rx_user_ready_3),
@ -1598,6 +1618,7 @@ module util_adxcvr #(
.up_es_wdata (up_es_wdata_4), .up_es_wdata (up_es_wdata_4),
.up_es_rdata (up_es_rdata_4), .up_es_rdata (up_es_rdata_4),
.up_es_ready (up_es_ready_4), .up_es_ready (up_es_ready_4),
.up_es_reset (up_es_reset_4),
.up_rx_pll_locked (up_rx_pll_locked_4), .up_rx_pll_locked (up_rx_pll_locked_4),
.up_rx_rst (up_rx_rst_4), .up_rx_rst (up_rx_rst_4),
.up_rx_user_ready (up_rx_user_ready_4), .up_rx_user_ready (up_rx_user_ready_4),
@ -1700,6 +1721,7 @@ module util_adxcvr #(
.up_es_wdata (up_es_wdata_5), .up_es_wdata (up_es_wdata_5),
.up_es_rdata (up_es_rdata_5), .up_es_rdata (up_es_rdata_5),
.up_es_ready (up_es_ready_5), .up_es_ready (up_es_ready_5),
.up_es_reset (up_es_reset_5),
.up_rx_pll_locked (up_rx_pll_locked_5), .up_rx_pll_locked (up_rx_pll_locked_5),
.up_rx_rst (up_rx_rst_5), .up_rx_rst (up_rx_rst_5),
.up_rx_user_ready (up_rx_user_ready_5), .up_rx_user_ready (up_rx_user_ready_5),
@ -1802,6 +1824,7 @@ module util_adxcvr #(
.up_es_wdata (up_es_wdata_6), .up_es_wdata (up_es_wdata_6),
.up_es_rdata (up_es_rdata_6), .up_es_rdata (up_es_rdata_6),
.up_es_ready (up_es_ready_6), .up_es_ready (up_es_ready_6),
.up_es_reset (up_es_reset_6),
.up_rx_pll_locked (up_rx_pll_locked_6), .up_rx_pll_locked (up_rx_pll_locked_6),
.up_rx_rst (up_rx_rst_6), .up_rx_rst (up_rx_rst_6),
.up_rx_user_ready (up_rx_user_ready_6), .up_rx_user_ready (up_rx_user_ready_6),
@ -1904,6 +1927,7 @@ module util_adxcvr #(
.up_es_wdata (up_es_wdata_7), .up_es_wdata (up_es_wdata_7),
.up_es_rdata (up_es_rdata_7), .up_es_rdata (up_es_rdata_7),
.up_es_ready (up_es_ready_7), .up_es_ready (up_es_ready_7),
.up_es_reset (up_es_reset_7),
.up_rx_pll_locked (up_rx_pll_locked_7), .up_rx_pll_locked (up_rx_pll_locked_7),
.up_rx_rst (up_rx_rst_7), .up_rx_rst (up_rx_rst_7),
.up_rx_user_ready (up_rx_user_ready_7), .up_rx_user_ready (up_rx_user_ready_7),
@ -2043,6 +2067,7 @@ module util_adxcvr #(
.up_es_wdata (up_es_wdata_8), .up_es_wdata (up_es_wdata_8),
.up_es_rdata (up_es_rdata_8), .up_es_rdata (up_es_rdata_8),
.up_es_ready (up_es_ready_8), .up_es_ready (up_es_ready_8),
.up_es_reset (up_es_reset_8),
.up_rx_pll_locked (up_rx_pll_locked_8), .up_rx_pll_locked (up_rx_pll_locked_8),
.up_rx_rst (up_rx_rst_8), .up_rx_rst (up_rx_rst_8),
.up_rx_user_ready (up_rx_user_ready_8), .up_rx_user_ready (up_rx_user_ready_8),
@ -2145,6 +2170,7 @@ module util_adxcvr #(
.up_es_wdata (up_es_wdata_9), .up_es_wdata (up_es_wdata_9),
.up_es_rdata (up_es_rdata_9), .up_es_rdata (up_es_rdata_9),
.up_es_ready (up_es_ready_9), .up_es_ready (up_es_ready_9),
.up_es_reset (up_es_reset_9),
.up_rx_pll_locked (up_rx_pll_locked_9), .up_rx_pll_locked (up_rx_pll_locked_9),
.up_rx_rst (up_rx_rst_9), .up_rx_rst (up_rx_rst_9),
.up_rx_user_ready (up_rx_user_ready_9), .up_rx_user_ready (up_rx_user_ready_9),
@ -2247,6 +2273,7 @@ module util_adxcvr #(
.up_es_wdata (up_es_wdata_10), .up_es_wdata (up_es_wdata_10),
.up_es_rdata (up_es_rdata_10), .up_es_rdata (up_es_rdata_10),
.up_es_ready (up_es_ready_10), .up_es_ready (up_es_ready_10),
.up_es_reset (up_es_reset_10),
.up_rx_pll_locked (up_rx_pll_locked_10), .up_rx_pll_locked (up_rx_pll_locked_10),
.up_rx_rst (up_rx_rst_10), .up_rx_rst (up_rx_rst_10),
.up_rx_user_ready (up_rx_user_ready_10), .up_rx_user_ready (up_rx_user_ready_10),
@ -2349,6 +2376,7 @@ module util_adxcvr #(
.up_es_wdata (up_es_wdata_11), .up_es_wdata (up_es_wdata_11),
.up_es_rdata (up_es_rdata_11), .up_es_rdata (up_es_rdata_11),
.up_es_ready (up_es_ready_11), .up_es_ready (up_es_ready_11),
.up_es_reset (up_es_reset_11),
.up_rx_pll_locked (up_rx_pll_locked_11), .up_rx_pll_locked (up_rx_pll_locked_11),
.up_rx_rst (up_rx_rst_11), .up_rx_rst (up_rx_rst_11),
.up_rx_user_ready (up_rx_user_ready_11), .up_rx_user_ready (up_rx_user_ready_11),
@ -2488,6 +2516,7 @@ module util_adxcvr #(
.up_es_wdata (up_es_wdata_12), .up_es_wdata (up_es_wdata_12),
.up_es_rdata (up_es_rdata_12), .up_es_rdata (up_es_rdata_12),
.up_es_ready (up_es_ready_12), .up_es_ready (up_es_ready_12),
.up_es_reset (up_es_reset_12),
.up_rx_pll_locked (up_rx_pll_locked_12), .up_rx_pll_locked (up_rx_pll_locked_12),
.up_rx_rst (up_rx_rst_12), .up_rx_rst (up_rx_rst_12),
.up_rx_user_ready (up_rx_user_ready_12), .up_rx_user_ready (up_rx_user_ready_12),
@ -2590,6 +2619,7 @@ module util_adxcvr #(
.up_es_wdata (up_es_wdata_13), .up_es_wdata (up_es_wdata_13),
.up_es_rdata (up_es_rdata_13), .up_es_rdata (up_es_rdata_13),
.up_es_ready (up_es_ready_13), .up_es_ready (up_es_ready_13),
.up_es_reset (up_es_reset_13),
.up_rx_pll_locked (up_rx_pll_locked_13), .up_rx_pll_locked (up_rx_pll_locked_13),
.up_rx_rst (up_rx_rst_13), .up_rx_rst (up_rx_rst_13),
.up_rx_user_ready (up_rx_user_ready_13), .up_rx_user_ready (up_rx_user_ready_13),
@ -2692,6 +2722,7 @@ module util_adxcvr #(
.up_es_wdata (up_es_wdata_14), .up_es_wdata (up_es_wdata_14),
.up_es_rdata (up_es_rdata_14), .up_es_rdata (up_es_rdata_14),
.up_es_ready (up_es_ready_14), .up_es_ready (up_es_ready_14),
.up_es_reset (up_es_reset_14),
.up_rx_pll_locked (up_rx_pll_locked_14), .up_rx_pll_locked (up_rx_pll_locked_14),
.up_rx_rst (up_rx_rst_14), .up_rx_rst (up_rx_rst_14),
.up_rx_user_ready (up_rx_user_ready_14), .up_rx_user_ready (up_rx_user_ready_14),
@ -2794,6 +2825,7 @@ module util_adxcvr #(
.up_es_wdata (up_es_wdata_15), .up_es_wdata (up_es_wdata_15),
.up_es_rdata (up_es_rdata_15), .up_es_rdata (up_es_rdata_15),
.up_es_ready (up_es_ready_15), .up_es_ready (up_es_ready_15),
.up_es_reset (up_es_reset_15),
.up_rx_pll_locked (up_rx_pll_locked_15), .up_rx_pll_locked (up_rx_pll_locked_15),
.up_rx_rst (up_rx_rst_15), .up_rx_rst (up_rx_rst_15),
.up_rx_user_ready (up_rx_user_ready_15), .up_rx_user_ready (up_rx_user_ready_15),

1
library/xilinx/util_adxcvr/util_adxcvr_ip.tcl
View File

@ -161,6 +161,7 @@ for {set n 0} {$n < 16} {incr n} {
"wr up_es_wr_${n} "\ "wr up_es_wr_${n} "\
"wdata up_es_wdata_${n} "\ "wdata up_es_wdata_${n} "\
"rdata up_es_rdata_${n} "\ "rdata up_es_rdata_${n} "\
"reset up_es_reset_${n} "\
"ready up_es_ready_${n} "] "ready up_es_ready_${n} "]
adi_if_infer_bus analog.com:interface:if_xcvr_ch slave up_rx_${n} [list \ adi_if_infer_bus analog.com:interface:if_xcvr_ch slave up_rx_${n} [list \

3
library/xilinx/util_adxcvr/util_adxcvr_xch.v
View File

@ -100,6 +100,7 @@ module util_adxcvr_xch #(
input [15:0] up_es_wdata, input [15:0] up_es_wdata,
output [15:0] up_es_rdata, output [15:0] up_es_rdata,
output up_es_ready, output up_es_ready,
input up_es_reset,
output up_rx_pll_locked, output up_rx_pll_locked,
input up_rx_rst, input up_rx_rst,
input up_rx_user_ready, input up_rx_user_ready,
@ -2070,7 +2071,7 @@ module util_adxcvr_xch #(
.DRPRST (1'd0), .DRPRST (1'd0),
.DRPWE (up_wr_int), .DRPWE (up_wr_int),
.EYESCANDATAERROR (), .EYESCANDATAERROR (),
.EYESCANRESET (1'd0), .EYESCANRESET (up_es_reset),
.EYESCANTRIGGER (1'd0), .EYESCANTRIGGER (1'd0),
.FREQOS (1'd0), .FREQOS (1'd0),
.GTGREFCLK (1'd0), .GTGREFCLK (1'd0),