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altera: axi_adxcvr: Reduce register map interface address width 

The axi_adxcvr register map only uses a single 4k page, make this explicit.

This will allow for tighter packaging in the limited available total
register map space.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2017-07-24 15:04:44 +02:00
parent 8b31fe73e0
commit e1e0406a49
2 changed files with 8 additions and 5 deletions
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9
library/altera/axi_adxcvr/axi_adxcvr.v
View File

@ -52,7 +52,7 @@ module axi_adxcvr #(
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [31:0] s_axi_awaddr,
input [11:0] s_axi_awaddr,
input [ 2:0] s_axi_awprot,
output s_axi_awready,
input s_axi_wvalid,
@ -63,7 +63,7 @@ module axi_adxcvr #(
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [31:0] s_axi_araddr,
input [11:0] s_axi_araddr,
input [ 2:0] s_axi_arprot,
output s_axi_arready,
output s_axi_rvalid,
@ -110,7 +110,10 @@ module axi_adxcvr #(
.up_rdata (up_rdata),
.up_rack (up_rack));
up_axi #(.ADDRESS_WIDTH (10)) i_axi (
up_axi #(
.ADDRESS_WIDTH (10),
.AXI_ADDRESS_WIDTH (12)
) i_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),

4
library/altera/axi_adxcvr/axi_adxcvr_hw.tcl
View File

@ -52,7 +52,7 @@ add_interface s_axi axi4lite end
set_interface_property s_axi associatedClock s_axi_clock
set_interface_property s_axi associatedReset s_axi_reset
add_interface_port s_axi s_axi_awvalid awvalid Input 1
add_interface_port s_axi s_axi_awaddr awaddr Input 16
add_interface_port s_axi s_axi_awaddr awaddr Input 12
add_interface_port s_axi s_axi_awprot awprot Input 3
add_interface_port s_axi s_axi_awready awready Output 1
add_interface_port s_axi s_axi_wvalid wvalid Input 1
@ -63,7 +63,7 @@ add_interface_port s_axi s_axi_bvalid bvalid Output 1
add_interface_port s_axi s_axi_bresp bresp Output 2
add_interface_port s_axi s_axi_bready bready Input 1
add_interface_port s_axi s_axi_arvalid arvalid Input 1
add_interface_port s_axi s_axi_araddr araddr Input 16
add_interface_port s_axi s_axi_araddr araddr Input 12
add_interface_port s_axi s_axi_arprot arprot Input 3
add_interface_port s_axi s_axi_arready arready Output 1
add_interface_port s_axi s_axi_rvalid rvalid Output 1