daq2: Initial check in of the VC707 based project
NOTE: Can not communicate with the clock chip, rx/tx PLL not locking.main
Istvan Csomortani
parent
96899313d8
commit
e1d8dd10a9
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@ -0,0 +1,9 @@
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source $ad_hdl_dir/projects/common/vc707/vc707_system_bd.tcl
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source $ad_hdl_dir/projects/common/xilinx/sys_dmafifo.tcl
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p_sys_dmafifo [current_bd_instance .] axi_ad9680_fifo 128 16
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source ../common/daq2_bd.tcl
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@ -0,0 +1,62 @@
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# daq2
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set_property -dict {PACKAGE_PIN E10} [get_ports rx_ref_clk_p] ; ## B20 FMC_HPC_GBTCLK1_M2C_P
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set_property -dict {PACKAGE_PIN E9 } [get_ports rx_ref_clk_n] ; ## B21 FMC_HPC_GBTCLK1_M2C_N
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set_property -dict {PACKAGE_PIN A6 } [get_ports rx_data_p[0]] ; ## A10 FMC_HPC_DP3_M2C_P
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set_property -dict {PACKAGE_PIN A5 } [get_ports rx_data_n[0]] ; ## A11 FMC_HPC_DP3_M2C_N
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set_property -dict {PACKAGE_PIN D8 } [get_ports rx_data_p[1]] ; ## C06 FMC_HPC_DP0_M2C_P
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set_property -dict {PACKAGE_PIN D7 } [get_ports rx_data_n[1]] ; ## C07 FMC_HPC_DP0_M2C_N
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set_property -dict {PACKAGE_PIN B8 } [get_ports rx_data_p[2]] ; ## A06 FMC_HPC_DP2_M2C_P
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set_property -dict {PACKAGE_PIN B7 } [get_ports rx_data_n[2]] ; ## A07 FMC_HPC_DP2_M2C_N
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set_property -dict {PACKAGE_PIN C6 } [get_ports rx_data_p[3]] ; ## A02 FMC_HPC_DP1_M2C_P
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set_property -dict {PACKAGE_PIN C5 } [get_ports rx_data_n[3]] ; ## A03 FMC_HPC_DP1_M2C_N
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set_property -dict {PACKAGE_PIN J40 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_sync_p] ; ## D08 FMC_HPC_LA01_CC_P
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set_property -dict {PACKAGE_PIN J41 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_sync_n] ; ## D09 FMC_HPC_LA01_CC_N
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set_property -dict {PACKAGE_PIN M42 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_sysref_p] ; ## G09 FMC_HPC_LA03_P
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set_property -dict {PACKAGE_PIN L42 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_sysref_n] ; ## G10 FMC_HPC_LA03_N
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set_property -dict {PACKAGE_PIN A10} [get_ports tx_ref_clk_p] ; ## D04 FMC_HPC_GBTCLK0_M2C_P
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set_property -dict {PACKAGE_PIN A9 } [get_ports tx_ref_clk_n] ; ## D05 FMC_HPC_GBTCLK0_M2C_N
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set_property -dict {PACKAGE_PIN B4} [get_ports tx_data_p[0]] ; ## A30 FMC_HPC_DP3_C2M_P (tx_data_p[0])
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set_property -dict {PACKAGE_PIN B3} [get_ports tx_data_n[0]] ; ## A31 FMC_HPC_DP3_C2M_N (tx_data_n[0])
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set_property -dict {PACKAGE_PIN E2} [get_ports tx_data_p[1]] ; ## C02 FMC_HPC_DP0_C2M_P (tx_data_p[3])
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set_property -dict {PACKAGE_PIN E1} [get_ports tx_data_n[1]] ; ## C03 FMC_HPC_DP0_C2M_N (tx_data_n[3])
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set_property -dict {PACKAGE_PIN C2} [get_ports tx_data_p[2]] ; ## A26 FMC_HPC_DP2_C2M_P (tx_data_p[1])
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set_property -dict {PACKAGE_PIN C1} [get_ports tx_data_n[2]] ; ## A27 FMC_HPC_DP2_C2M_N (tx_data_n[1])
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set_property -dict {PACKAGE_PIN D4} [get_ports tx_data_p[3]] ; ## A22 FMC_HPC_DP1_C2M_P (tx_data_p[2])
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set_property -dict {PACKAGE_PIN D3} [get_ports tx_data_n[3]] ; ## A23 FMC_HPC_DP1_C2M_N (tx_data_n[2])
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set_property -dict {PACKAGE_PIN P41 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports tx_sync_p] ; ## H07 FMC_HPC_LA02_P
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set_property -dict {PACKAGE_PIN N41 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports tx_sync_n] ; ## H08 FMC_HPC_LA02_N
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set_property -dict {PACKAGE_PIN H40 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports tx_sysref_p] ; ## H10 FMC_HPC_LA04_P
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set_property -dict {PACKAGE_PIN H41 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports tx_sysref_n] ; ## H11 FMC_HPC_LA04_N
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set_property -dict {PACKAGE_PIN M41 IOSTANDARD LVCMOS18} [get_ports spi_csn_clk] ; ## D11 FMC_HPC_LA05_P
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set_property -dict {PACKAGE_PIN N38 IOSTANDARD LVCMOS18} [get_ports spi_csn_dac] ; ## C14 FMC_HPC_LA10_P
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set_property -dict {PACKAGE_PIN P42 IOSTANDARD LVCMOS18} [get_ports spi_csn_adc] ; ## D15 FMC_HPC_LA09_N
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set_property -dict {PACKAGE_PIN L41 IOSTANDARD LVCMOS18} [get_ports spi_clk] ; ## D12 FMC_HPC_LA05_N
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set_property -dict {PACKAGE_PIN R42 IOSTANDARD LVCMOS18} [get_ports spi_sdio] ; ## D14 FMC_HPC_LA09_P
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set_property -dict {PACKAGE_PIN M38 IOSTANDARD LVCMOS18} [get_ports spi_dir] ; ## G13 FMC_HPC_LA08_N
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set_property -dict {PACKAGE_PIN M37 IOSTANDARD LVCMOS18} [get_ports clkd_sync] ; ## G12 FMC_HPC_LA08_P
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set_property -dict {PACKAGE_PIN M39 IOSTANDARD LVCMOS18} [get_ports dac_reset] ; ## C15 FMC_HPC_LA10_N
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set_property -dict {PACKAGE_PIN P40 IOSTANDARD LVCMOS18} [get_ports dac_txen] ; ## G16 FMC_HPC_LA12_N
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set_property -dict {PACKAGE_PIN K42 IOSTANDARD LVCMOS18} [get_ports adc_pd] ; ## C10 FMC_HPC_LA06_P
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set_property -dict {PACKAGE_PIN H39 IOSTANDARD LVCMOS18} [get_ports clkd_status[0]] ; ## D17 FMC_HPC_LA13_P
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set_property -dict {PACKAGE_PIN G39 IOSTANDARD LVCMOS18} [get_ports clkd_status[1]] ; ## D18 FMC_HPC_LA13_N
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set_property -dict {PACKAGE_PIN R40 IOSTANDARD LVCMOS18} [get_ports dac_irq] ; ## G15 FMC_HPC_LA12_P
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set_property -dict {PACKAGE_PIN F40 IOSTANDARD LVCMOS18} [get_ports adc_fda] ; ## H16 FMC_HPC_LA11_P
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set_property -dict {PACKAGE_PIN F41 IOSTANDARD LVCMOS18} [get_ports adc_fdb] ; ## H17 FMC_HPC_LA11_N
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set_property -dict {PACKAGE_PIN G41 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports trig_p] ; ## H13 FMC_HPC_LA07_P
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set_property -dict {PACKAGE_PIN G42 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports trig_n] ; ## H14 FMC_HPC_LA07_N
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# clocks
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create_clock -name tx_ref_clk -period 2.00 [get_ports tx_ref_clk_p]
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create_clock -name rx_ref_clk -period 2.00 [get_ports rx_ref_clk_p]
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create_clock -name tx_div_clk -period 4.00 [get_nets i_system_wrapper/system_i/axi_daq2_gt_tx_clk]
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create_clock -name rx_div_clk -period 4.00 [get_nets i_system_wrapper/system_i/axi_daq2_gt_rx_clk]
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source ../../scripts/adi_env.tcl
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source $ad_hdl_dir/projects/scripts/adi_project.tcl
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adi_project_create daq2_vc707
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adi_project_files daq2_vc707 [list \
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"../common/daq2_spi.v" \
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"system_top.v" \
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"system_constr.xdc"\
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"$ad_hdl_dir/library/common/ad_iobuf.v" \
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"$ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc" ]
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set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc]
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set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc]
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adi_project_run daq2_vc707
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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sys_rst,
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sys_clk_p,
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sys_clk_n,
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uart_sin,
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uart_sout,
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ddr3_addr,
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ddr3_ba,
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ddr3_cas_n,
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ddr3_ck_n,
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ddr3_ck_p,
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ddr3_cke,
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ddr3_cs_n,
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ddr3_dm,
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ddr3_dq,
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ddr3_dqs_n,
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ddr3_dqs_p,
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ddr3_odt,
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ddr3_ras_n,
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ddr3_reset_n,
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ddr3_we_n,
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sgmii_rxp,
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sgmii_rxn,
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sgmii_txp,
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sgmii_txn,
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phy_rstn,
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mgt_clk_p,
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mgt_clk_n,
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mdio_mdc,
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mdio_mdio,
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fan_pwm,
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linear_flash_addr,
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linear_flash_adv_ldn,
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linear_flash_ce_n,
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linear_flash_oen,
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linear_flash_wen,
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linear_flash_dq_io,
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gpio_lcd,
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gpio_led,
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gpio_sw,
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iic_rstn,
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iic_scl,
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iic_sda,
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hdmi_out_clk,
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hdmi_hsync,
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hdmi_vsync,
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hdmi_data_e,
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hdmi_data,
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spdif,
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rx_ref_clk_p,
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rx_ref_clk_n,
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rx_sysref_p,
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rx_sysref_n,
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rx_sync_p,
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rx_sync_n,
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rx_data_p,
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rx_data_n,
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tx_ref_clk_p,
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tx_ref_clk_n,
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tx_sysref_p,
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tx_sysref_n,
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tx_sync_p,
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tx_sync_n,
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tx_data_p,
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tx_data_n,
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trig_p,
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trig_n,
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adc_fdb,
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adc_fda,
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dac_irq,
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clkd_status,
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adc_pd,
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dac_txen,
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dac_reset,
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clkd_sync,
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spi_csn_clk,
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spi_csn_dac,
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spi_csn_adc,
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spi_clk,
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spi_sdio,
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spi_dir);
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input sys_rst;
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input sys_clk_p;
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input sys_clk_n;
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input uart_sin;
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output uart_sout;
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output [13:0] ddr3_addr;
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output [ 2:0] ddr3_ba;
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output ddr3_cas_n;
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output [ 0:0] ddr3_ck_n;
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output [ 0:0] ddr3_ck_p;
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output [ 0:0] ddr3_cke;
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output [ 0:0] ddr3_cs_n;
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output [ 7:0] ddr3_dm;
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inout [63:0] ddr3_dq;
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inout [ 7:0] ddr3_dqs_n;
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inout [ 7:0] ddr3_dqs_p;
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output [ 0:0] ddr3_odt;
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output ddr3_ras_n;
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output ddr3_reset_n;
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output ddr3_we_n;
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input sgmii_rxp;
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input sgmii_rxn;
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output sgmii_txp;
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output sgmii_txn;
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output phy_rstn;
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input mgt_clk_p;
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input mgt_clk_n;
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output mdio_mdc;
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inout mdio_mdio;
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output fan_pwm;
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output [26:1] linear_flash_addr;
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output linear_flash_adv_ldn;
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output linear_flash_ce_n;
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output linear_flash_oen;
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output linear_flash_wen;
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inout [15:0] linear_flash_dq_io;
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output [ 6:0] gpio_lcd;
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output [ 7:0] gpio_led;
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input [12:0] gpio_sw;
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output iic_rstn;
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inout iic_scl;
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inout iic_sda;
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output hdmi_out_clk;
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output hdmi_hsync;
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output hdmi_vsync;
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output hdmi_data_e;
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output [35:0] hdmi_data;
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output spdif;
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input rx_ref_clk_p;
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input rx_ref_clk_n;
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input rx_sysref_p;
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input rx_sysref_n;
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output rx_sync_p;
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output rx_sync_n;
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input [ 3:0] rx_data_p;
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input [ 3:0] rx_data_n;
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input tx_ref_clk_p;
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input tx_ref_clk_n;
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input tx_sysref_p;
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input tx_sysref_n;
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input tx_sync_p;
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input tx_sync_n;
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output [ 3:0] tx_data_p;
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output [ 3:0] tx_data_n;
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input trig_p;
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input trig_n;
|
||||||
|
|
||||||
|
inout adc_fdb;
|
||||||
|
inout adc_fda;
|
||||||
|
inout dac_irq;
|
||||||
|
inout [ 1:0] clkd_status;
|
||||||
|
|
||||||
|
inout adc_pd;
|
||||||
|
inout dac_txen;
|
||||||
|
inout dac_reset;
|
||||||
|
inout clkd_sync;
|
||||||
|
|
||||||
|
output spi_csn_clk;
|
||||||
|
output spi_csn_dac;
|
||||||
|
output spi_csn_adc;
|
||||||
|
output spi_clk;
|
||||||
|
inout spi_sdio;
|
||||||
|
output spi_dir;
|
||||||
|
|
||||||
|
// internal registers
|
||||||
|
|
||||||
|
reg dac_drd = 'd0;
|
||||||
|
reg [63:0] dac_ddata_0 = 'd0;
|
||||||
|
reg [63:0] dac_ddata_1 = 'd0;
|
||||||
|
reg [63:0] dac_ddata_2 = 'd0;
|
||||||
|
reg [63:0] dac_ddata_3 = 'd0;
|
||||||
|
reg adc_dsync = 'd0;
|
||||||
|
reg adc_dwr = 'd0;
|
||||||
|
reg [127:0] adc_ddata = 'd0;
|
||||||
|
|
||||||
|
// internal signals
|
||||||
|
|
||||||
|
wire trig;
|
||||||
|
wire rx_ref_clk;
|
||||||
|
wire rx_sysref;
|
||||||
|
wire rx_sync;
|
||||||
|
wire tx_ref_clk;
|
||||||
|
wire tx_sysref;
|
||||||
|
wire tx_sync;
|
||||||
|
wire [ 2:0] spi_csn;
|
||||||
|
wire spi_mosi;
|
||||||
|
wire spi_miso;
|
||||||
|
wire dac_clk;
|
||||||
|
wire [127:0] dac_ddata;
|
||||||
|
wire dac_enable_0;
|
||||||
|
wire dac_enable_1;
|
||||||
|
wire dac_enable_2;
|
||||||
|
wire dac_enable_3;
|
||||||
|
wire dac_valid_0;
|
||||||
|
wire dac_valid_1;
|
||||||
|
wire dac_valid_2;
|
||||||
|
wire dac_valid_3;
|
||||||
|
wire adc_clk;
|
||||||
|
wire [63:0] adc_data_0;
|
||||||
|
wire [63:0] adc_data_1;
|
||||||
|
wire adc_enable_0;
|
||||||
|
wire adc_enable_1;
|
||||||
|
wire adc_valid_0;
|
||||||
|
wire adc_valid_1;
|
||||||
|
wire [ 5:0] gpio_ctl_i;
|
||||||
|
wire [ 5:0] gpio_ctl_o;
|
||||||
|
wire [ 5:0] gpio_ctl_t;
|
||||||
|
wire [ 4:0] gpio_status_i;
|
||||||
|
wire [ 4:0] gpio_status_o;
|
||||||
|
wire [ 4:0] gpio_status_t;
|
||||||
|
wire [31:0] mb_intrs;
|
||||||
|
|
||||||
|
// adc-dac data
|
||||||
|
|
||||||
|
always @(posedge dac_clk) begin
|
||||||
|
case ({dac_enable_1, dac_enable_0})
|
||||||
|
2'b11: begin
|
||||||
|
dac_drd <= dac_valid_0 & dac_valid_1;
|
||||||
|
dac_ddata_0[63:48] <= dac_ddata[111: 96];
|
||||||
|
dac_ddata_0[47:32] <= dac_ddata[ 79: 64];
|
||||||
|
dac_ddata_0[31:16] <= dac_ddata[ 47: 32];
|
||||||
|
dac_ddata_0[15: 0] <= dac_ddata[ 15: 0];
|
||||||
|
dac_ddata_1[63:48] <= dac_ddata[127:112];
|
||||||
|
dac_ddata_1[47:32] <= dac_ddata[ 95: 80];
|
||||||
|
dac_ddata_1[31:16] <= dac_ddata[ 63: 48];
|
||||||
|
dac_ddata_1[15: 0] <= dac_ddata[ 31: 16];
|
||||||
|
dac_ddata_2 <= 64'd0;
|
||||||
|
dac_ddata_3 <= 64'd0;
|
||||||
|
end
|
||||||
|
2'b10: begin
|
||||||
|
dac_drd <= dac_valid_1 & ~dac_drd;
|
||||||
|
dac_ddata_0 <= 64'd0;
|
||||||
|
if (dac_drd == 1'b1) begin
|
||||||
|
dac_ddata_1[63:48] <= dac_ddata[127:112];
|
||||||
|
dac_ddata_1[47:32] <= dac_ddata[111: 96];
|
||||||
|
dac_ddata_1[31:16] <= dac_ddata[ 95: 80];
|
||||||
|
dac_ddata_1[15: 0] <= dac_ddata[ 79: 64];
|
||||||
|
end else begin
|
||||||
|
dac_ddata_1[63:48] <= dac_ddata[ 63: 48];
|
||||||
|
dac_ddata_1[47:32] <= dac_ddata[ 47: 32];
|
||||||
|
dac_ddata_1[31:16] <= dac_ddata[ 31: 16];
|
||||||
|
dac_ddata_1[15: 0] <= dac_ddata[ 15: 0];
|
||||||
|
end
|
||||||
|
dac_ddata_2 <= 64'd0;
|
||||||
|
dac_ddata_3 <= 64'd0;
|
||||||
|
end
|
||||||
|
2'b01: begin
|
||||||
|
dac_drd <= dac_valid_0 & ~dac_drd;
|
||||||
|
if (dac_drd == 1'b1) begin
|
||||||
|
dac_ddata_0[63:48] <= dac_ddata[127:112];
|
||||||
|
dac_ddata_0[47:32] <= dac_ddata[111: 96];
|
||||||
|
dac_ddata_0[31:16] <= dac_ddata[ 95: 80];
|
||||||
|
dac_ddata_0[15: 0] <= dac_ddata[ 79: 64];
|
||||||
|
end else begin
|
||||||
|
dac_ddata_0[63:48] <= dac_ddata[ 63: 48];
|
||||||
|
dac_ddata_0[47:32] <= dac_ddata[ 47: 32];
|
||||||
|
dac_ddata_0[31:16] <= dac_ddata[ 31: 16];
|
||||||
|
dac_ddata_0[15: 0] <= dac_ddata[ 15: 0];
|
||||||
|
end
|
||||||
|
dac_ddata_1 <= 64'd0;
|
||||||
|
dac_ddata_2 <= 64'd0;
|
||||||
|
dac_ddata_3 <= 64'd0;
|
||||||
|
end
|
||||||
|
default: begin
|
||||||
|
dac_drd <= 1'b0;
|
||||||
|
dac_ddata_0 <= 64'd0;
|
||||||
|
dac_ddata_1 <= 64'd0;
|
||||||
|
dac_ddata_2 <= 64'd0;
|
||||||
|
dac_ddata_3 <= 64'd0;
|
||||||
|
end
|
||||||
|
endcase
|
||||||
|
end
|
||||||
|
|
||||||
|
always @(posedge adc_clk) begin
|
||||||
|
case ({adc_enable_1, adc_enable_0})
|
||||||
|
2'b11: begin
|
||||||
|
adc_dsync <= 1'b1;
|
||||||
|
adc_dwr <= adc_valid_1 & adc_valid_0;
|
||||||
|
adc_ddata[127:112] <= adc_data_1[63:48];
|
||||||
|
adc_ddata[111: 96] <= adc_data_0[63:48];
|
||||||
|
adc_ddata[ 95: 80] <= adc_data_1[47:32];
|
||||||
|
adc_ddata[ 79: 64] <= adc_data_0[47:32];
|
||||||
|
adc_ddata[ 63: 48] <= adc_data_1[31:16];
|
||||||
|
adc_ddata[ 47: 32] <= adc_data_0[31:16];
|
||||||
|
adc_ddata[ 31: 16] <= adc_data_1[15: 0];
|
||||||
|
adc_ddata[ 15: 0] <= adc_data_0[15: 0];
|
||||||
|
end
|
||||||
|
2'b10: begin
|
||||||
|
adc_dsync <= 1'b1;
|
||||||
|
adc_dwr <= adc_valid_1 & ~adc_dwr;
|
||||||
|
adc_ddata[127:112] <= adc_data_1[63:48];
|
||||||
|
adc_ddata[111: 96] <= adc_data_1[47:32];
|
||||||
|
adc_ddata[ 95: 80] <= adc_data_1[31:16];
|
||||||
|
adc_ddata[ 79: 64] <= adc_data_1[15: 0];
|
||||||
|
adc_ddata[ 63: 48] <= adc_ddata[127:112];
|
||||||
|
adc_ddata[ 47: 32] <= adc_ddata[111: 96];
|
||||||
|
adc_ddata[ 31: 16] <= adc_ddata[ 95: 80];
|
||||||
|
adc_ddata[ 15: 0] <= adc_ddata[ 79: 64];
|
||||||
|
end
|
||||||
|
2'b01: begin
|
||||||
|
adc_dsync <= 1'b1;
|
||||||
|
adc_dwr <= adc_valid_0 & ~adc_dwr;
|
||||||
|
adc_ddata[127:112] <= adc_data_0[63:48];
|
||||||
|
adc_ddata[111: 96] <= adc_data_0[47:32];
|
||||||
|
adc_ddata[ 95: 80] <= adc_data_0[31:16];
|
||||||
|
adc_ddata[ 79: 64] <= adc_data_0[15: 0];
|
||||||
|
adc_ddata[ 63: 48] <= adc_ddata[127:112];
|
||||||
|
adc_ddata[ 47: 32] <= adc_ddata[111: 96];
|
||||||
|
adc_ddata[ 31: 16] <= adc_ddata[ 95: 80];
|
||||||
|
adc_ddata[ 15: 0] <= adc_ddata[ 79: 64];
|
||||||
|
end
|
||||||
|
default: begin
|
||||||
|
adc_dsync <= 1'b0;
|
||||||
|
adc_dwr <= 1'b0;
|
||||||
|
adc_ddata <= 128'd0;
|
||||||
|
end
|
||||||
|
endcase
|
||||||
|
end
|
||||||
|
|
||||||
|
// spi
|
||||||
|
|
||||||
|
assign spi_csn_adc = spi_csn[2];
|
||||||
|
assign spi_csn_dac = spi_csn[1];
|
||||||
|
assign spi_csn_clk = spi_csn[0];
|
||||||
|
|
||||||
|
// default logic
|
||||||
|
|
||||||
|
assign fan_pwm = 1'b1;
|
||||||
|
|
||||||
|
// instantiations
|
||||||
|
|
||||||
|
IBUFDS_GTE2 i_ibufds_rx_ref_clk (
|
||||||
|
.CEB (1'd0),
|
||||||
|
.I (rx_ref_clk_p),
|
||||||
|
.IB (rx_ref_clk_n),
|
||||||
|
.O (rx_ref_clk),
|
||||||
|
.ODIV2 ());
|
||||||
|
|
||||||
|
IBUFDS i_ibufds_rx_sysref (
|
||||||
|
.I (rx_sysref_p),
|
||||||
|
.IB (rx_sysref_n),
|
||||||
|
.O (rx_sysref));
|
||||||
|
|
||||||
|
OBUFDS i_obufds_rx_sync (
|
||||||
|
.I (rx_sync),
|
||||||
|
.O (rx_sync_p),
|
||||||
|
.OB (rx_sync_n));
|
||||||
|
|
||||||
|
IBUFDS_GTE2 i_ibufds_tx_ref_clk (
|
||||||
|
.CEB (1'd0),
|
||||||
|
.I (tx_ref_clk_p),
|
||||||
|
.IB (tx_ref_clk_n),
|
||||||
|
.O (tx_ref_clk),
|
||||||
|
.ODIV2 ());
|
||||||
|
|
||||||
|
IBUFDS i_ibufds_tx_sysref (
|
||||||
|
.I (tx_sysref_p),
|
||||||
|
.IB (tx_sysref_n),
|
||||||
|
.O (tx_sysref));
|
||||||
|
|
||||||
|
IBUFDS i_ibufds_tx_sync (
|
||||||
|
.I (tx_sync_p),
|
||||||
|
.IB (tx_sync_n),
|
||||||
|
.O (tx_sync));
|
||||||
|
|
||||||
|
daq2_spi i_spi (
|
||||||
|
.spi_csn (spi_csn),
|
||||||
|
.spi_clk (spi_clk),
|
||||||
|
.spi_mosi (spi_mosi),
|
||||||
|
.spi_miso (spi_miso),
|
||||||
|
.spi_sdio (spi_sdio),
|
||||||
|
.spi_dir (spi_dir));
|
||||||
|
|
||||||
|
IBUFDS i_ibufds_trig (
|
||||||
|
.I (trig_p),
|
||||||
|
.IB (trig_n),
|
||||||
|
.O (trig));
|
||||||
|
|
||||||
|
assign gpio_ctl_i[0] = trig;
|
||||||
|
|
||||||
|
ad_iobuf #(.DATA_WIDTH(9)) i_iobuf (
|
||||||
|
.dt ({gpio_ctl_t[5:3], gpio_ctl_t[1], gpio_status_t[4:0]}),
|
||||||
|
.di ({gpio_ctl_o[5:3], gpio_ctl_o[1], gpio_status_o[4:0]}),
|
||||||
|
.do ({gpio_ctl_i[5:3], gpio_ctl_i[1], gpio_status_i[4:0]}),
|
||||||
|
.dio ({ adc_pd, // 10
|
||||||
|
dac_txen, // 9
|
||||||
|
dac_reset, // 8
|
||||||
|
clkd_sync, // 6
|
||||||
|
adc_fdb, // 4
|
||||||
|
adc_fda, // 3
|
||||||
|
dac_irq, // 2
|
||||||
|
clkd_status})); // 0
|
||||||
|
|
||||||
|
// instantiations
|
||||||
|
|
||||||
|
system_wrapper i_system_wrapper (
|
||||||
|
.adc_clk (adc_clk),
|
||||||
|
.adc_data_0 (adc_data_0),
|
||||||
|
.adc_data_1 (adc_data_1),
|
||||||
|
.adc_ddata (adc_ddata),
|
||||||
|
.adc_dsync (adc_dsync),
|
||||||
|
.adc_dwr (adc_dwr),
|
||||||
|
.adc_enable_0 (adc_enable_0),
|
||||||
|
.adc_enable_1 (adc_enable_1),
|
||||||
|
.adc_valid_0 (adc_valid_0),
|
||||||
|
.adc_valid_1 (adc_valid_1),
|
||||||
|
.ddr3_addr (ddr3_addr),
|
||||||
|
.ddr3_ba (ddr3_ba),
|
||||||
|
.ddr3_cas_n (ddr3_cas_n),
|
||||||
|
.ddr3_ck_n (ddr3_ck_n),
|
||||||
|
.ddr3_ck_p (ddr3_ck_p),
|
||||||
|
.ddr3_cke (ddr3_cke),
|
||||||
|
.ddr3_cs_n (ddr3_cs_n),
|
||||||
|
.ddr3_dm (ddr3_dm),
|
||||||
|
.ddr3_dq (ddr3_dq),
|
||||||
|
.ddr3_dqs_n (ddr3_dqs_n),
|
||||||
|
.ddr3_dqs_p (ddr3_dqs_p),
|
||||||
|
.ddr3_odt (ddr3_odt),
|
||||||
|
.ddr3_ras_n (ddr3_ras_n),
|
||||||
|
.ddr3_reset_n (ddr3_reset_n),
|
||||||
|
.ddr3_we_n (ddr3_we_n),
|
||||||
|
.dac_clk (dac_clk),
|
||||||
|
.dac_ddata (dac_ddata),
|
||||||
|
.dac_ddata_0 (dac_ddata_0),
|
||||||
|
.dac_ddata_1 (dac_ddata_1),
|
||||||
|
.dac_ddata_2 (dac_ddata_2),
|
||||||
|
.dac_ddata_3 (dac_ddata_3),
|
||||||
|
.dac_drd (dac_drd),
|
||||||
|
.dac_enable_0 (dac_enable_0),
|
||||||
|
.dac_enable_1 (dac_enable_1),
|
||||||
|
.dac_enable_2 (dac_enable_2),
|
||||||
|
.dac_enable_3 (dac_enable_3),
|
||||||
|
.dac_valid_0 (dac_valid_0),
|
||||||
|
.dac_valid_1 (dac_valid_1),
|
||||||
|
.dac_valid_2 (dac_valid_2),
|
||||||
|
.dac_valid_3 (dac_valid_3),
|
||||||
|
.gpio_ctl_i (gpio_ctl_i),
|
||||||
|
.gpio_ctl_o (gpio_ctl_o),
|
||||||
|
.gpio_ctl_t (gpio_ctl_t),
|
||||||
|
.linear_flash_addr (linear_flash_addr),
|
||||||
|
.linear_flash_adv_ldn (linear_flash_adv_ldn),
|
||||||
|
.linear_flash_ce_n (linear_flash_ce_n),
|
||||||
|
.linear_flash_oen (linear_flash_oen),
|
||||||
|
.linear_flash_wen (linear_flash_wen),
|
||||||
|
.linear_flash_dq_io(linear_flash_dq_io),
|
||||||
|
.gpio_lcd_tri_o (gpio_lcd),
|
||||||
|
.gpio_led_tri_o (gpio_led),
|
||||||
|
.gpio_status_i (gpio_status_i),
|
||||||
|
.gpio_status_o (gpio_status_o),
|
||||||
|
.gpio_status_t (gpio_status_t),
|
||||||
|
.gpio_sw_tri_i (gpio_sw),
|
||||||
|
.hdmi_data (hdmi_data),
|
||||||
|
.hdmi_data_e (hdmi_data_e),
|
||||||
|
.hdmi_hsync (hdmi_hsync),
|
||||||
|
.hdmi_out_clk (hdmi_out_clk),
|
||||||
|
.hdmi_vsync (hdmi_vsync),
|
||||||
|
.iic_main_scl_io (iic_scl),
|
||||||
|
.iic_main_sda_io (iic_sda),
|
||||||
|
.iic_rstn (iic_rstn),
|
||||||
|
.mb_intr_10 (mb_intrs[10]),
|
||||||
|
.mb_intr_11 (mb_intrs[11]),
|
||||||
|
.mb_intr_12 (mb_intrs[12]),
|
||||||
|
.mb_intr_13 (mb_intrs[13]),
|
||||||
|
.mb_intr_14 (mb_intrs[14]),
|
||||||
|
.mb_intr_15 (mb_intrs[15]),
|
||||||
|
.mb_intr_16 (mb_intrs[16]),
|
||||||
|
.mb_intr_17 (mb_intrs[17]),
|
||||||
|
.mb_intr_18 (mb_intrs[18]),
|
||||||
|
.mb_intr_19 (mb_intrs[19]),
|
||||||
|
.mb_intr_20 (mb_intrs[20]),
|
||||||
|
.mb_intr_21 (mb_intrs[21]),
|
||||||
|
.mb_intr_22 (mb_intrs[22]),
|
||||||
|
.mb_intr_23 (mb_intrs[23]),
|
||||||
|
.mb_intr_24 (mb_intrs[24]),
|
||||||
|
.mb_intr_25 (mb_intrs[25]),
|
||||||
|
.mb_intr_26 (mb_intrs[26]),
|
||||||
|
.mb_intr_27 (mb_intrs[27]),
|
||||||
|
.mb_intr_28 (mb_intrs[28]),
|
||||||
|
.mb_intr_29 (mb_intrs[29]),
|
||||||
|
.mb_intr_30 (mb_intrs[30]),
|
||||||
|
.mb_intr_31 (mb_intrs[31]),
|
||||||
|
.axi_ad9144_dma_intr (mb_intrs[13]),
|
||||||
|
.axi_ad9680_dma_intr (mb_intrs[12]),
|
||||||
|
.axi_daq2_gpio_intr (mb_intrs[11]),
|
||||||
|
.axi_daq2_spi_intr (mb_intrs[10]),
|
||||||
|
.rx_data_n (rx_data_n),
|
||||||
|
.rx_data_p (rx_data_p),
|
||||||
|
.rx_ref_clk (rx_ref_clk),
|
||||||
|
.rx_sync (rx_sync),
|
||||||
|
.rx_sysref (rx_sysref),
|
||||||
|
.tx_data_n (tx_data_n),
|
||||||
|
.tx_data_p (tx_data_p),
|
||||||
|
.tx_ref_clk (tx_ref_clk),
|
||||||
|
.tx_sync (tx_sync),
|
||||||
|
.tx_sysref (tx_sysref),
|
||||||
|
.spi_clk_i (spi_clk),
|
||||||
|
.spi_clk_o (spi_clk),
|
||||||
|
.spi_csn_i (spi_csn),
|
||||||
|
.spi_csn_o (spi_csn),
|
||||||
|
.spi_sdi_i (spi_miso),
|
||||||
|
.spi_sdo_i (spi_mosi),
|
||||||
|
.spi_sdo_o (spi_mosi),
|
||||||
|
.mdio_mdc (mdio_mdc),
|
||||||
|
.mdio_mdio_io (mdio_mdio),
|
||||||
|
.mgt_clk_clk_n (mgt_clk_n),
|
||||||
|
.mgt_clk_clk_p (mgt_clk_p),
|
||||||
|
.phy_rstn (phy_rstn),
|
||||||
|
.sgmii_rxn (sgmii_rxn),
|
||||||
|
.sgmii_rxp (sgmii_rxp),
|
||||||
|
.sgmii_txn (sgmii_txn),
|
||||||
|
.sgmii_txp (sgmii_txp),
|
||||||
|
.spdif (spdif),
|
||||||
|
.sys_clk_n (sys_clk_n),
|
||||||
|
.sys_clk_p (sys_clk_p),
|
||||||
|
.sys_rst (sys_rst),
|
||||||
|
.uart_sin (uart_sin),
|
||||||
|
.uart_sout (uart_sout));
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
|
||||||
|
// ***************************************************************************
|
||||||
|
// ***************************************************************************
|
||||||
Loading…
Reference in New Issue