From e1b73545e4dcee476cf30df0d2aeecaf947385a6 Mon Sep 17 00:00:00 2001
From: Laszlo Nagy <laszlo.nagy@analog.com>
Date: Mon, 10 May 2021 15:29:02 +0100
Subject: [PATCH] util_adxcvr: GTY TX phase and delay alignment circuit power
 down.

Tied High when a) TX buffer bypass is not in use;
see UG578
---
 library/xilinx/util_adxcvr/util_adxcvr_xch.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/library/xilinx/util_adxcvr/util_adxcvr_xch.v b/library/xilinx/util_adxcvr/util_adxcvr_xch.v
index 869ae1fab..612f80748 100644
--- a/library/xilinx/util_adxcvr/util_adxcvr_xch.v
+++ b/library/xilinx/util_adxcvr/util_adxcvr_xch.v
@@ -3272,7 +3272,7 @@ module util_adxcvr_xch #(
       .TXPDELECIDLEMODE (1'b0),
       .TXPHALIGN (1'b0),
       .TXPHALIGNEN (1'b0),
-      .TXPHDLYPD (1'b0),
+      .TXPHDLYPD (1'b1),
       .TXPHDLYRESET (1'b0),
       .TXPHDLYTSTCLK (1'b0),
       .TXPHINIT (1'b0),