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ad9250- update to use alt ip interface script

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Rejeesh Kutty 2015-06-24 05:25:16 -04:00
parent 00bc48bc24
commit e1b1e1bc2c
1 changed files with 21 additions and 23 deletions
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44
library/axi_ad9250/axi_ad9250_hw.tcl
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@ -2,6 +2,7 @@
package require -exact qsys 13.0 package require -exact qsys 13.0
source ../scripts/adi_env.tcl source ../scripts/adi_env.tcl
source ../scripts/adi_ip_alt.tcl
set_module_property NAME axi_ad9250 set_module_property NAME axi_ad9250
set_module_property DESCRIPTION "AXI AD9250 Interface" set_module_property DESCRIPTION "AXI AD9250 Interface"
@ -26,6 +27,7 @@ add_fileset_file axi_ad9250_pnmon.v VERILOG PATH axi_ad9250_pnmon.v
add_fileset_file axi_ad9250_if.v VERILOG PATH axi_ad9250_if.v add_fileset_file axi_ad9250_if.v VERILOG PATH axi_ad9250_if.v
add_fileset_file axi_ad9250_channel.v VERILOG PATH axi_ad9250_channel.v add_fileset_file axi_ad9250_channel.v VERILOG PATH axi_ad9250_channel.v
add_fileset_file axi_ad9250.v VERILOG PATH axi_ad9250.v TOP_LEVEL_FILE add_fileset_file axi_ad9250.v VERILOG PATH axi_ad9250.v TOP_LEVEL_FILE
add_fileset_file ad_axi_ip_constr.sdc SDC PATH $ad_hdl_dir/library/common/ad_axi_ip_constr.sdc
# parameters # parameters
@ -56,7 +58,8 @@ add_interface s_axi axi4lite end
set_interface_property s_axi associatedClock s_axi_clock set_interface_property s_axi associatedClock s_axi_clock
set_interface_property s_axi associatedReset s_axi_reset set_interface_property s_axi associatedReset s_axi_reset
add_interface_port s_axi s_axi_awvalid awvalid Input 1 add_interface_port s_axi s_axi_awvalid awvalid Input 1
add_interface_port s_axi s_axi_awaddr awaddr Input 14 add_interface_port s_axi s_axi_awaddr awaddr Input 16
add_interface_port s_axi s_axi_awprot awprot Input 3
add_interface_port s_axi s_axi_awready awready Output 1 add_interface_port s_axi s_axi_awready awready Output 1
add_interface_port s_axi s_axi_wvalid wvalid Input 1 add_interface_port s_axi s_axi_wvalid wvalid Input 1
add_interface_port s_axi s_axi_wdata wdata Input 32 add_interface_port s_axi s_axi_wdata wdata Input 32
@ -66,38 +69,33 @@ add_interface_port s_axi s_axi_bvalid bvalid Output 1
add_interface_port s_axi s_axi_bresp bresp Output 2 add_interface_port s_axi s_axi_bresp bresp Output 2
add_interface_port s_axi s_axi_bready bready Input 1 add_interface_port s_axi s_axi_bready bready Input 1
add_interface_port s_axi s_axi_arvalid arvalid Input 1 add_interface_port s_axi s_axi_arvalid arvalid Input 1
add_interface_port s_axi s_axi_araddr araddr Input 14 add_interface_port s_axi s_axi_araddr araddr Input 16
add_interface_port s_axi s_axi_arprot arprot Input 3
add_interface_port s_axi s_axi_arready arready Output 1 add_interface_port s_axi s_axi_arready arready Output 1
add_interface_port s_axi s_axi_rvalid rvalid Output 1 add_interface_port s_axi s_axi_rvalid rvalid Output 1
add_interface_port s_axi s_axi_rresp rresp Output 2 add_interface_port s_axi s_axi_rresp rresp Output 2
add_interface_port s_axi s_axi_rdata rdata Output 32 add_interface_port s_axi s_axi_rdata rdata Output 32
add_interface_port s_axi s_axi_rready rready Input 1 add_interface_port s_axi s_axi_rready rready Input 1
add_interface_port s_axi s_axi_awprot awprot Input 3
add_interface_port s_axi s_axi_arprot arprot Input 3
# transceiver interface # transceiver interface
add_interface xcvr_clk clock end add_interface if_rx_clk clock end
add_interface_port xcvr_clk rx_clk clk Input 1 add_interface_port if_rx_clk rx_clk clk Input 1
add_interface xcvr_data conduit end add_interface if_rx_data avalon_streaming end
set_interface_property xcvr_data associatedClock xcvr_clk set_interface_property if_rx_data associatedClock if_rx_clk
add_interface_port xcvr_data rx_data data Input 64 set_interface_property if_rx_data dataBitsPerSymbol 64
add_interface_port if_rx_data rx_data data Input 64
# dma interface # dma interface
add_interface adc_clock clock start ad_alt_intf clock adc_clock output 1
add_interface_port adc_clock adc_clk clk Output 1 ad_alt_intf signal adc_valid_a output 1 adc_valid_0
ad_alt_intf signal adc_enable_a output 1 adc_enable_0
add_interface adc_dma_if conduit end ad_alt_intf signal adc_data_a output 32 adc_data_0
set_interface_property adc_dma_if associatedClock adc_clock ad_alt_intf signal adc_valid_b output 1 adc_valid_1
add_interface_port adc_dma_if adc_valid_a adc_valid_a Output 1 ad_alt_intf signal adc_enable_b output 1 adc_enable_1
add_interface_port adc_dma_if adc_enable_a adc_enable_a Output 1 ad_alt_intf signal adc_data_b output 32 adc_data_1
add_interface_port adc_dma_if adc_data_a adc_data_a Output 32 ad_alt_intf signal adc_dovf input 1
add_interface_port adc_dma_if adc_valid_b adc_valid_b Output 1 ad_alt_intf signal adc_dunf input 1
add_interface_port adc_dma_if adc_enable_b adc_enable_b Output 1
add_interface_port adc_dma_if adc_data_b adc_data_b Output 32
add_interface_port adc_dma_if adc_dovf adc_dovf Input 1
add_interface_port adc_dma_if adc_dunf adc_dunf Input 1