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ad9081: Parameters and header update 

Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
main
Bogdan Luncan 2023-05-08 13:01:09 +01:00 committed by Bogdan Luncan
parent b21fb3a0e0
commit e1af7837da
14 changed files with 92 additions and 130 deletions
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2
projects/ad9081_fmca_ebz/a10soc/system_top.v
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@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
// Copyright 2014 - 2023 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are

23
projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl
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@ -23,7 +23,9 @@ source $ad_hdl_dir/projects/common/xilinx/data_offload_bd.tcl
source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl
source $ad_hdl_dir/library/axi_tdd/scripts/axi_tdd.tcl
set INTF_CFG $ad_project_params(INTF_CFG)
if {![info exists INTF_CFG]} {
set INTF_CFG RXTX
}
# Common parameter for TX and RX
set JESD_MODE $ad_project_params(JESD_MODE)
@ -118,8 +120,10 @@ if {$TX_DMA_SAMPLE_WIDTH == 12} {
set TX_DATAPATH_WIDTH [adi_jesd204_calc_tpl_width $DATAPATH_WIDTH $TX_JESD_L $TX_JESD_M $TX_JESD_S $TX_JESD_NP $TX_TPL_WIDTH]
set TX_SAMPLES_PER_CHANNEL [expr $TX_NUM_OF_LANES * 8* $TX_DATAPATH_WIDTH / ($TX_NUM_OF_CONVERTERS * $TX_SAMPLE_WIDTH)]
set TX_SAMPLES_PER_CHANNEL [expr $TX_NUM_OF_LANES * 8 * $TX_DATAPATH_WIDTH / ($TX_NUM_OF_CONVERTERS * $TX_SAMPLE_WIDTH)]
# TODO: Increase the maximum number of quads if necessary
set max_num_quads 2
set num_quads [expr int(round(1.0 * $RX_NUM_OF_LANES / 4))]
source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl
@ -248,8 +252,8 @@ if {$INTF_CFG != "TX"} {
ad_ip_parameter axi_mxfe_rx_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter axi_mxfe_rx_dma CONFIG.MAX_BYTES_PER_BURST 4096
ad_ip_parameter axi_mxfe_rx_dma CONFIG.CYCLIC 0
ad_ip_parameter axi_mxfe_rx_dma CONFIG.DMA_DATA_WIDTH_SRC $dac_dma_data_width
ad_ip_parameter axi_mxfe_rx_dma CONFIG.DMA_DATA_WIDTH_DEST [expr min(512, $dac_dma_data_width)]
ad_ip_parameter axi_mxfe_rx_dma CONFIG.DMA_DATA_WIDTH_SRC $adc_dma_data_width
ad_ip_parameter axi_mxfe_rx_dma CONFIG.DMA_DATA_WIDTH_DEST [expr min(512, $adc_dma_data_width)]
}
# Instantiate DAC (Tx) path
@ -507,6 +511,17 @@ if {$ADI_PHY_SEL == 1} {
for {set j 0} {$j < $num_quads} {incr j} {
make_bd_intf_pins_external [get_bd_intf_pins jesd204_phy/GT_Serial_${j}]
}
# Unused serial lanes
for {set i $num_quads} {$i < $max_num_quads} {incr i} {
if {$INTF_CFG != "TX"} {
create_bd_port -dir I -from 3 -to 0 GT_Serial_${i}_0_grx_p
create_bd_port -dir I -from 3 -to 0 GT_Serial_${i}_0_grx_n
}
if {$INTF_CFG != "RX"} {
create_bd_port -dir O -from 3 -to 0 GT_Serial_${i}_0_gtx_p
create_bd_port -dir O -from 3 -to 0 GT_Serial_${i}_0_gtx_n
}
}
}
# Sync at TPL level

1
projects/ad9081_fmca_ebz/vck190/system_project.tcl
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@ -30,7 +30,6 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
# make JESD_MODE=64B66B RX_LANE_RATE=24.75 TX_LANE_RATE=24.75 RX_JESD_M=4 RX_JESD_L=4 RX_JESD_S=2 RX_JESD_NP=12 TX_JESD_M=4 TX_JESD_L=4 TX_JESD_S=2 TX_JESD_NP=12
adi_project ad9081_fmca_ebz_vck190 0 [list \
INTF_CFG RXTX \
JESD_MODE [get_env_param JESD_MODE 64B66B ]\
RX_LANE_RATE [get_env_param RX_LANE_RATE 11.88 ] \
TX_LANE_RATE [get_env_param TX_LANE_RATE 11.88 ] \

158
projects/ad9081_fmca_ebz/vck190/system_top.v
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@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
// Copyright 2014 - 2023 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
@ -255,113 +255,59 @@ module system_top #(
assign gpio_i[94:64] = gpio_o[94:64];
assign gpio_i[31:10] = gpio_o[31:10];
generate
if (RX_JESD_L > 4 || TX_JESD_L > 4) begin
system_wrapper i_system_wrapper (
.gpio0_i (gpio_i[31:0]),
.gpio0_o (gpio_o[31:0]),
.gpio0_t (gpio_t[31:0]),
.gpio1_i (gpio_i[63:32]),
.gpio1_o (gpio_o[63:32]),
.gpio1_t (gpio_t[63:32]),
.gpio2_i (gpio_i[95:64]),
.gpio2_o (gpio_o[95:64]),
.gpio2_t (gpio_t[95:64]),
.ddr4_dimm1_sma_clk_clk_n (sys_clk_n),
.ddr4_dimm1_sma_clk_clk_p (sys_clk_p),
.ddr4_dimm1_act_n (ddr4_act_n),
.ddr4_dimm1_adr (ddr4_adr),
.ddr4_dimm1_ba (ddr4_ba),
.ddr4_dimm1_bg (ddr4_bg),
.ddr4_dimm1_ck_c (ddr4_ck_c),
.ddr4_dimm1_ck_t (ddr4_ck_t),
.ddr4_dimm1_cke (ddr4_cke),
.ddr4_dimm1_cs_n (ddr4_cs_n),
.ddr4_dimm1_dm_n (ddr4_dm_n),
.ddr4_dimm1_dq (ddr4_dq),
.ddr4_dimm1_dqs_c (ddr4_dqs_c),
.ddr4_dimm1_dqs_t (ddr4_dqs_t),
.ddr4_dimm1_odt (ddr4_odt),
.ddr4_dimm1_reset_n (ddr4_reset_n),
.spi0_csn (spi0_csn),
.spi0_miso (spi0_miso),
.spi0_mosi (spi0_mosi),
.spi0_sclk (spi0_sclk),
.spi1_csn (spi1_csn),
.spi1_miso (spi1_miso),
.spi1_mosi (spi1_mosi),
.spi1_sclk (spi1_sclk),
// FMC HPC
.GT_Serial_0_0_gtx_p (tx_data_p_loc[3:0]),
.GT_Serial_0_0_gtx_n (tx_data_n_loc[3:0]),
.GT_Serial_0_0_grx_p (rx_data_p_loc[3:0]),
.GT_Serial_0_0_grx_n (rx_data_n_loc[3:0]),
.GT_Serial_1_0_gtx_p (tx_data_p_loc[7:4]),
.GT_Serial_1_0_gtx_n (tx_data_n_loc[7:4]),
.GT_Serial_1_0_grx_p (rx_data_p_loc[7:4]),
.GT_Serial_1_0_grx_n (rx_data_n_loc[7:4]),
system_wrapper i_system_wrapper (
.gpio0_i (gpio_i[31:0]),
.gpio0_o (gpio_o[31:0]),
.gpio0_t (gpio_t[31:0]),
.gpio1_i (gpio_i[63:32]),
.gpio1_o (gpio_o[63:32]),
.gpio1_t (gpio_t[63:32]),
.gpio2_i (gpio_i[95:64]),
.gpio2_o (gpio_o[95:64]),
.gpio2_t (gpio_t[95:64]),
.ddr4_dimm1_sma_clk_clk_n (sys_clk_n),
.ddr4_dimm1_sma_clk_clk_p (sys_clk_p),
.ddr4_dimm1_act_n (ddr4_act_n),
.ddr4_dimm1_adr (ddr4_adr),
.ddr4_dimm1_ba (ddr4_ba),
.ddr4_dimm1_bg (ddr4_bg),
.ddr4_dimm1_ck_c (ddr4_ck_c),
.ddr4_dimm1_ck_t (ddr4_ck_t),
.ddr4_dimm1_cke (ddr4_cke),
.ddr4_dimm1_cs_n (ddr4_cs_n),
.ddr4_dimm1_dm_n (ddr4_dm_n),
.ddr4_dimm1_dq (ddr4_dq),
.ddr4_dimm1_dqs_c (ddr4_dqs_c),
.ddr4_dimm1_dqs_t (ddr4_dqs_t),
.ddr4_dimm1_odt (ddr4_odt),
.ddr4_dimm1_reset_n (ddr4_reset_n),
.spi0_csn (spi0_csn),
.spi0_miso (spi0_miso),
.spi0_mosi (spi0_mosi),
.spi0_sclk (spi0_sclk),
.spi1_csn (spi1_csn),
.spi1_miso (spi1_miso),
.spi1_mosi (spi1_mosi),
.spi1_sclk (spi1_sclk),
// FMC HPC
.GT_Serial_0_0_gtx_p (tx_data_p_loc[3:0]),
.GT_Serial_0_0_gtx_n (tx_data_n_loc[3:0]),
.GT_Serial_0_0_grx_p (rx_data_p_loc[3:0]),
.GT_Serial_0_0_grx_n (rx_data_n_loc[3:0]),
.GT_Serial_1_0_gtx_p (tx_data_p_loc[7:4]),
.GT_Serial_1_0_gtx_n (tx_data_n_loc[7:4]),
.GT_Serial_1_0_grx_p (rx_data_p_loc[7:4]),
.GT_Serial_1_0_grx_n (rx_data_n_loc[7:4]),
.ref_clk_q0 (ref_clk),
.ref_clk_q1 (ref_clk),
.ref_clk_q0 (ref_clk),
.ref_clk_q1 (ref_clk),
.rx_device_clk (rx_device_clk),
.tx_device_clk (tx_device_clk),
.rx_sync_0 (rx_syncout),
.tx_sync_0 (tx_syncin),
.rx_sysref_0 (sysref),
.tx_sysref_0 (sysref));
end else begin
system_wrapper i_system_wrapper (
.gpio0_i (gpio_i[31:0]),
.gpio0_o (gpio_o[31:0]),
.gpio0_t (gpio_t[31:0]),
.gpio1_i (gpio_i[63:32]),
.gpio1_o (gpio_o[63:32]),
.gpio1_t (gpio_t[63:32]),
.gpio2_i (gpio_i[95:64]),
.gpio2_o (gpio_o[95:64]),
.gpio2_t (gpio_t[95:64]),
.ddr4_dimm1_sma_clk_clk_n (sys_clk_n),
.ddr4_dimm1_sma_clk_clk_p (sys_clk_p),
.ddr4_dimm1_act_n (ddr4_act_n),
.ddr4_dimm1_adr (ddr4_adr),
.ddr4_dimm1_ba (ddr4_ba),
.ddr4_dimm1_bg (ddr4_bg),
.ddr4_dimm1_ck_c (ddr4_ck_c),
.ddr4_dimm1_ck_t (ddr4_ck_t),
.ddr4_dimm1_cke (ddr4_cke),
.ddr4_dimm1_cs_n (ddr4_cs_n),
.ddr4_dimm1_dm_n (ddr4_dm_n),
.ddr4_dimm1_dq (ddr4_dq),
.ddr4_dimm1_dqs_c (ddr4_dqs_c),
.ddr4_dimm1_dqs_t (ddr4_dqs_t),
.ddr4_dimm1_odt (ddr4_odt),
.ddr4_dimm1_reset_n (ddr4_reset_n),
.spi0_csn (spi0_csn),
.spi0_miso (spi0_miso),
.spi0_mosi (spi0_mosi),
.spi0_sclk (spi0_sclk),
.spi1_csn (spi1_csn),
.spi1_miso (spi1_miso),
.spi1_mosi (spi1_mosi),
.spi1_sclk (spi1_sclk),
// FMC HPC
.GT_Serial_0_0_gtx_p (tx_data_p_loc[3:0]),
.GT_Serial_0_0_gtx_n (tx_data_n_loc[3:0]),
.GT_Serial_0_0_grx_p (rx_data_p_loc[3:0]),
.GT_Serial_0_0_grx_n (rx_data_n_loc[3:0]),
.ref_clk_q0 (ref_clk),
.ref_clk_q1 (ref_clk),
.rx_device_clk (rx_device_clk),
.tx_device_clk (tx_device_clk),
.rx_sync_0 (rx_syncout),
.tx_sync_0 (tx_syncin),
.rx_sysref_0 (sysref),
.tx_sysref_0 (sysref));
end
endgenerate
.rx_device_clk (rx_device_clk),
.tx_device_clk (tx_device_clk),
.rx_sync_0 (rx_syncout),
.tx_sync_0 (tx_syncin),
.rx_sysref_0 (sysref),
.tx_sysref_0 (sysref));
assign rx_data_p_loc[RX_JESD_L*RX_NUM_LINKS-1:0] = rx_data_p[RX_JESD_L*RX_NUM_LINKS-1:0];
assign rx_data_n_loc[RX_JESD_L*RX_NUM_LINKS-1:0] = rx_data_n[RX_JESD_L*RX_NUM_LINKS-1:0];

8
projects/ad9081_fmca_ebz/vcu118/system_bd.tcl
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@ -9,8 +9,12 @@ source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl
source $ad_hdl_dir/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl
source $ad_hdl_dir/projects/scripts/adi_pd.tcl
ad_ip_parameter axi_mxfe_rx_jesd/rx CONFIG.NUM_INPUT_PIPELINE 2
ad_ip_parameter axi_mxfe_tx_jesd/tx CONFIG.NUM_OUTPUT_PIPELINE 1
if {$INTF_CFG != "TX"} {
ad_ip_parameter axi_mxfe_rx_jesd/rx CONFIG.NUM_INPUT_PIPELINE 2
}
if {$INTF_CFG != "RX"} {
ad_ip_parameter axi_mxfe_tx_jesd/tx CONFIG.NUM_OUTPUT_PIPELINE 1
}
set mem_init_sys_path [get_env_param ADI_PROJECT_DIR ""]mem_init_sys.txt;

1
projects/ad9081_fmca_ebz/vcu118/system_project.tcl
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@ -32,7 +32,6 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
#
adi_project ad9081_fmca_ebz_vcu118 0 [list \
INTF_CFG RXTX \
JESD_MODE [get_env_param JESD_MODE 8B10B ] \
RX_LANE_RATE [get_env_param RX_LANE_RATE 10 ] \
TX_LANE_RATE [get_env_param TX_LANE_RATE 10 ] \

2
projects/ad9081_fmca_ebz/vcu118/system_top.v
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@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
// Copyright 2014 - 2023 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are

18
projects/ad9081_fmca_ebz/vcu128/system_bd.tcl
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@ -10,20 +10,22 @@ source $ad_hdl_dir/projects/common/vcu128/vcu128_system_bd.tcl
source $ad_hdl_dir/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl
source $ad_hdl_dir/projects/scripts/adi_pd.tcl
if {$INTF_CFG != "TX"} {
ad_connect_hbm HBM mxfe_rx_data_offload/storage_unit $sys_hbm_clk $sys_hbm_resetn 0
ad_ip_parameter $adc_data_offload_name/i_data_offload CONFIG.HAS_BYPASS false
ad_ip_parameter axi_mxfe_rx_jesd/rx CONFIG.NUM_INPUT_PIPELINE 2
}
ad_connect_hbm HBM mxfe_rx_data_offload/storage_unit $sys_hbm_clk $sys_hbm_resetn 0
ad_connect_hbm HBM mxfe_tx_data_offload/storage_unit $sys_hbm_clk $sys_hbm_resetn 4
ad_ip_parameter $adc_data_offload_name/i_data_offload CONFIG.HAS_BYPASS false
ad_ip_parameter $dac_data_offload_name/i_data_offload CONFIG.HAS_BYPASS false
if {$INTF_CFG != "RX"} {
ad_connect_hbm HBM mxfe_tx_data_offload/storage_unit $sys_hbm_clk $sys_hbm_resetn 4
ad_ip_parameter $dac_data_offload_name/i_data_offload CONFIG.HAS_BYPASS false
ad_ip_parameter axi_mxfe_tx_jesd/tx CONFIG.NUM_OUTPUT_PIPELINE 1
}
ad_connect HBM/HBM_REF_CLK_0 $sys_cpu_clk
ad_connect HBM/APB_0_PCLK $sys_cpu_clk
ad_connect HBM/APB_0_PRESET_N $sys_cpu_resetn
ad_ip_parameter axi_mxfe_rx_jesd/rx CONFIG.NUM_INPUT_PIPELINE 2
ad_ip_parameter axi_mxfe_tx_jesd/tx CONFIG.NUM_OUTPUT_PIPELINE 1
set mem_init_sys_path [get_env_param ADI_PROJECT_DIR ""]mem_init_sys.txt;
#system ID

1
projects/ad9081_fmca_ebz/vcu128/system_project.tcl
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@ -32,7 +32,6 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
#
adi_project ad9081_fmca_ebz_vcu128 0 [list \
INTF_CFG RXTX \
JESD_MODE [get_env_param JESD_MODE 8B10B ] \
RX_LANE_RATE [get_env_param RX_LANE_RATE 10 ] \
TX_LANE_RATE [get_env_param TX_LANE_RATE 10 ] \

2
projects/ad9081_fmca_ebz/vcu128/system_top.v
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@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
// Copyright 2014 - 2023 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are

1
projects/ad9081_fmca_ebz/zc706/system_project.tcl
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@ -30,7 +30,6 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
adi_project ad9081_fmca_ebz_zc706 0 [list \
JESD_MODE 8B10B \
INTF_CFG RXTX \
RX_LANE_RATE [get_env_param RX_LANE_RATE 10 ] \
TX_LANE_RATE [get_env_param TX_LANE_RATE 10 ] \
RX_JESD_M [get_env_param RX_JESD_M 8 ] \

2
projects/ad9081_fmca_ebz/zc706/system_top.v
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@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2020 (c) Analog Devices, Inc. All rights reserved.
// Copyright 2014 - 2023 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are

1
projects/ad9081_fmca_ebz/zcu102/system_project.tcl
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@ -26,7 +26,6 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
#
adi_project ad9081_fmca_ebz_zcu102 0 [list \
INTF_CFG RXTX \
JESD_MODE [get_env_param JESD_MODE 8B10B ] \
RX_LANE_RATE [get_env_param RX_LANE_RATE 10 ] \
TX_LANE_RATE [get_env_param TX_LANE_RATE 10 ] \

2
projects/ad9081_fmca_ebz/zcu102/system_top.v
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@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
// Copyright 2014 - 2023 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are