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axi_dacfifo: Cosmetic changes

main
Istvan Csomortani 2016-05-26 14:25:36 +03:00
parent c724c027c4
commit e1495b89f9
4 changed files with 14 additions and 14 deletions
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6
library/axi_dacfifo/axi_dacfifo.v
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@ -194,8 +194,8 @@ module axi_dacfifo (
wire [(AXI_DATA_WIDTH-1):0] axi_rd_data_s; wire [(AXI_DATA_WIDTH-1):0] axi_rd_data_s;
wire axi_rd_ready_s; wire axi_rd_ready_s;
wire axi_rd_valid_s; wire axi_rd_valid_s;
wire [31:0] axi_rd_lastaddr_s;
wire axi_xfer_req_s; wire axi_xfer_req_s;
wire [31:0] axi_last_addr_s;
wire [31:0] dma_last_addr_s; wire [31:0] dma_last_addr_s;
wire [(DAC_DATA_WIDTH-1):0] dac_data_s; wire [(DAC_DATA_WIDTH-1):0] dac_data_s;
@ -217,7 +217,7 @@ module axi_dacfifo (
.dma_valid (dma_valid), .dma_valid (dma_valid),
.dma_xfer_req (dma_xfer_req), .dma_xfer_req (dma_xfer_req),
.dma_xfer_last (dma_xfer_last), .dma_xfer_last (dma_xfer_last),
.axi_last_raddr (axi_rd_lastaddr_s), .axi_last_addr (axi_last_addr_s),
.dma_last_addr (dma_last_addr_s), .dma_last_addr (dma_last_addr_s),
.axi_xfer_out (axi_xfer_req_s), .axi_xfer_out (axi_xfer_req_s),
.axi_clk (axi_clk), .axi_clk (axi_clk),
@ -253,7 +253,7 @@ module axi_dacfifo (
.AXI_LENGTH (AXI_LENGTH), .AXI_LENGTH (AXI_LENGTH),
.AXI_ADDRESS (AXI_ADDRESS) .AXI_ADDRESS (AXI_ADDRESS)
) i_rd ( ) i_rd (
.axi_rd_lastaddr (axi_rd_lastaddr_s), .axi_last_raddr (axi_last_addr_s),
.axi_xfer_req (axi_xfer_req_s), .axi_xfer_req (axi_xfer_req_s),
.axi_clk (axi_clk), .axi_clk (axi_clk),
.axi_resetn (axi_resetn), .axi_resetn (axi_resetn),

4
library/axi_dacfifo/axi_dacfifo_dac.v
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@ -85,7 +85,7 @@ module axi_dacfifo_dac (
output axi_dready; output axi_dready;
input axi_xfer_req; input axi_xfer_req;
input [32:0] dma_last_addr; input [31:0] dma_last_addr;
// dac read // dac read
@ -320,7 +320,7 @@ module axi_dacfifo_dac (
end else begin end else begin
dac_almost_empty <= 1'b0; dac_almost_empty <= 1'b0;
end end
dac_dunf <= (dac_mem_addr_diff == 0) ? 1'b1 : 1'b0; dac_dunf <= (dac_mem_addr_diff == 1'b0) ? 1'b1 : 1'b0;
end end
end end

8
library/axi_dacfifo/axi_dacfifo_rd.v
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@ -44,7 +44,7 @@ module axi_dacfifo_rd (
// xfer last for read/write synchronization // xfer last for read/write synchronization
axi_xfer_req, axi_xfer_req,
axi_rd_lastaddr, axi_last_raddr,
// axi read address and read data channels // axi read address and read data channels
@ -92,7 +92,7 @@ module axi_dacfifo_rd (
// xfer last for read/write synchronization // xfer last for read/write synchronization
input axi_xfer_req; input axi_xfer_req;
input [ 31:0] axi_rd_lastaddr; input [ 31:0] axi_last_raddr;
// axi interface // axi interface
@ -199,7 +199,7 @@ module axi_dacfifo_rd (
end end
if ((axi_xfer_req_init == 1'b1)) begin if ((axi_xfer_req_init == 1'b1)) begin
axi_araddr <= AXI_ADDRESS; axi_araddr <= AXI_ADDRESS;
axi_rd_addr_h <= axi_rd_lastaddr; axi_rd_addr_h <= axi_last_raddr;
end else if ((axi_xfer_req == 1'b1) && end else if ((axi_xfer_req == 1'b1) &&
(axi_arvalid == 1'b1) && (axi_arvalid == 1'b1) &&
(axi_arready == 1'b1)) begin (axi_arready == 1'b1)) begin
@ -220,7 +220,7 @@ module axi_dacfifo_rd (
end else begin end else begin
axi_ddata <= axi_rdata; axi_ddata <= axi_rdata;
axi_dvalid <= axi_dvalid_s; axi_dvalid <= axi_dvalid_s;
if (axi_xfer_req == 1) begin if (axi_xfer_req == 1'b1) begin
axi_rready <= axi_rvalid; axi_rready <= axi_rvalid;
end end
end end

10
library/axi_dacfifo/axi_dacfifo_wr.v
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@ -55,7 +55,7 @@ module axi_dacfifo_wr (
// syncronization for the read side // syncronization for the read side
axi_last_raddr, axi_last_addr,
dma_last_addr, dma_last_addr,
axi_xfer_out, axi_xfer_out,
@ -125,7 +125,7 @@ module axi_dacfifo_wr (
input dma_xfer_req; input dma_xfer_req;
input dma_xfer_last; input dma_xfer_last;
output [31:0] axi_last_raddr; output [31:0] axi_last_addr;
output [31:0] dma_last_addr; output [31:0] dma_last_addr;
output axi_xfer_out; output axi_xfer_out;
@ -195,7 +195,7 @@ module axi_dacfifo_wr (
reg axi_reset = 1'b0; reg axi_reset = 1'b0;
reg axi_xfer_out = 1'b0; reg axi_xfer_out = 1'b0;
reg [31:0] axi_last_raddr = 'b0; reg [31:0] axi_last_addr = 'b0;
reg axi_awvalid = 1'b0; reg axi_awvalid = 1'b0;
reg [31:0] axi_awaddr = 32'b0; reg [31:0] axi_awaddr = 32'b0;
reg axi_xfer_init = 1'b0; reg axi_xfer_init = 1'b0;
@ -511,7 +511,7 @@ module axi_dacfifo_wr (
if (axi_resetn == 1'b0) begin if (axi_resetn == 1'b0) begin
axi_awvalid <= 'd0; axi_awvalid <= 'd0;
axi_awaddr <= AXI_ADDRESS; axi_awaddr <= AXI_ADDRESS;
axi_last_raddr <= AXI_ADDRESS; axi_last_addr <= AXI_ADDRESS;
axi_xfer_out <= 1'b0; axi_xfer_out <= 1'b0;
end else begin end else begin
if (axi_awvalid == 1'b1) begin if (axi_awvalid == 1'b1) begin
@ -530,7 +530,7 @@ module axi_dacfifo_wr (
axi_awaddr <= axi_awaddr + AXI_AWINCR; axi_awaddr <= axi_awaddr + AXI_AWINCR;
end end
if(axi_xfer_last_m[2] == 1'b1) begin if(axi_xfer_last_m[2] == 1'b1) begin
axi_last_raddr <= axi_awaddr; axi_last_addr <= axi_awaddr;
axi_xfer_out <= 1'b1; axi_xfer_out <= 1'b1;
end end
end end