m2k: use DMA streaming interface
The previous mechanism was "probing" the DMAs for valid data. Better said, each interpolation channel enabled it's DMA until a valid data was received, then it disabled the DMA read and waited for the adjacent channel(DMA) to receive a valid data. Only when for both channels had valid data on the DMAs interfaces was the transmission started. This added an undesired and redundant complexity to the interpolation channels. Furthermore, for continuous transmission, using the above mechanism lead to a fixed phase(sample) shift between the two channels at each start. By using the streaming mechanism the interface is simplified and the above problems are solved.main
AndreiGrozav
AndreiGrozav
parent
dd47e30431
commit
e1353d5291
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@ -49,11 +49,14 @@ module axi_dac_interpolate #(
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input dma_valid_a,
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input dma_valid_b,
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output dma_ready_a,
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output dma_ready_b,
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input dac_enable_a,
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input dac_enable_b,
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output [15:0] dac_int_data_a,
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output [15:0] dac_int_data_b,
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output dac_int_valid_a,
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output dac_int_valid_b,
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output underflow,
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input [ 1:0] trigger_i,
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input trigger_adc,
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@ -140,6 +143,8 @@ module axi_dac_interpolate #(
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wire trigger_active;
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wire ext_trigger;
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wire underflow_a;
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wire underflow_b;
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// signal name changes
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@ -190,6 +195,7 @@ module axi_dac_interpolate #(
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low_level_trigger <= ~trigger_i_m3 & low_level;
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end
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assign underflow = underflow_a | underflow_b;
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axi_dac_interpolate_filter #(
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.CORRECTION_DISABLE(CORRECTION_DISABLE))
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@ -200,8 +206,10 @@ module axi_dac_interpolate #(
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.dac_data (dac_data_a),
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.dac_valid (dac_valid_a),
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.dac_enable (dac_enable_a),
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.dac_int_data (dac_int_data_a),
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.dac_int_valid (dac_int_valid_a),
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.dma_ready (dma_ready_a),
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.underflow (underflow_a),
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.filter_mask (filter_mask_a),
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.interpolation_ratio (interpolation_ratio_a),
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@ -223,9 +231,11 @@ module axi_dac_interpolate #(
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.dac_data (dac_data_b),
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.dac_valid (dac_valid_b),
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.underflow (underflow_b),
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.dac_enable (dac_enable_b),
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.dac_int_data (dac_int_data_b),
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.dac_int_valid (dac_int_valid_b),
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.dma_ready (dma_ready_b),
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.filter_mask (filter_mask_b),
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.interpolation_ratio (interpolation_ratio_b),
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@ -46,8 +46,10 @@ module axi_dac_interpolate_filter #(
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input [15:0] dac_data,
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input dac_valid,
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input dac_enable,
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output reg [15:0] dac_int_data,
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output dac_int_valid,
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output dma_ready,
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output underflow,
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input [ 2:0] filter_mask,
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input [31:0] interpolation_ratio,
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@ -63,26 +65,25 @@ module axi_dac_interpolate_filter #(
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// internal signals
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reg dac_int_valid_d;
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reg dac_int_ready;
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reg dac_filt_int_valid;
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reg [15:0] interp_rate_cic;
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reg [ 2:0] filter_mask_d1;
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reg cic_change_rate;
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reg [31:0] interpolation_counter;
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reg transmit_ready = 1'b1;
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reg transmit_ready = 1'b0;
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reg dma_data_valid = 1'b0;
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reg dma_data_valid_adjacent = 1'b0;
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reg filter_enable = 1'b0;
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reg triggered = 1'b0;
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reg transfer = 1'b0;
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wire dac_valid_corrected;
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wire [15:0] dac_data_corrected;
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wire dac_fir_valid;
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wire [35:0] dac_fir_data;
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wire dac_cic_valid;
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wire [109:0] dac_cic_data;
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@ -127,51 +128,46 @@ module axi_dac_interpolate_filter #(
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end
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end
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// - for start synchronized, if the channels run until the DMA has data valid
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// then if the case wait for second channel DMA to have valid data
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// - for start synchronized, wait until the DMA has valid data on both channels
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// - for non synchronized channels the start of transmission gets the 2 data
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// paths randomly ready. Only valid for the case of loading data buffers
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// paths randomly ready, only when using data buffers
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always @(posedge dac_clk) begin
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if (interpolation_ratio == 0 || interpolation_ratio == 1) begin
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dac_int_valid_d <= dac_filt_int_valid;
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dac_int_ready <= dac_filt_int_valid;
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end else begin
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if (dac_filt_int_valid &
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(!start_sync_channels | !dma_data_valid |
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(dma_data_valid & dma_data_valid_adjacent))) begin
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(!start_sync_channels & dma_valid |
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(dma_valid & dma_valid_adjacent))) begin
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if (interpolation_counter < interpolation_ratio) begin
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interpolation_counter <= interpolation_counter + 1;
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dac_int_valid_d <= 1'b0;
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dac_int_ready <= 1'b0;
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end else begin
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interpolation_counter <= 0;
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dac_int_valid_d <= 1'b1;
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dac_int_ready <= 1'b1;
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end
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end else begin
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dac_int_valid_d <= 1'b0;
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dac_int_ready <= 1'b0;
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interpolation_counter <= 0;
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end
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end
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end
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always @(posedge dac_clk) begin
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if (dma_transfer_suspend) begin
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dma_data_valid <= 1'b0;
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dma_data_valid_adjacent <= 1'b0;
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triggered <= 1'b0;
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if (dma_transfer_suspend == 1'b0) begin
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transfer <= trigger ? 1'b1 : transfer | !trigger_active;
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end else begin
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dma_data_valid <= dma_valid ? 1'b1 : dma_data_valid;
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dma_data_valid_adjacent <= dma_valid_adjacent ? 1'b1 : dma_data_valid_adjacent;
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triggered <= trigger ? 1'b1 : triggered | !trigger_active;
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transfer <= 1'b0;
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end
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if (start_sync_channels == 1'b0) begin
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transmit_ready <= triggered;
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transmit_ready <= dma_valid & transfer;
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end else begin
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transmit_ready <= (dma_data_valid & dma_data_valid_adjacent) ? triggered : ~dma_data_valid;
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transmit_ready <= dma_valid & dma_valid_adjacent & transfer;
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end
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end
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assign dac_int_valid = transmit_ready ? dac_int_valid_d : 1'b0;
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assign dma_ready = transmit_ready ? dac_int_ready : 1'b0;
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assign underflow = dac_enable & dma_ready & ~dma_valid;
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always @(posedge dac_clk) begin
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case (filter_mask)
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@ -113,7 +113,7 @@ ad_ip_parameter ad9963_adc_dmac CONFIG.SYNC_TRANSFER_START true
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ad_ip_parameter ad9963_adc_dmac CONFIG.DISABLE_DEBUG_REGISTERS $DISABLE_DMAC_DEBUG
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ad_ip_instance axi_dmac ad9963_dac_dmac_a
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ad_ip_parameter ad9963_dac_dmac_a CONFIG.DMA_TYPE_DEST 2
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ad_ip_parameter ad9963_dac_dmac_a CONFIG.DMA_TYPE_DEST 1
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ad_ip_parameter ad9963_dac_dmac_a CONFIG.DMA_TYPE_SRC 0
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ad_ip_parameter ad9963_dac_dmac_a CONFIG.DMA_AXI_PROTOCOL_SRC 1
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ad_ip_parameter ad9963_dac_dmac_a CONFIG.MAX_BYTES_PER_BURST 128
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@ -123,7 +123,7 @@ ad_ip_parameter ad9963_dac_dmac_a CONFIG.CYCLIC {true}
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ad_ip_parameter ad9963_dac_dmac_a CONFIG.DISABLE_DEBUG_REGISTERS $DISABLE_DMAC_DEBUG
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ad_ip_instance axi_dmac ad9963_dac_dmac_b
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ad_ip_parameter ad9963_dac_dmac_b CONFIG.DMA_TYPE_DEST 2
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ad_ip_parameter ad9963_dac_dmac_b CONFIG.DMA_TYPE_DEST 1
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ad_ip_parameter ad9963_dac_dmac_b CONFIG.DMA_TYPE_SRC 0
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ad_ip_parameter ad9963_dac_dmac_b CONFIG.DMA_AXI_PROTOCOL_SRC 1
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ad_ip_parameter ad9963_dac_dmac_b CONFIG.MAX_BYTES_PER_BURST 128
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@ -245,15 +245,17 @@ ad_connect axi_dac_interpolate/dac_valid_b axi_ad9963/dac_valid_q
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ad_connect axi_dac_interpolate/dac_int_data_a axi_ad9963/dac_data_i
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ad_connect axi_dac_interpolate/dac_int_data_b axi_ad9963/dac_data_q
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ad_connect ad9963_dac_dmac_a/fifo_rd_clk axi_ad9963/dac_clk
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ad_connect ad9963_dac_dmac_b/fifo_rd_clk axi_ad9963/dac_clk
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ad_connect ad9963_dac_dmac_a/m_axis_aclk axi_ad9963/dac_clk
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ad_connect ad9963_dac_dmac_b/m_axis_aclk axi_ad9963/dac_clk
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ad_connect axi_dac_interpolate/dac_data_a ad9963_dac_dmac_a/fifo_rd_dout
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ad_connect axi_dac_interpolate/dac_int_valid_a ad9963_dac_dmac_a/fifo_rd_en
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ad_connect ad9963_dac_dmac_a/fifo_rd_valid axi_dac_interpolate/dma_valid_a
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ad_connect axi_dac_interpolate/dac_data_b ad9963_dac_dmac_b/fifo_rd_dout
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ad_connect axi_dac_interpolate/dac_int_valid_b ad9963_dac_dmac_b/fifo_rd_en
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ad_connect ad9963_dac_dmac_b/fifo_rd_valid axi_dac_interpolate/dma_valid_b
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ad_connect axi_dac_interpolate/dac_data_a ad9963_dac_dmac_a/m_axis_data
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ad_connect axi_dac_interpolate/dma_ready_a ad9963_dac_dmac_a/m_axis_ready
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ad_connect axi_dac_interpolate/dac_enable_a axi_ad9963/dac_enable_i
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ad_connect ad9963_dac_dmac_a/m_axis_valid axi_dac_interpolate/dma_valid_a
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ad_connect axi_dac_interpolate/dac_data_b ad9963_dac_dmac_b/m_axis_data
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ad_connect axi_dac_interpolate/dma_ready_b ad9963_dac_dmac_b/m_axis_ready
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ad_connect axi_dac_interpolate/dac_enable_b axi_ad9963/dac_enable_q
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ad_connect ad9963_dac_dmac_b/m_axis_valid axi_dac_interpolate/dma_valid_b
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ad_connect axi_dac_interpolate/trigger_i trigger_i
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ad_connect axi_dac_interpolate/trigger_adc adc_trigger/trigger_out_la
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@ -278,7 +280,7 @@ ad_connect trigger_t adc_trigger/trigger_t
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ad_connect axi_ad9963/dac_sync_in axi_ad9963/dac_sync_out
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ad_connect axi_ad9963/adc_dovf ad9963_adc_dmac/fifo_wr_overflow
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ad_connect axi_ad9963/dac_dunf ad9963_dac_dmac_a/fifo_rd_underflow
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ad_connect axi_ad9963/dac_dunf axi_dac_interpolate/underflow
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# interconnects
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