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ad9081_fmca_ebz: Whitespace cleanup 

Clear extra lines and whitespaces at end of lines.
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Laszlo Nagy 2020-04-21 16:17:01 +01:00 committed by Laszlo Nagy
parent 7df4caf8b0
commit e112a03d85
1 changed files with 13 additions and 27 deletions
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14
projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl
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@ -18,7 +18,6 @@
# [RX/TX]_NUM_LINKS : Number of links, matches numer of MxFE devices # [RX/TX]_NUM_LINKS : Number of links, matches numer of MxFE devices
# #
# Common parameter for TX and RX # Common parameter for TX and RX
set JESD_MODE $ad_project_params(JESD_MODE) set JESD_MODE $ad_project_params(JESD_MODE)
@ -49,7 +48,6 @@ set RX_JESD_L $ad_project_params(RX_JESD_L)
set RX_JESD_S $ad_project_params(RX_JESD_S) set RX_JESD_S $ad_project_params(RX_JESD_S)
set RX_JESD_NP $ad_project_params(RX_JESD_NP) set RX_JESD_NP $ad_project_params(RX_JESD_NP)
set RX_NUM_OF_LANES [expr $RX_JESD_L * $RX_NUM_LINKS] set RX_NUM_OF_LANES [expr $RX_JESD_L * $RX_NUM_LINKS]
set RX_NUM_OF_CONVERTERS [expr $RX_JESD_M * $RX_NUM_LINKS] set RX_NUM_OF_CONVERTERS [expr $RX_JESD_M * $RX_NUM_LINKS]
set RX_SAMPLES_PER_FRAME $RX_JESD_S set RX_SAMPLES_PER_FRAME $RX_JESD_S
@ -57,7 +55,6 @@ set RX_SAMPLE_WIDTH $RX_JESD_NP
set RX_SAMPLES_PER_CHANNEL [expr $RX_NUM_OF_LANES * 8*$DATAPATH_WIDTH / ($RX_NUM_OF_CONVERTERS * $RX_SAMPLE_WIDTH)] set RX_SAMPLES_PER_CHANNEL [expr $RX_NUM_OF_LANES * 8*$DATAPATH_WIDTH / ($RX_NUM_OF_CONVERTERS * $RX_SAMPLE_WIDTH)]
# TX parameters # TX parameters
set TX_NUM_LINKS $ad_project_params(TX_NUM_LINKS) set TX_NUM_LINKS $ad_project_params(TX_NUM_LINKS)
@ -139,7 +136,6 @@ ad_ip_instance proc_sys_reset tx_device_clk_rstgen
ad_connect tx_device_clk tx_device_clk_rstgen/slowest_sync_clk ad_connect tx_device_clk tx_device_clk_rstgen/slowest_sync_clk
ad_connect $sys_cpu_resetn tx_device_clk_rstgen/ext_reset_in ad_connect $sys_cpu_resetn tx_device_clk_rstgen/ext_reset_in
# Common PHYs # Common PHYs
# Use two instances since they are located on different SLRS # Use two instances since they are located on different SLRS
set rx_rate $ad_project_params(RX_RATE) set rx_rate $ad_project_params(RX_RATE)
@ -187,7 +183,6 @@ ad_ip_instance jesd204_phy jesd204_phy_126 [list \
# adc peripherals # adc peripherals
adi_axi_jesd204_rx_create axi_mxfe_rx_jesd $RX_NUM_OF_LANES $RX_NUM_LINKS $ENCODER_SEL adi_axi_jesd204_rx_create axi_mxfe_rx_jesd $RX_NUM_OF_LANES $RX_NUM_LINKS $ENCODER_SEL
ad_ip_parameter axi_mxfe_rx_jesd/rx CONFIG.SYSREF_IOB false ad_ip_parameter axi_mxfe_rx_jesd/rx CONFIG.SYSREF_IOB false
@ -221,8 +216,6 @@ ad_ip_parameter axi_mxfe_rx_dma CONFIG.CYCLIC 0
ad_ip_parameter axi_mxfe_rx_dma CONFIG.DMA_DATA_WIDTH_SRC $adc_dma_data_width ad_ip_parameter axi_mxfe_rx_dma CONFIG.DMA_DATA_WIDTH_SRC $adc_dma_data_width
ad_ip_parameter axi_mxfe_rx_dma CONFIG.DMA_DATA_WIDTH_DEST $adc_dma_data_width ad_ip_parameter axi_mxfe_rx_dma CONFIG.DMA_DATA_WIDTH_DEST $adc_dma_data_width
# dac peripherals # dac peripherals
adi_axi_jesd204_tx_create axi_mxfe_tx_jesd $TX_NUM_OF_LANES $TX_NUM_LINKS $ENCODER_SEL adi_axi_jesd204_tx_create axi_mxfe_tx_jesd $TX_NUM_OF_LANES $TX_NUM_LINKS $ENCODER_SEL
@ -276,11 +269,9 @@ for {set i 0} {$i < [expr max($TX_NUM_OF_LANES,$RX_NUM_OF_LANES)]} {incr i} {
ad_xcvrpll axi_mxfe_tx_xcvr/up_pll_rst util_mxfe_xcvr/up_qpll_rst_* ad_xcvrpll axi_mxfe_tx_xcvr/up_pll_rst util_mxfe_xcvr/up_qpll_rst_*
ad_xcvrpll axi_mxfe_rx_xcvr/up_pll_rst util_mxfe_xcvr/up_cpll_rst_* ad_xcvrpll axi_mxfe_rx_xcvr/up_pll_rst util_mxfe_xcvr/up_cpll_rst_*
ad_connect $sys_cpu_resetn util_mxfe_xcvr/up_rstn ad_connect $sys_cpu_resetn util_mxfe_xcvr/up_rstn
ad_connect $sys_cpu_clk util_mxfe_xcvr/up_clk ad_connect $sys_cpu_clk util_mxfe_xcvr/up_clk
# connections (adc) # connections (adc)
ad_xcvrcon util_mxfe_xcvr axi_mxfe_rx_xcvr axi_mxfe_rx_jesd {} rx_device_clk ad_xcvrcon util_mxfe_xcvr axi_mxfe_rx_xcvr axi_mxfe_rx_jesd {} rx_device_clk
@ -391,7 +382,6 @@ for {set j 0} {$j < $RX_NUM_OF_LANES} {incr j} {
ad_connect axi_mxfe_rx_jesd/rx_phy$j $logic_lane($j) ad_connect axi_mxfe_rx_jesd/rx_phy$j $logic_lane($j)
} }
ad_connect rx_sysref_0 axi_mxfe_rx_jesd/sysref ad_connect rx_sysref_0 axi_mxfe_rx_jesd/sysref
} }
@ -416,7 +406,6 @@ ad_connect mxfe_adc_fifo/dma_wdata axi_mxfe_rx_dma/s_axis_data
ad_connect mxfe_adc_fifo/dma_wready axi_mxfe_rx_dma/s_axis_ready ad_connect mxfe_adc_fifo/dma_wready axi_mxfe_rx_dma/s_axis_ready
ad_connect mxfe_adc_fifo/dma_xfer_req axi_mxfe_rx_dma/s_axis_xfer_req ad_connect mxfe_adc_fifo/dma_xfer_req axi_mxfe_rx_dma/s_axis_xfer_req
# connect dac dataflow # connect dac dataflow
# #
if {$ADI_PHY_SEL == 0} { if {$ADI_PHY_SEL == 0} {
@ -444,7 +433,6 @@ for {set i 0} {$i < 4} {incr i} {
ad_connect jesd204_phy_126/txp_out txp_out_slice_[expr $i+4]/Din ad_connect jesd204_phy_126/txp_out txp_out_slice_[expr $i+4]/Din
} }
for {set i 0} {$i < $MAX_TX_LANES} {incr i} { for {set i 0} {$i < $MAX_TX_LANES} {incr i} {
ad_connect txn_out_slice_$i/Dout tx_data_${i}_n ad_connect txn_out_slice_$i/Dout tx_data_${i}_n
ad_connect txp_out_slice_$i/Dout tx_data_${i}_p ad_connect txp_out_slice_$i/Dout tx_data_${i}_p
@ -492,7 +480,6 @@ ad_connect mxfe_dac_fifo/dac_dunf tx_mxfe_tpl_core/dac_dunf
create_bd_port -dir I dac_fifo_bypass create_bd_port -dir I dac_fifo_bypass
ad_connect mxfe_dac_fifo/bypass dac_fifo_bypass ad_connect mxfe_dac_fifo/bypass dac_fifo_bypass
# interconnect (cpu) # interconnect (cpu)
if {$ADI_PHY_SEL == 1} { if {$ADI_PHY_SEL == 1} {
ad_cpu_interconnect 0x44a60000 axi_mxfe_rx_xcvr ad_cpu_interconnect 0x44a60000 axi_mxfe_rx_xcvr
@ -527,7 +514,6 @@ ad_cpu_interrupt ps-12 mb-13 axi_mxfe_tx_dma/irq
ad_cpu_interrupt ps-11 mb-14 axi_mxfe_rx_jesd/irq ad_cpu_interrupt ps-11 mb-14 axi_mxfe_rx_jesd/irq
ad_cpu_interrupt ps-10 mb-15 axi_mxfe_tx_jesd/irq ad_cpu_interrupt ps-10 mb-15 axi_mxfe_tx_jesd/irq
if {$ADI_PHY_SEL == 1} { if {$ADI_PHY_SEL == 1} {
# Create dummy outputs for unused Tx lanes # Create dummy outputs for unused Tx lanes
for {set i $TX_NUM_OF_LANES} {$i < 8} {incr i} { for {set i $TX_NUM_OF_LANES} {$i < 8} {incr i} {