spi_engine_execution: Optimize SDI latch delay logic
parent
137c31db1d
commit
e0d47645de
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@ -141,7 +141,7 @@ wire sdi_enabled = cmd_d1[9];
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reg [(DATA_WIDTH-1):0] data_sdo_shift = 'h0;
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reg [(DATA_WIDTH-1):0] data_sdo_shift = 'h0;
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reg [4:0] trigger_rx_d = 5'b0;
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reg [SDI_DELAY+1:0] trigger_rx_d = {(SDI_DELAY+1){1'b0}};
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wire [1:0] inst = cmd[13:12];
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wire [1:0] inst = cmd[13:12];
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wire [1:0] inst_d1 = cmd_d1[13:12];
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wire [1:0] inst_d1 = cmd_d1[13:12];
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@ -391,13 +391,10 @@ assign sdo_int_s = data_sdo_shift[DATA_WIDTH-1];
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always @(posedge clk) begin
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always @(posedge clk) begin
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trigger_rx_d[0] <= trigger_rx;
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trigger_rx_d[0] <= trigger_rx;
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trigger_rx_d[4:1] <= trigger_rx_d[3:0];
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trigger_rx_d[SDI_DELAY+1:1] <= trigger_rx_d[SDI_DELAY:0];
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end
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end
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assign trigger_rx_s = (SDI_DELAY == 2'b00) ? trigger_rx_d[1] :
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assign trigger_rx_s = trigger_rx_d[SDI_DELAY+1];
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(SDI_DELAY == 2'b01) ? trigger_rx_d[2] :
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(SDI_DELAY == 2'b10) ? trigger_rx_d[3] :
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(SDI_DELAY == 2'b11) ? trigger_rx_d[4] : trigger_rx_d[1];
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// Load the serial data into SDI shift register(s), then link it to the output
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// Load the serial data into SDI shift register(s), then link it to the output
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// register of the module
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// register of the module
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