From e0b5044aa305136b9a84544c88cc2dacf6043ed8 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Thu, 20 Aug 2015 18:12:04 +0200 Subject: [PATCH] axi_dmac: Disable dummy AXI ports for Xilinx IPI The memory mapped AXI interfaces for the AXI-DMAC are uni-directional. Which means they are either write-only or read-only. Unfortunately the Altera tools can't handle this, so we had to add dummy signals for the other direction. The Xilinx tools on the other hand handle uni-directional AXI interfaces and in fact IPI can do a better job and use less resources when creating the AXI interconnects when it knows that the interface is uni-directional. So always disable the dummy ports for the IPI package. Signed-off-by: Lars-Peter Clausen --- library/axi_dmac/axi_dmac_ip.tcl | 40 ++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/library/axi_dmac/axi_dmac_ip.tcl b/library/axi_dmac/axi_dmac_ip.tcl index 757fc3bcb..4d6aafc86 100644 --- a/library/axi_dmac/axi_dmac_ip.tcl +++ b/library/axi_dmac/axi_dmac_ip.tcl @@ -101,6 +101,46 @@ foreach p $dummy_axi_ports { adi_set_ports_dependency $p "0" } +# These are in the design to keep the Altera tools happy which can't handle +# uni-directional AXI interfaces. The Xilinx tools can and do a better job when +# they know that the interface is uni-directional, so disable the ports. +set dummy_axi_ports [list \ + "m_dest_axi_arvalid" \ + "m_dest_axi_arready" \ + "m_dest_axi_araddr" \ + "m_dest_axi_arlen" \ + "m_dest_axi_arsize" \ + "m_dest_axi_arburst" \ + "m_dest_axi_arcache" \ + "m_dest_axi_arprot" \ + "m_dest_axi_rready" \ + "m_dest_axi_rvalid" \ + "m_dest_axi_rresp" \ + "m_dest_axi_rdata" \ + "m_src_axi_awvalid" \ + "m_src_axi_awready" \ + "m_src_axi_awvalid" \ + "m_src_axi_awaddr" \ + "m_src_axi_awlen" \ + "m_src_axi_awsize" \ + "m_src_axi_awburst" \ + "m_src_axi_awcache" \ + "m_src_axi_awprot" \ + "m_src_axi_wvalid" \ + "m_src_axi_wready" \ + "m_src_axi_wvalid" \ + "m_src_axi_wdata" \ + "m_src_axi_wstrb" \ + "m_src_axi_wlast" \ + "m_src_axi_bready" \ + "m_src_axi_bvalid" \ + "m_src_axi_bresp" \ +] + +foreach p $dummy_axi_ports { + adi_set_ports_dependency $p "0" +} + adi_add_bus "fifo_wr" "slave" \ "analog.com:interface:fifo_wr_rtl:1.0" \ "analog.com:interface:fifo_wr:1.0" \